1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * All rights reserved. 5 * Copyright 2021 NXP 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef PLATFORM_CONFIG_H 31 #define PLATFORM_CONFIG_H 32 33 #include <mm/generic_ram_layout.h> 34 35 #define STACK_ALIGNMENT 64 36 37 /* console uart define */ 38 #define CONSOLE_UART_BASE UART0_BASE 39 40 /* Platform specific defines */ 41 #if defined(PLATFORM_FLAVOR_ls1012ardb) 42 /* DUART 1 */ 43 #define UART0_BASE 0x021C0500 44 #define GIC_BASE 0x01400000 45 #define GICC_OFFSET 0x2000 46 #define GICD_OFFSET 0x1000 47 #define CAAM_BASE 0x01700000 48 #define CAAM_SIZE 0x100000 49 #endif 50 51 #if defined(PLATFORM_FLAVOR_ls1043ardb) 52 #define UART0_BASE 0x021C0500 53 #define GIC_BASE 0x01400000 54 #define GICC_OFFSET_REV1 0x2000 55 #define GICD_OFFSET_REV1 0x1000 56 #define GICC_OFFSET_REV1_1 0x20000 57 #define GICD_OFFSET_REV1_1 0x10000 58 #define CAAM_BASE 0x01700000 59 #define CAAM_SIZE 0x100000 60 #define DCFG_BASE 0x01EE0000 61 #define DCFG_SVR_OFFSET 0xA4 62 #endif 63 64 #if defined(PLATFORM_FLAVOR_ls1046ardb) 65 /* DUART 1 */ 66 #define UART0_BASE 0x021C0500 67 #define GIC_BASE 0x01400000 68 #define GICC_OFFSET 0x20000 69 #define GICD_OFFSET 0x10000 70 #define CAAM_BASE 0x01700000 71 #define CAAM_SIZE 0x100000 72 #endif 73 74 #if defined(PLATFORM_FLAVOR_ls1088ardb) 75 /* DUART 1 */ 76 #define UART0_BASE 0x021C0500 77 #define GIC_BASE 0x06000000 78 #define GICC_OFFSET 0x0 79 #define GICD_OFFSET 0x0 80 #define CAAM_BASE 0x08000000 81 #define CAAM_SIZE 0x100000 82 #endif 83 84 #if defined(PLATFORM_FLAVOR_ls2088ardb) 85 /* DUART 1 */ 86 #define UART0_BASE 0x021C0600 87 #define GIC_BASE 0x06000000 88 #define GICC_OFFSET 0x0 89 #define GICD_OFFSET 0x0 90 #define CAAM_BASE 0x08000000 91 #define CAAM_SIZE 0x100000 92 #endif 93 94 #if defined(PLATFORM_FLAVOR_ls1028ardb) 95 /* DUART 1 */ 96 #define UART0_BASE 0x021C0500 97 #define GIC_BASE 0x06000000 98 #define GICC_OFFSET 0x0 99 #define GICD_OFFSET 0x0 100 #define CAAM_BASE 0x08000000 101 #define CAAM_SIZE 0x100000 102 #endif 103 104 #if defined(PLATFORM_FLAVOR_lx2160ardb) 105 /* DUART 1 */ 106 #define UART0_BASE 0x021C0000 107 #define GIC_BASE 0x06000000 108 #define GICC_OFFSET 0x0 109 #define GICD_OFFSET 0x0 110 #define CAAM_BASE 0x08000000 111 #define CAAM_SIZE 0x100000 112 #endif 113 114 #if defined(PLATFORM_FLAVOR_lx2160aqds) 115 /* DUART 1 */ 116 #define UART0_BASE 0x021C0000 117 #define GIC_BASE 0x06000000 118 #define GICC_OFFSET 0x0 119 #define GICD_OFFSET 0x0 120 #define CAAM_BASE 0x08000000 121 #define CAAM_SIZE 0x100000 122 #endif 123 124 #endif /*PLATFORM_CONFIG_H*/ 125