1 //***************************************************************************** 2 // 3 // hw_memmap.h - Macros defining the memory map of Stellaris. 4 // 5 // Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 9453 of the Stellaris Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_MEMMAP_H__ 41 #define __HW_MEMMAP_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the base address of the memories and 46 // peripherals. 47 // 48 //***************************************************************************** 49 #define FLASH_BASE 0x00000000 // FLASH memory 50 #define SRAM_BASE 0x20000000 // SRAM memory 51 #define WATCHDOG0_BASE 0x40000000 // Watchdog0 52 #define WATCHDOG1_BASE 0x40001000 // Watchdog1 53 #define GPIO_PORTA_BASE 0x40004000 // GPIO Port A 54 #define GPIO_PORTB_BASE 0x40005000 // GPIO Port B 55 #define GPIO_PORTC_BASE 0x40006000 // GPIO Port C 56 #define GPIO_PORTD_BASE 0x40007000 // GPIO Port D 57 #define SSI0_BASE 0x40008000 // SSI0 58 #define SSI1_BASE 0x40009000 // SSI1 59 #define SSI2_BASE 0x4000A000 // SSI2 60 #define SSI3_BASE 0x4000B000 // SSI3 61 #define UART0_BASE 0x4000C000 // UART0 62 #define UART1_BASE 0x4000D000 // UART1 63 #define UART2_BASE 0x4000E000 // UART2 64 #define UART3_BASE 0x4000F000 // UART3 65 #define UART4_BASE 0x40010000 // UART4 66 #define UART5_BASE 0x40011000 // UART5 67 #define UART6_BASE 0x40012000 // UART6 68 #define UART7_BASE 0x40013000 // UART7 69 #define I2C0_MASTER_BASE 0x40020000 // I2C0 Master 70 #define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave 71 #define I2C1_MASTER_BASE 0x40021000 // I2C1 Master 72 #define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave 73 #define I2C2_MASTER_BASE 0x40022000 // I2C2 Master 74 #define I2C2_SLAVE_BASE 0x40022800 // I2C2 Slave 75 #define I2C3_MASTER_BASE 0x40023000 // I2C3 Master 76 #define I2C3_SLAVE_BASE 0x40023800 // I2C3 Slave 77 #define GPIO_PORTE_BASE 0x40024000 // GPIO Port E 78 #define GPIO_PORTF_BASE 0x40025000 // GPIO Port F 79 #define GPIO_PORTG_BASE 0x40026000 // GPIO Port G 80 #define GPIO_PORTH_BASE 0x40027000 // GPIO Port H 81 #define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM) 82 #define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM) 83 #define QEI0_BASE 0x4002C000 // QEI0 84 #define QEI1_BASE 0x4002D000 // QEI1 85 #define TIMER0_BASE 0x40030000 // Timer0 86 #define TIMER1_BASE 0x40031000 // Timer1 87 #define TIMER2_BASE 0x40032000 // Timer2 88 #define TIMER3_BASE 0x40033000 // Timer3 89 #define TIMER4_BASE 0x40034000 // Timer4 90 #define TIMER5_BASE 0x40035000 // Timer5 91 #define WTIMER0_BASE 0x40036000 // Wide Timer0 92 #define WTIMER1_BASE 0x40037000 // Wide Timer1 93 #define ADC0_BASE 0x40038000 // ADC0 94 #define ADC1_BASE 0x40039000 // ADC1 95 #define COMP_BASE 0x4003C000 // Analog comparators 96 #define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J 97 #define CAN0_BASE 0x40040000 // CAN0 98 #define CAN1_BASE 0x40041000 // CAN1 99 #define CAN2_BASE 0x40042000 // CAN2 100 #define ETH_BASE 0x40048000 // Ethernet 101 #define MAC_BASE 0x40048000 // Ethernet 102 #define WTIMER2_BASE 0x4004C000 // Wide Timer2 103 #define WTIMER3_BASE 0x4004D000 // Wide Timer3 104 #define WTIMER4_BASE 0x4004E000 // Wide Timer4 105 #define WTIMER5_BASE 0x4004F000 // Wide Timer5 106 #define USB0_BASE 0x40050000 // USB 0 Controller 107 #define I2S0_BASE 0x40054000 // I2S0 108 #define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed) 109 #define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed) 110 #define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed) 111 #define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed) 112 #define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed) 113 #define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed) 114 #define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed) 115 #define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed) 116 #define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed) 117 #define GPIO_PORTK_BASE 0x40061000 // GPIO Port K 118 #define GPIO_PORTL_BASE 0x40062000 // GPIO Port L 119 #define GPIO_PORTM_BASE 0x40063000 // GPIO Port M 120 #define GPIO_PORTN_BASE 0x40064000 // GPIO Port N 121 #define GPIO_PORTP_BASE 0x40065000 // GPIO Port P 122 #define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q 123 #define LPC0_BASE 0x40080000 // Low Pin Count Interface (LPC) 124 #define FAN0_BASE 0x40084000 // Fan Control (FAN) 125 #define EEPROM_BASE 0x400AF000 // EEPROM memory 126 #define PECI0_BASE 0x400B0000 // Platform Environment Control 127 // Interface (PECI) 128 #define I2C4_MASTER_BASE 0x400C0000 // I2C4 Master 129 #define I2C4_SLAVE_BASE 0x400C0800 // I2C4 Slave 130 #define I2C5_MASTER_BASE 0x400C1000 // I2C5 Master 131 #define I2C5_SLAVE_BASE 0x400C1800 // I2C5 Slave 132 #define EPI0_BASE 0x400D0000 // EPI0 133 #define SYSEXC_BASE 0x400F9000 // System Exception Module 134 #define HIB_BASE 0x400FC000 // Hibernation Module 135 #define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller 136 #define SYSCTL_BASE 0x400FE000 // System Control 137 #define UDMA_BASE 0x400FF000 // uDMA Controller 138 139 #if !LK 140 #define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell 141 #define DWT_BASE 0xE0001000 // Data Watchpoint and Trace 142 #define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint 143 #define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl 144 #define TPIU_BASE 0xE0040000 // Trace Port Interface Unit 145 #endif 146 147 //***************************************************************************** 148 // 149 // The following definitions are deprecated. 150 // 151 //***************************************************************************** 152 #ifndef DEPRECATED 153 154 //***************************************************************************** 155 // 156 // The following are deprecated defines for the base address of the memories 157 // and peripherals. 158 // 159 //***************************************************************************** 160 #define WATCHDOG_BASE 0x40000000 // Watchdog 161 #define SSI_BASE 0x40008000 // SSI 162 #define I2C_MASTER_BASE 0x40020000 // I2C Master 163 #define I2C_SLAVE_BASE 0x40020800 // I2C Slave 164 #define PWM_BASE 0x40028000 // PWM 165 #define QEI_BASE 0x4002C000 // QEI 166 #define ADC_BASE 0x40038000 // ADC 167 168 #endif 169 170 #endif // __HW_MEMMAP_H__ 171