1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2000, 2004, 2005  MIPS Technologies, Inc.
4  *	All rights reserved.
5  *	Authors: Carsten Langgaard <carstenl@mips.com>
6  *		 Maciej W. Rozycki <macro@mips.com>
7  * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
8  */
9 #ifndef _ASM_GT64120_H
10 #define _ASM_GT64120_H
11 
12 #include <asm/addrspace.h>
13 #include <asm/byteorder.h>
14 
15 #define MSK(n)			((1 << (n)) - 1)
16 
17 /*
18  *  Register offset addresses
19  */
20 /* CPU Configuration.  */
21 #define GT_CPU_OFS		0x000
22 
23 #define GT_MULTI_OFS		0x120
24 
25 /* CPU Address Decode.	*/
26 #define GT_SCS10LD_OFS		0x008
27 #define GT_SCS10HD_OFS		0x010
28 #define GT_SCS32LD_OFS		0x018
29 #define GT_SCS32HD_OFS		0x020
30 #define GT_CS20LD_OFS		0x028
31 #define GT_CS20HD_OFS		0x030
32 #define GT_CS3BOOTLD_OFS	0x038
33 #define GT_CS3BOOTHD_OFS	0x040
34 #define GT_PCI0IOLD_OFS		0x048
35 #define GT_PCI0IOHD_OFS		0x050
36 #define GT_PCI0M0LD_OFS		0x058
37 #define GT_PCI0M0HD_OFS		0x060
38 #define GT_ISD_OFS		0x068
39 
40 #define GT_PCI0M1LD_OFS		0x080
41 #define GT_PCI0M1HD_OFS		0x088
42 #define GT_PCI1IOLD_OFS		0x090
43 #define GT_PCI1IOHD_OFS		0x098
44 #define GT_PCI1M0LD_OFS		0x0a0
45 #define GT_PCI1M0HD_OFS		0x0a8
46 #define GT_PCI1M1LD_OFS		0x0b0
47 #define GT_PCI1M1HD_OFS		0x0b8
48 #define GT_PCI1M1LD_OFS		0x0b0
49 #define GT_PCI1M1HD_OFS		0x0b8
50 
51 #define GT_SCS10AR_OFS		0x0d0
52 #define GT_SCS32AR_OFS		0x0d8
53 #define GT_CS20R_OFS		0x0e0
54 #define GT_CS3BOOTR_OFS		0x0e8
55 
56 #define GT_PCI0IOREMAP_OFS	0x0f0
57 #define GT_PCI0M0REMAP_OFS	0x0f8
58 #define GT_PCI0M1REMAP_OFS	0x100
59 #define GT_PCI1IOREMAP_OFS	0x108
60 #define GT_PCI1M0REMAP_OFS	0x110
61 #define GT_PCI1M1REMAP_OFS	0x118
62 
63 /* CPU Error Report.  */
64 #define GT_CPUERR_ADDRLO_OFS	0x070
65 #define GT_CPUERR_ADDRHI_OFS	0x078
66 
67 #define GT_CPUERR_DATALO_OFS	0x128			/* GT-64120A only  */
68 #define GT_CPUERR_DATAHI_OFS	0x130			/* GT-64120A only  */
69 #define GT_CPUERR_PARITY_OFS	0x138			/* GT-64120A only  */
70 
71 /* CPU Sync Barrier.  */
72 #define GT_PCI0SYNC_OFS		0x0c0
73 #define GT_PCI1SYNC_OFS		0x0c8
74 
75 /* SDRAM and Device Address Decode.  */
76 #define GT_SCS0LD_OFS		0x400
77 #define GT_SCS0HD_OFS		0x404
78 #define GT_SCS1LD_OFS		0x408
79 #define GT_SCS1HD_OFS		0x40c
80 #define GT_SCS2LD_OFS		0x410
81 #define GT_SCS2HD_OFS		0x414
82 #define GT_SCS3LD_OFS		0x418
83 #define GT_SCS3HD_OFS		0x41c
84 #define GT_CS0LD_OFS		0x420
85 #define GT_CS0HD_OFS		0x424
86 #define GT_CS1LD_OFS		0x428
87 #define GT_CS1HD_OFS		0x42c
88 #define GT_CS2LD_OFS		0x430
89 #define GT_CS2HD_OFS		0x434
90 #define GT_CS3LD_OFS		0x438
91 #define GT_CS3HD_OFS		0x43c
92 #define GT_BOOTLD_OFS		0x440
93 #define GT_BOOTHD_OFS		0x444
94 
95 #define GT_ADERR_OFS		0x470
96 
97 /* SDRAM Configuration.	 */
98 #define GT_SDRAM_CFG_OFS	0x448
99 
100 #define GT_SDRAM_OPMODE_OFS	0x474
101 #define GT_SDRAM_BM_OFS		0x478
102 #define GT_SDRAM_ADDRDECODE_OFS 0x47c
103 
104 /* SDRAM Parameters.  */
105 #define GT_SDRAM_B0_OFS		0x44c
106 #define GT_SDRAM_B1_OFS		0x450
107 #define GT_SDRAM_B2_OFS		0x454
108 #define GT_SDRAM_B3_OFS		0x458
109 
110 /* Device Parameters.  */
111 #define GT_DEV_B0_OFS		0x45c
112 #define GT_DEV_B1_OFS		0x460
113 #define GT_DEV_B2_OFS		0x464
114 #define GT_DEV_B3_OFS		0x468
115 #define GT_DEV_BOOT_OFS		0x46c
116 
117 /* ECC.	 */
118 #define GT_ECC_ERRDATALO	0x480			/* GT-64120A only  */
119 #define GT_ECC_ERRDATAHI	0x484			/* GT-64120A only  */
120 #define GT_ECC_MEM		0x488			/* GT-64120A only  */
121 #define GT_ECC_CALC		0x48c			/* GT-64120A only  */
122 #define GT_ECC_ERRADDR		0x490			/* GT-64120A only  */
123 
124 /* DMA Record.	*/
125 #define GT_DMA0_CNT_OFS		0x800
126 #define GT_DMA1_CNT_OFS		0x804
127 #define GT_DMA2_CNT_OFS		0x808
128 #define GT_DMA3_CNT_OFS		0x80c
129 #define GT_DMA0_SA_OFS		0x810
130 #define GT_DMA1_SA_OFS		0x814
131 #define GT_DMA2_SA_OFS		0x818
132 #define GT_DMA3_SA_OFS		0x81c
133 #define GT_DMA0_DA_OFS		0x820
134 #define GT_DMA1_DA_OFS		0x824
135 #define GT_DMA2_DA_OFS		0x828
136 #define GT_DMA3_DA_OFS		0x82c
137 #define GT_DMA0_NEXT_OFS	0x830
138 #define GT_DMA1_NEXT_OFS	0x834
139 #define GT_DMA2_NEXT_OFS	0x838
140 #define GT_DMA3_NEXT_OFS	0x83c
141 
142 #define GT_DMA0_CUR_OFS		0x870
143 #define GT_DMA1_CUR_OFS		0x874
144 #define GT_DMA2_CUR_OFS		0x878
145 #define GT_DMA3_CUR_OFS		0x87c
146 
147 /* DMA Channel Control.	 */
148 #define GT_DMA0_CTRL_OFS	0x840
149 #define GT_DMA1_CTRL_OFS	0x844
150 #define GT_DMA2_CTRL_OFS	0x848
151 #define GT_DMA3_CTRL_OFS	0x84c
152 
153 /* DMA Arbiter.	 */
154 #define GT_DMA_ARB_OFS		0x860
155 
156 /* Timer/Counter.  */
157 #define GT_TC0_OFS		0x850
158 #define GT_TC1_OFS		0x854
159 #define GT_TC2_OFS		0x858
160 #define GT_TC3_OFS		0x85c
161 
162 #define GT_TC_CONTROL_OFS	0x864
163 
164 /* PCI Internal.  */
165 #define GT_PCI0_CMD_OFS		0xc00
166 #define GT_PCI0_TOR_OFS		0xc04
167 #define GT_PCI0_BS_SCS10_OFS	0xc08
168 #define GT_PCI0_BS_SCS32_OFS	0xc0c
169 #define GT_PCI0_BS_CS20_OFS	0xc10
170 #define GT_PCI0_BS_CS3BT_OFS	0xc14
171 
172 #define GT_PCI1_IACK_OFS	0xc30
173 #define GT_PCI0_IACK_OFS	0xc34
174 
175 #define GT_PCI0_BARE_OFS	0xc3c
176 #define GT_PCI0_PREFMBR_OFS	0xc40
177 
178 #define GT_PCI0_SCS10_BAR_OFS	0xc48
179 #define GT_PCI0_SCS32_BAR_OFS	0xc4c
180 #define GT_PCI0_CS20_BAR_OFS	0xc50
181 #define GT_PCI0_CS3BT_BAR_OFS	0xc54
182 #define GT_PCI0_SSCS10_BAR_OFS	0xc58
183 #define GT_PCI0_SSCS32_BAR_OFS	0xc5c
184 
185 #define GT_PCI0_SCS3BT_BAR_OFS	0xc64
186 
187 #define GT_PCI1_CMD_OFS		0xc80
188 #define GT_PCI1_TOR_OFS		0xc84
189 #define GT_PCI1_BS_SCS10_OFS	0xc88
190 #define GT_PCI1_BS_SCS32_OFS	0xc8c
191 #define GT_PCI1_BS_CS20_OFS	0xc90
192 #define GT_PCI1_BS_CS3BT_OFS	0xc94
193 
194 #define GT_PCI1_BARE_OFS	0xcbc
195 #define GT_PCI1_PREFMBR_OFS	0xcc0
196 
197 #define GT_PCI1_SCS10_BAR_OFS	0xcc8
198 #define GT_PCI1_SCS32_BAR_OFS	0xccc
199 #define GT_PCI1_CS20_BAR_OFS	0xcd0
200 #define GT_PCI1_CS3BT_BAR_OFS	0xcd4
201 #define GT_PCI1_SSCS10_BAR_OFS	0xcd8
202 #define GT_PCI1_SSCS32_BAR_OFS	0xcdc
203 
204 #define GT_PCI1_SCS3BT_BAR_OFS	0xce4
205 
206 #define GT_PCI1_CFGADDR_OFS	0xcf0
207 #define GT_PCI1_CFGDATA_OFS	0xcf4
208 #define GT_PCI0_CFGADDR_OFS	0xcf8
209 #define GT_PCI0_CFGDATA_OFS	0xcfc
210 
211 /* Interrupts.	*/
212 #define GT_INTRCAUSE_OFS	0xc18
213 #define GT_INTRMASK_OFS		0xc1c
214 
215 #define GT_PCI0_ICMASK_OFS	0xc24
216 #define GT_PCI0_SERR0MASK_OFS	0xc28
217 
218 #define GT_CPU_INTSEL_OFS	0xc70
219 #define GT_PCI0_INTSEL_OFS	0xc74
220 
221 #define GT_HINTRCAUSE_OFS	0xc98
222 #define GT_HINTRMASK_OFS	0xc9c
223 
224 #define GT_PCI0_HICMASK_OFS	0xca4
225 #define GT_PCI1_SERR1MASK_OFS	0xca8
226 
227 
228 /*
229  * I2O Support Registers
230  */
231 #define INBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x010
232 #define INBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x014
233 #define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x018
234 #define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x01c
235 #define INBOUND_DOORBELL_REGISTER_PCI_SIDE		0x020
236 #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x024
237 #define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x028
238 #define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE		0x02c
239 #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x030
240 #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x034
241 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x040
242 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x044
243 #define QUEUE_CONTROL_REGISTER_PCI_SIDE			0x050
244 #define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE		0x054
245 #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x060
246 #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x064
247 #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x068
248 #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x06c
249 #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x070
250 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x074
251 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x078
252 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x07c
253 
254 #define INBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1c10
255 #define INBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1c14
256 #define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1c18
257 #define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1c1c
258 #define INBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1c20
259 #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1c24
260 #define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1c28
261 #define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1c2c
262 #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1c30
263 #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1c34
264 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	0x1c40
265 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	0x1c44
266 #define QUEUE_CONTROL_REGISTER_CPU_SIDE			0x1c50
267 #define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE		0x1c54
268 #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	0x1c60
269 #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	0x1c64
270 #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	0x1c68
271 #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	0x1c6c
272 #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	0x1c70
273 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	0x1c74
274 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	0x1c78
275 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	0x1c7c
276 
277 /*
278  *  Register encodings
279  */
280 #define GT_CPU_ENDIAN_SHF	12
281 #define GT_CPU_ENDIAN_MSK	(MSK(1) << GT_CPU_ENDIAN_SHF)
282 #define GT_CPU_ENDIAN_BIT	GT_CPU_ENDIAN_MSK
283 #define GT_CPU_WR_SHF		16
284 #define GT_CPU_WR_MSK		(MSK(1) << GT_CPU_WR_SHF)
285 #define GT_CPU_WR_BIT		GT_CPU_WR_MSK
286 #define GT_CPU_WR_DXDXDXDX	0
287 #define GT_CPU_WR_DDDD		1
288 
289 
290 #define GT_PCI_DCRM_SHF		21
291 #define GT_PCI_LD_SHF		0
292 #define GT_PCI_LD_MSK		(MSK(15) << GT_PCI_LD_SHF)
293 #define GT_PCI_HD_SHF		0
294 #define GT_PCI_HD_MSK		(MSK(7) << GT_PCI_HD_SHF)
295 #define GT_PCI_REMAP_SHF	0
296 #define GT_PCI_REMAP_MSK	(MSK(11) << GT_PCI_REMAP_SHF)
297 
298 
299 #define GT_CFGADDR_CFGEN_SHF	31
300 #define GT_CFGADDR_CFGEN_MSK	(MSK(1) << GT_CFGADDR_CFGEN_SHF)
301 #define GT_CFGADDR_CFGEN_BIT	GT_CFGADDR_CFGEN_MSK
302 
303 #define GT_CFGADDR_BUSNUM_SHF	16
304 #define GT_CFGADDR_BUSNUM_MSK	(MSK(8) << GT_CFGADDR_BUSNUM_SHF)
305 
306 #define GT_CFGADDR_DEVNUM_SHF	11
307 #define GT_CFGADDR_DEVNUM_MSK	(MSK(5) << GT_CFGADDR_DEVNUM_SHF)
308 
309 #define GT_CFGADDR_FUNCNUM_SHF	8
310 #define GT_CFGADDR_FUNCNUM_MSK	(MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
311 
312 #define GT_CFGADDR_REGNUM_SHF	2
313 #define GT_CFGADDR_REGNUM_MSK	(MSK(6) << GT_CFGADDR_REGNUM_SHF)
314 
315 
316 #define GT_SDRAM_BM_ORDER_SHF	2
317 #define GT_SDRAM_BM_ORDER_MSK	(MSK(1) << GT_SDRAM_BM_ORDER_SHF)
318 #define GT_SDRAM_BM_ORDER_BIT	GT_SDRAM_BM_ORDER_MSK
319 #define GT_SDRAM_BM_ORDER_SUB	1
320 #define GT_SDRAM_BM_ORDER_LIN	0
321 
322 #define GT_SDRAM_BM_RSVD_ALL1	0xffb
323 
324 
325 #define GT_SDRAM_ADDRDECODE_ADDR_SHF	0
326 #define GT_SDRAM_ADDRDECODE_ADDR_MSK	(MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
327 #define GT_SDRAM_ADDRDECODE_ADDR_0	0
328 #define GT_SDRAM_ADDRDECODE_ADDR_1	1
329 #define GT_SDRAM_ADDRDECODE_ADDR_2	2
330 #define GT_SDRAM_ADDRDECODE_ADDR_3	3
331 #define GT_SDRAM_ADDRDECODE_ADDR_4	4
332 #define GT_SDRAM_ADDRDECODE_ADDR_5	5
333 #define GT_SDRAM_ADDRDECODE_ADDR_6	6
334 #define GT_SDRAM_ADDRDECODE_ADDR_7	7
335 
336 
337 #define GT_SDRAM_B0_CASLAT_SHF		0
338 #define GT_SDRAM_B0_CASLAT_MSK		(MSK(2) << GT_SDRAM_B0__SHF)
339 #define GT_SDRAM_B0_CASLAT_2		1
340 #define GT_SDRAM_B0_CASLAT_3		2
341 
342 #define GT_SDRAM_B0_FTDIS_SHF		2
343 #define GT_SDRAM_B0_FTDIS_MSK		(MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
344 #define GT_SDRAM_B0_FTDIS_BIT		GT_SDRAM_B0_FTDIS_MSK
345 
346 #define GT_SDRAM_B0_SRASPRCHG_SHF	3
347 #define GT_SDRAM_B0_SRASPRCHG_MSK	(MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
348 #define GT_SDRAM_B0_SRASPRCHG_BIT	GT_SDRAM_B0_SRASPRCHG_MSK
349 #define GT_SDRAM_B0_SRASPRCHG_2		0
350 #define GT_SDRAM_B0_SRASPRCHG_3		1
351 
352 #define GT_SDRAM_B0_B0COMPAB_SHF	4
353 #define GT_SDRAM_B0_B0COMPAB_MSK	(MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
354 #define GT_SDRAM_B0_B0COMPAB_BIT	GT_SDRAM_B0_B0COMPAB_MSK
355 
356 #define GT_SDRAM_B0_64BITINT_SHF	5
357 #define GT_SDRAM_B0_64BITINT_MSK	(MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
358 #define GT_SDRAM_B0_64BITINT_BIT	GT_SDRAM_B0_64BITINT_MSK
359 #define GT_SDRAM_B0_64BITINT_2		0
360 #define GT_SDRAM_B0_64BITINT_4		1
361 
362 #define GT_SDRAM_B0_BW_SHF		6
363 #define GT_SDRAM_B0_BW_MSK		(MSK(1) << GT_SDRAM_B0_BW_SHF)
364 #define GT_SDRAM_B0_BW_BIT		GT_SDRAM_B0_BW_MSK
365 #define GT_SDRAM_B0_BW_32		0
366 #define GT_SDRAM_B0_BW_64		1
367 
368 #define GT_SDRAM_B0_BLODD_SHF		7
369 #define GT_SDRAM_B0_BLODD_MSK		(MSK(1) << GT_SDRAM_B0_BLODD_SHF)
370 #define GT_SDRAM_B0_BLODD_BIT		GT_SDRAM_B0_BLODD_MSK
371 
372 #define GT_SDRAM_B0_PAR_SHF		8
373 #define GT_SDRAM_B0_PAR_MSK		(MSK(1) << GT_SDRAM_B0_PAR_SHF)
374 #define GT_SDRAM_B0_PAR_BIT		GT_SDRAM_B0_PAR_MSK
375 
376 #define GT_SDRAM_B0_BYPASS_SHF		9
377 #define GT_SDRAM_B0_BYPASS_MSK		(MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
378 #define GT_SDRAM_B0_BYPASS_BIT		GT_SDRAM_B0_BYPASS_MSK
379 
380 #define GT_SDRAM_B0_SRAS2SCAS_SHF	10
381 #define GT_SDRAM_B0_SRAS2SCAS_MSK	(MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
382 #define GT_SDRAM_B0_SRAS2SCAS_BIT	GT_SDRAM_B0_SRAS2SCAS_MSK
383 #define GT_SDRAM_B0_SRAS2SCAS_2		0
384 #define GT_SDRAM_B0_SRAS2SCAS_3		1
385 
386 #define GT_SDRAM_B0_SIZE_SHF		11
387 #define GT_SDRAM_B0_SIZE_MSK		(MSK(1) << GT_SDRAM_B0_SIZE_SHF)
388 #define GT_SDRAM_B0_SIZE_BIT		GT_SDRAM_B0_SIZE_MSK
389 #define GT_SDRAM_B0_SIZE_16M		0
390 #define GT_SDRAM_B0_SIZE_64M		1
391 
392 #define GT_SDRAM_B0_EXTPAR_SHF		12
393 #define GT_SDRAM_B0_EXTPAR_MSK		(MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
394 #define GT_SDRAM_B0_EXTPAR_BIT		GT_SDRAM_B0_EXTPAR_MSK
395 
396 #define GT_SDRAM_B0_BLEN_SHF		13
397 #define GT_SDRAM_B0_BLEN_MSK		(MSK(1) << GT_SDRAM_B0_BLEN_SHF)
398 #define GT_SDRAM_B0_BLEN_BIT		GT_SDRAM_B0_BLEN_MSK
399 #define GT_SDRAM_B0_BLEN_8		0
400 #define GT_SDRAM_B0_BLEN_4		1
401 
402 
403 #define GT_SDRAM_CFG_REFINT_SHF		0
404 #define GT_SDRAM_CFG_REFINT_MSK		(MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
405 
406 #define GT_SDRAM_CFG_NINTERLEAVE_SHF	14
407 #define GT_SDRAM_CFG_NINTERLEAVE_MSK	(MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
408 #define GT_SDRAM_CFG_NINTERLEAVE_BIT	GT_SDRAM_CFG_NINTERLEAVE_MSK
409 
410 #define GT_SDRAM_CFG_RMW_SHF		15
411 #define GT_SDRAM_CFG_RMW_MSK		(MSK(1) << GT_SDRAM_CFG_RMW_SHF)
412 #define GT_SDRAM_CFG_RMW_BIT		GT_SDRAM_CFG_RMW_MSK
413 
414 #define GT_SDRAM_CFG_NONSTAGREF_SHF	16
415 #define GT_SDRAM_CFG_NONSTAGREF_MSK	(MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
416 #define GT_SDRAM_CFG_NONSTAGREF_BIT	GT_SDRAM_CFG_NONSTAGREF_MSK
417 
418 #define GT_SDRAM_CFG_DUPCNTL_SHF	19
419 #define GT_SDRAM_CFG_DUPCNTL_MSK	(MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
420 #define GT_SDRAM_CFG_DUPCNTL_BIT	GT_SDRAM_CFG_DUPCNTL_MSK
421 
422 #define GT_SDRAM_CFG_DUPBA_SHF		20
423 #define GT_SDRAM_CFG_DUPBA_MSK		(MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
424 #define GT_SDRAM_CFG_DUPBA_BIT		GT_SDRAM_CFG_DUPBA_MSK
425 
426 #define GT_SDRAM_CFG_DUPEOT0_SHF	21
427 #define GT_SDRAM_CFG_DUPEOT0_MSK	(MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
428 #define GT_SDRAM_CFG_DUPEOT0_BIT	GT_SDRAM_CFG_DUPEOT0_MSK
429 
430 #define GT_SDRAM_CFG_DUPEOT1_SHF	22
431 #define GT_SDRAM_CFG_DUPEOT1_MSK	(MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
432 #define GT_SDRAM_CFG_DUPEOT1_BIT	GT_SDRAM_CFG_DUPEOT1_MSK
433 
434 #define GT_SDRAM_OPMODE_OP_SHF		0
435 #define GT_SDRAM_OPMODE_OP_MSK		(MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
436 #define GT_SDRAM_OPMODE_OP_NORMAL	0
437 #define GT_SDRAM_OPMODE_OP_NOP		1
438 #define GT_SDRAM_OPMODE_OP_PRCHG	2
439 #define GT_SDRAM_OPMODE_OP_MODE		3
440 #define GT_SDRAM_OPMODE_OP_CBR		4
441 
442 #define GT_TC_CONTROL_ENTC0_SHF		0
443 #define GT_TC_CONTROL_ENTC0_MSK		(MSK(1) << GT_TC_CONTROL_ENTC0_SHF)
444 #define GT_TC_CONTROL_ENTC0_BIT		GT_TC_CONTROL_ENTC0_MSK
445 #define GT_TC_CONTROL_SELTC0_SHF	1
446 #define GT_TC_CONTROL_SELTC0_MSK	(MSK(1) << GT_TC_CONTROL_SELTC0_SHF)
447 #define GT_TC_CONTROL_SELTC0_BIT	GT_TC_CONTROL_SELTC0_MSK
448 
449 
450 #define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF	0
451 #define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK	(MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
452 #define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT	GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
453 
454 #define GT_PCI0_BARE_SWSCS32DIS_SHF	1
455 #define GT_PCI0_BARE_SWSCS32DIS_MSK	(MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
456 #define GT_PCI0_BARE_SWSCS32DIS_BIT	GT_PCI0_BARE_SWSCS32DIS_MSK
457 
458 #define GT_PCI0_BARE_SWSCS10DIS_SHF	2
459 #define GT_PCI0_BARE_SWSCS10DIS_MSK	(MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
460 #define GT_PCI0_BARE_SWSCS10DIS_BIT	GT_PCI0_BARE_SWSCS10DIS_MSK
461 
462 #define GT_PCI0_BARE_INTIODIS_SHF	3
463 #define GT_PCI0_BARE_INTIODIS_MSK	(MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
464 #define GT_PCI0_BARE_INTIODIS_BIT	GT_PCI0_BARE_INTIODIS_MSK
465 
466 #define GT_PCI0_BARE_INTMEMDIS_SHF	4
467 #define GT_PCI0_BARE_INTMEMDIS_MSK	(MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
468 #define GT_PCI0_BARE_INTMEMDIS_BIT	GT_PCI0_BARE_INTMEMDIS_MSK
469 
470 #define GT_PCI0_BARE_CS3BOOTDIS_SHF	5
471 #define GT_PCI0_BARE_CS3BOOTDIS_MSK	(MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
472 #define GT_PCI0_BARE_CS3BOOTDIS_BIT	GT_PCI0_BARE_CS3BOOTDIS_MSK
473 
474 #define GT_PCI0_BARE_CS20DIS_SHF	6
475 #define GT_PCI0_BARE_CS20DIS_MSK	(MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
476 #define GT_PCI0_BARE_CS20DIS_BIT	GT_PCI0_BARE_CS20DIS_MSK
477 
478 #define GT_PCI0_BARE_SCS32DIS_SHF	7
479 #define GT_PCI0_BARE_SCS32DIS_MSK	(MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
480 #define GT_PCI0_BARE_SCS32DIS_BIT	GT_PCI0_BARE_SCS32DIS_MSK
481 
482 #define GT_PCI0_BARE_SCS10DIS_SHF	8
483 #define GT_PCI0_BARE_SCS10DIS_MSK	(MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
484 #define GT_PCI0_BARE_SCS10DIS_BIT	GT_PCI0_BARE_SCS10DIS_MSK
485 
486 
487 #define GT_INTRCAUSE_MASABORT0_SHF	18
488 #define GT_INTRCAUSE_MASABORT0_MSK	(MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
489 #define GT_INTRCAUSE_MASABORT0_BIT	GT_INTRCAUSE_MASABORT0_MSK
490 
491 #define GT_INTRCAUSE_TARABORT0_SHF	19
492 #define GT_INTRCAUSE_TARABORT0_MSK	(MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
493 #define GT_INTRCAUSE_TARABORT0_BIT	GT_INTRCAUSE_TARABORT0_MSK
494 
495 
496 #define GT_PCI0_CFGADDR_REGNUM_SHF	2
497 #define GT_PCI0_CFGADDR_REGNUM_MSK	(MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
498 #define GT_PCI0_CFGADDR_FUNCTNUM_SHF	8
499 #define GT_PCI0_CFGADDR_FUNCTNUM_MSK	(MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
500 #define GT_PCI0_CFGADDR_DEVNUM_SHF	11
501 #define GT_PCI0_CFGADDR_DEVNUM_MSK	(MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
502 #define GT_PCI0_CFGADDR_BUSNUM_SHF	16
503 #define GT_PCI0_CFGADDR_BUSNUM_MSK	(MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
504 #define GT_PCI0_CFGADDR_CONFIGEN_SHF	31
505 #define GT_PCI0_CFGADDR_CONFIGEN_MSK	(MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
506 #define GT_PCI0_CFGADDR_CONFIGEN_BIT	GT_PCI0_CFGADDR_CONFIGEN_MSK
507 
508 #define GT_PCI0_CMD_MBYTESWAP_SHF	0
509 #define GT_PCI0_CMD_MBYTESWAP_MSK	(MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
510 #define GT_PCI0_CMD_MBYTESWAP_BIT	GT_PCI0_CMD_MBYTESWAP_MSK
511 #define GT_PCI0_CMD_MWORDSWAP_SHF	10
512 #define GT_PCI0_CMD_MWORDSWAP_MSK	(MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
513 #define GT_PCI0_CMD_MWORDSWAP_BIT	GT_PCI0_CMD_MWORDSWAP_MSK
514 #define GT_PCI0_CMD_SBYTESWAP_SHF	16
515 #define GT_PCI0_CMD_SBYTESWAP_MSK	(MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
516 #define GT_PCI0_CMD_SBYTESWAP_BIT	GT_PCI0_CMD_SBYTESWAP_MSK
517 #define GT_PCI0_CMD_SWORDSWAP_SHF	11
518 #define GT_PCI0_CMD_SWORDSWAP_MSK	(MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
519 #define GT_PCI0_CMD_SWORDSWAP_BIT	GT_PCI0_CMD_SWORDSWAP_MSK
520 
521 #define GT_INTR_T0EXP_SHF		8
522 #define GT_INTR_T0EXP_MSK		(MSK(1) << GT_INTR_T0EXP_SHF)
523 #define GT_INTR_T0EXP_BIT		GT_INTR_T0EXP_MSK
524 #define GT_INTR_RETRYCTR0_SHF		20
525 #define GT_INTR_RETRYCTR0_MSK		(MSK(1) << GT_INTR_RETRYCTR0_SHF)
526 #define GT_INTR_RETRYCTR0_BIT		GT_INTR_RETRYCTR0_MSK
527 
528 /*
529  *  Misc
530  */
531 #define GT_DEF_PCI0_IO_BASE	0x10000000UL
532 #define GT_DEF_PCI0_IO_SIZE	0x02000000UL
533 #define GT_DEF_PCI0_MEM0_BASE	0x12000000UL
534 #define GT_DEF_PCI0_MEM0_SIZE	0x02000000UL
535 #define GT_DEF_BASE		0x14000000UL
536 
537 #define GT_MAX_BANKSIZE		(256 * 1024 * 1024)	/* Max 256MB bank  */
538 #define GT_LATTIM_MIN		6			/* Minimum lat	*/
539 
540 /*
541  * The gt64120_dep.h file must define the following macros
542  *
543  *   GT_READ(ofs, data_pointer)
544  *   GT_WRITE(ofs, data)	   - read/write GT64120 registers in 32bit
545  *
546  *   TIMER	- gt64120 timer irq, temporary solution until
547  *		  full gt64120 cascade interrupt support is in place
548  */
549 
550 #include <mach-gt64120.h>
551 
552 /*
553  * Because of an error/peculiarity in the Galileo chip, we need to swap the
554  * bytes when running bigendian.  We also provide non-swapping versions.
555  */
556 #define __GT_READ(ofs)							\
557 	(*(volatile u32 *)(GT64120_BASE+(ofs)))
558 #define __GT_WRITE(ofs, data)						\
559 	do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
560 #define GT_READ(ofs)		le32_to_cpu(__GT_READ(ofs))
561 #define GT_WRITE(ofs, data)	__GT_WRITE(ofs, cpu_to_le32(data))
562 
563 extern void gt641xx_set_base_clock(unsigned int clock);
564 extern int gt641xx_timer0_state(void);
565 
566 #endif /* _ASM_GT64120_H */
567