1 /* 2 * Copyright (C) 2015-2020 Alibaba Group Holding Limited 3 */ 4 #ifndef __HAL_CMU_BEST2001_H__ 5 #define __HAL_CMU_BEST2001_H__ 6 7 #ifdef __cplusplus 8 extern "C" { 9 #endif 10 11 #ifdef FPGA 12 #define HAL_CMU_DEFAULT_CRYSTAL_FREQ 26000000 13 #define HAL_CMU_VALID_CRYSTAL_FREQ { HAL_CMU_DEFAULT_CRYSTAL_FREQ, } 14 #else 15 #define HAL_CMU_VALID_CRYSTAL_FREQ { 26000000, 40000000, } 16 #endif 17 18 enum HAL_CMU_MOD_ID_T { 19 // HCLK/HRST 20 HAL_CMU_MOD_H_MCU, // 0 21 HAL_CMU_MOD_H_CACHE0, // 1 22 HAL_CMU_MOD_H_CP, // 2 23 HAL_CMU_MOD_H_CACHE1, // 3 24 HAL_CMU_MOD_H_ADMA, // 4 25 HAL_CMU_MOD_H_GDMA, // 5 26 HAL_CMU_MOD_H_SEC_ENG, // 6 27 HAL_CMU_MOD_H_USBC, // 7 28 HAL_CMU_MOD_H_USBH, // 8 29 HAL_CMU_MOD_H_I2C_SLAVE, // 9 30 HAL_CMU_MOD_H_AX2H_A7, // 10 31 HAL_CMU_MOD_H_AH2H_WF, // 11 32 HAL_CMU_MOD_H_AH2H_BT, // 12 33 HAL_CMU_MOD_H_CODEC, // 13 34 HAL_CMU_MOD_H_AHB1, // 14 35 HAL_CMU_MOD_H_AHB0, // 15 36 HAL_CMU_MOD_H_PSRAM1G, // 16 37 HAL_CMU_MOD_H_PSRAM200, // 17 38 HAL_CMU_MOD_H_FLASH, // 18 39 HAL_CMU_MOD_H_RAM9, // 19 40 HAL_CMU_MOD_H_RAM8, // 20 41 HAL_CMU_MOD_H_RAM7, // 21 42 HAL_CMU_MOD_H_RAM3_6, // 22 43 HAL_CMU_MOD_H_RAM1_2, // 23 44 HAL_CMU_MOD_H_RAM0, // 24 45 HAL_CMU_MOD_H_ROM0, // 25 46 HAL_CMU_MOD_H_BT_DUMP, // 26 47 HAL_CMU_MOD_H_WF_DUMP, // 27 48 HAL_CMU_MOD_H_SDMMC, // 28 49 HAL_CMU_MOD_H_CHECKSUM, // 29 50 HAL_CMU_MOD_H_CRC, // 30 51 // PCLK/PRST 52 HAL_CMU_MOD_P_CMU, // 31 53 HAL_CMU_MOD_P_WDT, // 32 54 HAL_CMU_MOD_P_TIMER0, // 33 55 HAL_CMU_MOD_P_TIMER1, // 34 56 HAL_CMU_MOD_P_TIMER2, // 35 57 HAL_CMU_MOD_P_I2C0, // 36 58 HAL_CMU_MOD_P_I2C1, // 37 59 HAL_CMU_MOD_P_SPI, // 38 60 HAL_CMU_MOD_P_SLCD, // 39 61 HAL_CMU_MOD_P_SPI_ITN, // 40 62 HAL_CMU_MOD_P_SPI_PHY, // 41 63 HAL_CMU_MOD_P_UART0, // 42 64 HAL_CMU_MOD_P_UART1, // 43 65 HAL_CMU_MOD_P_UART2, // 44 66 HAL_CMU_MOD_P_PCM, // 45 67 HAL_CMU_MOD_P_I2S0, // 46 68 HAL_CMU_MOD_P_SPDIF0, // 47 69 HAL_CMU_MOD_P_TQWF, // 48 70 HAL_CMU_MOD_P_TQA7, // 49 71 HAL_CMU_MOD_P_TRNG, // 50 72 HAL_CMU_MOD_P_SEC_ENG, // 51 73 HAL_CMU_MOD_P_TZC, // 52 74 // OCLK/ORST 75 HAL_CMU_MOD_O_SLEEP, // 53 76 HAL_CMU_MOD_O_USB, // 54 77 HAL_CMU_MOD_O_USB32K, // 55 78 HAL_CMU_MOD_O_PSRAM1G, // 56 79 HAL_CMU_MOD_O_PSRAM200, // 57 80 HAL_CMU_MOD_O_FLASH, // 58 81 HAL_CMU_MOD_O_SDMMC, // 59 82 HAL_CMU_MOD_O_WDT, // 60 83 HAL_CMU_MOD_O_TIMER0, // 61 84 HAL_CMU_MOD_O_TIMER1, // 62 85 HAL_CMU_MOD_O_TIMER2, // 63 86 HAL_CMU_MOD_O_I2C0, // 64 87 HAL_CMU_MOD_O_I2C1, // 65 88 HAL_CMU_MOD_O_SPI, // 66 89 HAL_CMU_MOD_O_SLCD, // 67 90 HAL_CMU_MOD_O_SPI_ITN, // 68 91 HAL_CMU_MOD_O_SPI_PHY, // 69 92 HAL_CMU_MOD_O_UART0, // 70 93 HAL_CMU_MOD_O_UART1, // 71 94 HAL_CMU_MOD_O_UART2, // 72 95 HAL_CMU_MOD_O_PCM, // 73 96 HAL_CMU_MOD_O_I2S0, // 74 97 HAL_CMU_MOD_O_SPDIF0, // 75 98 HAL_CMU_MOD_O_I2S1, // 76 99 HAL_CMU_MOD_O_A7, // 77 100 HAL_CMU_MOD_O_TSF, // 78 101 HAL_CMU_MOD_O_WDT_AP, // 79 102 HAL_CMU_MOD_O_TIMER0_AP, // 80 103 HAL_CMU_MOD_O_TIMER1_AP, // 81 104 105 // AON ACLK/ARST 106 HAL_CMU_AON_A_CMU, // 82 107 HAL_CMU_AON_A_GPIO, // 83 108 HAL_CMU_AON_A_GPIO_INT, // 84 109 HAL_CMU_AON_A_WDT, // 85 110 HAL_CMU_AON_A_PWM, // 86 111 HAL_CMU_AON_A_TIMER, // 87 112 HAL_CMU_AON_A_IOMUX, // 88 113 HAL_CMU_AON_A_SPIDPD, // 89 114 HAL_CMU_AON_A_APBC, // 90 115 HAL_CMU_AON_A_H2H_MCU, // 91 116 // AON OCLK/ORST 117 HAL_CMU_AON_O_WDT, // 92 118 HAL_CMU_AON_O_TIMER, // 93 119 HAL_CMU_AON_O_GPIO, // 94 120 HAL_CMU_AON_O_PWM0, // 95 121 HAL_CMU_AON_O_PWM1, // 96 122 HAL_CMU_AON_O_PWM2, // 97 123 HAL_CMU_AON_O_PWM3, // 98 124 HAL_CMU_AON_O_IOMUX, // 99 125 HAL_CMU_AON_O_SLP32K, // 100 126 HAL_CMU_AON_O_SLP26M, // 101 127 HAL_CMU_AON_O_SPIDPD, // 102 128 HAL_CMU_AON_RESERVED0, // 103 129 // AON SUBSYS 130 HAL_CMU_AON_A7, // 104 131 HAL_CMU_AON_A7CPU, // 105 132 HAL_CMU_AON_MCU, // 106 133 HAL_CMU_AON_CODEC, // 107 134 HAL_CMU_AON_WF, // 108 135 HAL_CMU_AON_BT, // 109 136 HAL_CMU_AON_MCUCPU, // 110 137 HAL_CMU_AON_WFCPU, // 111 138 HAL_CMU_AON_BTCPU, // 112 139 HAL_CMU_AON_GLOBAL, // 113 140 141 HAL_CMU_MOD_QTY, 142 143 HAL_CMU_MOD_GLOBAL = HAL_CMU_AON_GLOBAL, 144 HAL_CMU_MOD_BT = HAL_CMU_AON_BT, 145 HAL_CMU_MOD_BTCPU = HAL_CMU_AON_BTCPU, 146 HAL_CMU_MOD_WF = HAL_CMU_AON_WF, 147 HAL_CMU_MOD_WFCPU = HAL_CMU_AON_WFCPU, 148 149 HAL_CMU_MOD_P_PWM = HAL_CMU_AON_A_PWM, 150 HAL_CMU_MOD_O_PWM0 = HAL_CMU_AON_O_PWM0, 151 HAL_CMU_MOD_O_PWM1 = HAL_CMU_AON_O_PWM1, 152 HAL_CMU_MOD_O_PWM2 = HAL_CMU_AON_O_PWM2, 153 HAL_CMU_MOD_O_PWM3 = HAL_CMU_AON_O_PWM3, 154 155 HAL_CMU_H_ICACHE = HAL_CMU_MOD_H_CACHE0, 156 HAL_CMU_H_DCACHE = HAL_CMU_MOD_QTY, 157 HAL_CMU_H_ICACHECP = HAL_CMU_MOD_H_CACHE1, 158 HAL_CMU_H_DCACHECP = HAL_CMU_MOD_QTY, 159 160 HAL_CMU_MOD_P_SPI_DPD = HAL_CMU_AON_A_SPIDPD, 161 HAL_CMU_MOD_O_SPI_DPD = HAL_CMU_AON_O_SPIDPD, 162 HAL_CMU_MOD_H_PSRAM = HAL_CMU_MOD_H_PSRAM200, 163 HAL_CMU_MOD_O_PSRAM = HAL_CMU_MOD_O_PSRAM200, 164 HAL_CMU_MOD_H_PSRAMUHS = HAL_CMU_MOD_H_PSRAM1G, 165 HAL_CMU_MOD_O_PSRAMUHS = HAL_CMU_MOD_O_PSRAM1G, 166 }; 167 168 enum HAL_CMU_CLOCK_OUT_ID_T { 169 HAL_CMU_CLOCK_OUT_AON_32K = 0x00, 170 HAL_CMU_CLOCK_OUT_AON_26M = 0x01, 171 HAL_CMU_CLOCK_OUT_AON_52M = 0x02, 172 HAL_CMU_CLOCK_OUT_AON_DIG_52M = 0x03, 173 HAL_CMU_CLOCK_OUT_AON_DIG_104M = 0x04, 174 HAL_CMU_CLOCK_OUT_AON_PER = 0x05, 175 HAL_CMU_CLOCK_OUT_AON_USB = 0x06, 176 HAL_CMU_CLOCK_OUT_AON_DCDC = 0x07, 177 HAL_CMU_CLOCK_OUT_AON_CHCLK = 0x08, 178 HAL_CMU_CLOCK_OUT_AON_SPDIF0 = 0x09, 179 HAL_CMU_CLOCK_OUT_AON_MCU = 0x0A, 180 HAL_CMU_CLOCK_OUT_AON_FLASH = 0x0B, 181 HAL_CMU_CLOCK_OUT_AON_SYS = 0x0C, 182 183 HAL_CMU_CLOCK_OUT_BT_32K = 0x40, 184 HAL_CMU_CLOCK_OUT_BT_SYS = 0x41, 185 HAL_CMU_CLOCK_OUT_BT_52M = 0x42, 186 HAL_CMU_CLOCK_OUT_BT_26MI = 0x43, 187 HAL_CMU_CLOCK_OUT_BT_13M = 0x44, 188 HAL_CMU_CLOCK_OUT_BT_12M = 0x45, 189 HAL_CMU_CLOCK_OUT_BT_ADC = 0x46, 190 HAL_CMU_CLOCK_OUT_BT_ADC2 = 0x47, 191 HAL_CMU_CLOCK_OUT_BT_24M = 0x48, 192 HAL_CMU_CLOCK_OUT_BT_26M = 0x49, 193 194 HAL_CMU_CLOCK_OUT_MCU_32K = 0x60, 195 HAL_CMU_CLOCK_OUT_MCU_SYS = 0x61, 196 HAL_CMU_CLOCK_OUT_MCU_FLASH = 0x62, 197 HAL_CMU_CLOCK_OUT_MCU_USB = 0x63, 198 HAL_CMU_CLOCK_OUT_MCU_PCLK = 0x64, 199 HAL_CMU_CLOCK_OUT_MCU_I2S = 0x65, 200 HAL_CMU_CLOCK_OUT_MCU_PCM = 0x66, 201 HAL_CMU_CLOCK_OUT_MCU_SPDIF0 = 0x67, 202 HAL_CMU_CLOCK_OUT_MCU_SDMMC = 0x68, 203 HAL_CMU_CLOCK_OUT_MCU_SPI2 = 0x69, 204 HAL_CMU_CLOCK_OUT_MCU_SPI0 = 0x6A, 205 HAL_CMU_CLOCK_OUT_MCU_SPI1 = 0x6B, 206 207 HAL_CMU_CLOCK_OUT_CODEC_ADC_ANA = 0x80, 208 HAL_CMU_CLOCK_OUT_CODEC_CODEC = 0x81, 209 HAL_CMU_CLOCK_OUT_CODEC_IIR = 0x82, 210 HAL_CMU_CLOCK_OUT_CODEC_RS = 0x83, 211 HAL_CMU_CLOCK_OUT_CODEC_HCLK = 0x84, 212 }; 213 214 enum HAL_CMU_I2S_MCLK_ID_T { 215 HAL_CMU_I2S_MCLK_PLLCODEC = 0x00, 216 HAL_CMU_I2S_MCLK_CODEC = 0x01, 217 HAL_CMU_I2S_MCLK_PLLIIR = 0x02, 218 HAL_CMU_I2S_MCLK_PLLRS = 0x03, 219 HAL_CMU_I2S_MCLK_PLLSPDIF0 = 0x04, 220 HAL_CMU_I2S_MCLK_PLLPCM = 0x05, 221 HAL_CMU_I2S_MCLK_PER = 0x06, 222 HAL_CMU_I2S_MCLK_CLK_OUT = 0x07, 223 }; 224 225 enum HAL_CMU_LOW_SYS_FREQ_T { 226 HAL_CMU_LOW_SYS_FREQ_NONE, 227 HAL_CMU_LOW_SYS_FREQ_13M, 228 HAL_CMU_LOW_SYS_FREQ_6P5M, 229 }; 230 231 enum HAL_CMU_FREQ_T { 232 HAL_CMU_FREQ_32K, 233 HAL_CMU_FREQ_26M, 234 HAL_CMU_FREQ_52M, 235 HAL_CMU_FREQ_78M, 236 HAL_CMU_FREQ_104M, 237 HAL_CMU_FREQ_156M, 238 HAL_CMU_FREQ_208M, 239 HAL_CMU_FREQ_260M, 240 HAL_CMU_FREQ_390M, 241 HAL_CMU_FREQ_780M, 242 243 HAL_CMU_FREQ_QTY 244 }; 245 #define HAL_CMU_FREQ_T HAL_CMU_FREQ_T 246 247 enum HAL_CMU_PLL_T { 248 HAL_CMU_PLL_USB = 0, 249 HAL_CMU_PLL_AUD = HAL_CMU_PLL_USB, 250 HAL_CMU_PLL_DDR, 251 HAL_CMU_PLL_DSP, 252 HAL_CMU_PLL_BB, 253 HAL_CMU_PLL_BB_PSRAM, 254 255 HAL_CMU_PLL_QTY 256 }; 257 #define HAL_CMU_PLL_T HAL_CMU_PLL_T 258 259 enum HAL_CMU_PLL_USER_T { 260 HAL_CMU_PLL_USER_SYS, 261 HAL_CMU_PLL_USER_AUD, 262 HAL_CMU_PLL_USER_USB, 263 HAL_CMU_PLL_USER_FLASH, 264 HAL_CMU_PLL_USER_PSRAM, 265 HAL_CMU_PLL_USER_DSP, 266 267 HAL_CMU_PLL_USER_QTY, 268 HAL_CMU_PLL_USER_ALL = HAL_CMU_PLL_USER_QTY, 269 }; 270 #define HAL_CMU_PLL_USER_T HAL_CMU_PLL_USER_T 271 272 void hal_cmu_low_sys_clock_set(enum HAL_CMU_LOW_SYS_FREQ_T freq); 273 274 int hal_cmu_low_sys_clock_enabled(void); 275 276 int hal_cmu_ddr_clock_enable(); 277 278 void hal_cmu_codec_vad_clock_enable(uint32_t enabled); 279 280 uint32_t hal_cmu_get_aon_chip_id(void); 281 282 uint32_t hal_cmu_get_aon_revision_id(void); 283 284 void hal_cmu_dma_dsd_enable(void); 285 286 void hal_cmu_dma_dsd_disable(void); 287 288 void hal_cmu_cp_enable(uint32_t sp, uint32_t entry); 289 290 void hal_cmu_cp_disable(void); 291 292 uint32_t hal_cmu_cp_get_entry_addr(void); 293 294 void hal_cmu_wifi_clock_enable(void); 295 296 void hal_cmu_wifi_clock_disable(void); 297 298 void hal_cmu_wifi_reset_set(void); 299 300 void hal_cmu_wifi_reset_clear(void); 301 void hal_cmu_wifi_module_reset_clear(void); 302 void hal_cmu_wifi_cpu_reset_clear(void); 303 void hal_cmu_wifi_clock_cfg_80M(void); 304 305 void hal_cmu_dsp_clock_enable(void); 306 307 void hal_cmu_dsp_clock_disable(void); 308 309 void hal_cmu_dsp_reset_set(void); 310 311 void hal_cmu_dsp_reset_clear(void); 312 313 void hal_cmu_dsp_init_boot_reg(uint32_t entry); 314 315 void hal_cmu_dsp_start_cpu(void); 316 317 void hal_cmu_dsp_setup(void); 318 319 void hal_cmu_dsp_stop_cpu(void); 320 321 #ifdef __cplusplus 322 } 323 #endif 324 325 #endif 326 327