1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_pwr_ex.c
4 * @author MCD Application Team
5 * @version V1.0.1
6 * @date 25-June-2015
7 * @brief Extended PWR HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of PWR extension peripheral:
10 * + Peripheral Extended features functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42 /* Includes ------------------------------------------------------------------*/
43 #include "stm32f7xx_hal.h"
44
45 /** @addtogroup STM32F7xx_HAL_Driver
46 * @{
47 */
48
49 /** @defgroup PWREx PWREx
50 * @brief PWR HAL module driver
51 * @{
52 */
53
54 #ifdef HAL_PWR_MODULE_ENABLED
55
56 /* Private typedef -----------------------------------------------------------*/
57 /* Private define ------------------------------------------------------------*/
58 /** @addtogroup PWREx_Private_Constants
59 * @{
60 */
61 #define PWR_OVERDRIVE_TIMEOUT_VALUE 1000
62 #define PWR_UDERDRIVE_TIMEOUT_VALUE 1000
63 #define PWR_BKPREG_TIMEOUT_VALUE 1000
64 #define PWR_VOSRDY_TIMEOUT_VALUE 1000
65 /**
66 * @}
67 */
68
69 /* Private macro -------------------------------------------------------------*/
70 /* Private variables ---------------------------------------------------------*/
71 /* Private function prototypes -----------------------------------------------*/
72 /* Private functions ---------------------------------------------------------*/
73 /** @defgroup PWREx_Exported_Functions PWREx Exported Functions
74 * @{
75 */
76
77 /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
78 * @brief Peripheral Extended features functions
79 *
80 @verbatim
81
82 ===============================================================================
83 ##### Peripheral extended features functions #####
84 ===============================================================================
85
86 *** Main and Backup Regulators configuration ***
87 ================================================
88 [..]
89 (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
90 the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
91 retained even in Standby or VBAT mode when the low power backup regulator
92 is enabled. It can be considered as an internal EEPROM when VBAT is
93 always present. You can use the HAL_PWREx_EnableBkUpReg() function to
94 enable the low power backup regulator.
95
96 (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
97 the backup SRAM is powered from VDD which replaces the VBAT power supply to
98 save battery life.
99
100 (+) The backup SRAM is not mass erased by a tamper event. It is read
101 protected to prevent confidential data, such as cryptographic private
102 key, from being accessed. The backup SRAM can be erased only through
103 the Flash interface when a protection level change from level 1 to
104 level 0 is requested.
105 -@- Refer to the description of Read protection (RDP) in the Flash
106 programming manual.
107
108 (+) The main internal regulator can be configured to have a tradeoff between
109 performance and power consumption when the device does not operate at
110 the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
111 macro which configure VOS bit in PWR_CR register
112
113 Refer to the product datasheets for more details.
114
115 *** FLASH Power Down configuration ****
116 =======================================
117 [..]
118 (+) By setting the FPDS bit in the PWR_CR register by using the
119 HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
120 down mode when the device enters Stop mode. When the Flash memory
121 is in power down mode, an additional startup delay is incurred when
122 waking up from Stop mode.
123
124 *** Over-Drive and Under-Drive configuration ****
125 =================================================
126 [..]
127 (+) In Run mode: the main regulator has 2 operating modes available:
128 (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
129 voltage scaling (scale 1, scale 2 or scale 3)
130 (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
131 higher frequency than the normal mode for a given voltage scaling (scale 1,
132 scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
133 disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
134 the sequence described in Reference manual.
135
136 (+) In Stop mode: the main regulator or low power regulator supplies a low power
137 voltage to the 1.2V domain, thus preserving the content of registers
138 and internal SRAM. 2 operating modes are available:
139 (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
140 available when the main regulator or the low power regulator is used in Scale 3 or
141 low voltage mode.
142 (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
143 available when the main regulator or the low power regulator is in low voltage mode.
144
145 @endverbatim
146 * @{
147 */
148
149 /**
150 * @brief Enables the Backup Regulator.
151 * @retval HAL status
152 */
HAL_PWREx_EnableBkUpReg(void)153 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
154 {
155 uint32_t tickstart = 0;
156
157 /* Enable Backup regulator */
158 PWR->CSR1 |= PWR_CSR1_BRE;
159
160 /* Get tick */
161 tickstart = HAL_GetTick();
162
163 /* Wait till Backup regulator ready flag is set */
164 while (__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET) {
165 if ((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) {
166 return HAL_TIMEOUT;
167 }
168 }
169 return HAL_OK;
170 }
171
172 /**
173 * @brief Disables the Backup Regulator.
174 * @retval HAL status
175 */
HAL_PWREx_DisableBkUpReg(void)176 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
177 {
178 uint32_t tickstart = 0;
179
180 /* Disable Backup regulator */
181 PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);
182
183 /* Get tick */
184 tickstart = HAL_GetTick();
185
186 /* Wait till Backup regulator ready flag is set */
187 while (__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET) {
188 if ((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) {
189 return HAL_TIMEOUT;
190 }
191 }
192 return HAL_OK;
193 }
194
195 /**
196 * @brief Enables the Flash Power Down in Stop mode.
197 * @retval None
198 */
HAL_PWREx_EnableFlashPowerDown(void)199 void HAL_PWREx_EnableFlashPowerDown(void)
200 {
201 /* Enable the Flash Power Down */
202 PWR->CR1 |= PWR_CR1_FPDS;
203 }
204
205 /**
206 * @brief Disables the Flash Power Down in Stop mode.
207 * @retval None
208 */
HAL_PWREx_DisableFlashPowerDown(void)209 void HAL_PWREx_DisableFlashPowerDown(void)
210 {
211 /* Disable the Flash Power Down */
212 PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS);
213 }
214
215 /**
216 * @brief Enables Main Regulator low voltage mode.
217 * @retval None
218 */
HAL_PWREx_EnableMainRegulatorLowVoltage(void)219 void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
220 {
221 /* Enable Main regulator low voltage */
222 PWR->CR1 |= PWR_CR1_MRUDS;
223 }
224
225 /**
226 * @brief Disables Main Regulator low voltage mode.
227 * @retval None
228 */
HAL_PWREx_DisableMainRegulatorLowVoltage(void)229 void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
230 {
231 /* Disable Main regulator low voltage */
232 PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS);
233 }
234
235 /**
236 * @brief Enables Low Power Regulator low voltage mode.
237 * @retval None
238 */
HAL_PWREx_EnableLowRegulatorLowVoltage(void)239 void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
240 {
241 /* Enable low power regulator */
242 PWR->CR1 |= PWR_CR1_LPUDS;
243 }
244
245 /**
246 * @brief Disables Low Power Regulator low voltage mode.
247 * @retval None
248 */
HAL_PWREx_DisableLowRegulatorLowVoltage(void)249 void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
250 {
251 /* Disable low power regulator */
252 PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS);
253 }
254
255 /**
256 * @brief Activates the Over-Drive mode.
257 * @note This mode allows the CPU and the core logic to operate at a higher frequency
258 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
259 * @note It is recommended to enter or exit Over-drive mode when the application is not running
260 * critical tasks and when the system clock source is either HSI or HSE.
261 * During the Over-drive switch activation, no peripheral clocks should be enabled.
262 * The peripheral clocks must be enabled once the Over-drive mode is activated.
263 * @retval HAL status
264 */
HAL_PWREx_EnableOverDrive(void)265 HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
266 {
267 uint32_t tickstart = 0;
268
269 __HAL_RCC_PWR_CLK_ENABLE();
270
271 /* Enable the Over-drive to extend the clock frequency to 216 MHz */
272 __HAL_PWR_OVERDRIVE_ENABLE();
273
274 /* Get tick */
275 tickstart = HAL_GetTick();
276
277 while (!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) {
278 if ((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) {
279 return HAL_TIMEOUT;
280 }
281 }
282
283 /* Enable the Over-drive switch */
284 __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
285
286 /* Get tick */
287 tickstart = HAL_GetTick();
288
289 while (!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) {
290 if ((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) {
291 return HAL_TIMEOUT;
292 }
293 }
294 return HAL_OK;
295 }
296
297 /**
298 * @brief Deactivates the Over-Drive mode.
299 * @note This mode allows the CPU and the core logic to operate at a higher frequency
300 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
301 * @note It is recommended to enter or exit Over-drive mode when the application is not running
302 * critical tasks and when the system clock source is either HSI or HSE.
303 * During the Over-drive switch activation, no peripheral clocks should be enabled.
304 * The peripheral clocks must be enabled once the Over-drive mode is activated.
305 * @retval HAL status
306 */
HAL_PWREx_DisableOverDrive(void)307 HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
308 {
309 uint32_t tickstart = 0;
310
311 __HAL_RCC_PWR_CLK_ENABLE();
312
313 /* Disable the Over-drive switch */
314 __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
315
316 /* Get tick */
317 tickstart = HAL_GetTick();
318
319 while (__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) {
320 if ((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) {
321 return HAL_TIMEOUT;
322 }
323 }
324
325 /* Disable the Over-drive */
326 __HAL_PWR_OVERDRIVE_DISABLE();
327
328 /* Get tick */
329 tickstart = HAL_GetTick();
330
331 while (__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) {
332 if ((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) {
333 return HAL_TIMEOUT;
334 }
335 }
336
337 return HAL_OK;
338 }
339
340 /**
341 * @brief Enters in Under-Drive STOP mode.
342 *
343 * @note This mode can be selected only when the Under-Drive is already active
344 *
345 * @note This mode is enabled only with STOP low power mode.
346 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
347 * mode is only available when the main regulator or the low power regulator
348 * is in low voltage mode
349 *
350 * @note If the Under-drive mode was enabled, it is automatically disabled after
351 * exiting Stop mode.
352 * When the voltage regulator operates in Under-drive mode, an additional
353 * startup delay is induced when waking up from Stop mode.
354 *
355 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
356 *
357 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
358 * the HSI RC oscillator is selected as system clock.
359 *
360 * @note When the voltage regulator operates in low power mode, an additional
361 * startup delay is incurred when waking up from Stop mode.
362 * By keeping the internal regulator ON during Stop mode, the consumption
363 * is higher although the startup time is reduced.
364 *
365 * @param Regulator: specifies the regulator state in STOP mode.
366 * This parameter can be one of the following values:
367 * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode
368 * and Flash memory in power-down when the device is in Stop under-drive mode
369 * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode
370 * and Flash memory in power-down when the device is in Stop under-drive mode
371 * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
372 * This parameter can be one of the following values:
373 * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
374 * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
375 * @retval None
376 */
HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator,uint8_t STOPEntry)377 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
378 {
379 uint32_t tempreg = 0;
380 uint32_t tickstart = 0;
381
382 /* Check the parameters */
383 assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
384 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
385
386 /* Enable Power ctrl clock */
387 __HAL_RCC_PWR_CLK_ENABLE();
388 /* Enable the Under-drive Mode ---------------------------------------------*/
389 /* Clear Under-drive flag */
390 __HAL_PWR_CLEAR_ODRUDR_FLAG();
391
392 /* Enable the Under-drive */
393 __HAL_PWR_UNDERDRIVE_ENABLE();
394
395 /* Get tick */
396 tickstart = HAL_GetTick();
397
398 /* Wait for UnderDrive mode is ready */
399 while (__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY)) {
400 if ((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE) {
401 return HAL_TIMEOUT;
402 }
403 }
404
405 /* Select the regulator state in STOP mode ---------------------------------*/
406 tempreg = PWR->CR1;
407 /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
408 tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS);
409
410 /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
411 tempreg |= Regulator;
412
413 /* Store the new value */
414 PWR->CR1 = tempreg;
415
416 /* Set SLEEPDEEP bit of Cortex System Control Register */
417 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
418
419 /* Select STOP mode entry --------------------------------------------------*/
420 if (STOPEntry == PWR_SLEEPENTRY_WFI) {
421 /* Request Wait For Interrupt */
422 __WFI();
423 } else {
424 /* Request Wait For Event */
425 __WFE();
426 }
427 /* Reset SLEEPDEEP bit of Cortex System Control Register */
428 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
429
430 return HAL_OK;
431 }
432
433 /**
434 * @brief Returns Voltage Scaling Range.
435 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or
436 * PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1
437 */
HAL_PWREx_GetVoltageRange(void)438 uint32_t HAL_PWREx_GetVoltageRange(void)
439 {
440 return (PWR->CR1 & PWR_CR1_VOS);
441 }
442
443 /**
444 * @brief Configures the main internal regulator output voltage.
445 * @param VoltageScaling: specifies the regulator output voltage to achieve
446 * a tradeoff between performance and power consumption.
447 * This parameter can be one of the following values:
448 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
449 * typical output voltage at 1.4 V,
450 * system frequency up to 216 MHz.
451 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
452 * typical output voltage at 1.2 V,
453 * system frequency up to 180 MHz.
454 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode,
455 * typical output voltage at 1.00 V,
456 * system frequency up to 151 MHz.
457 * @note To update the system clock frequency(SYSCLK):
458 * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
459 * - Call the HAL_RCC_OscConfig() to configure the PLL.
460 * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
461 * - Set the new system clock frequency using the HAL_RCC_ClockConfig().
462 * @note The scale can be modified only when the HSI or HSE clock source is selected
463 * as system clock source, otherwise the API returns HAL_ERROR.
464 * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
465 * value in the PWR_CR1 register are not taken in account.
466 * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
467 * @note The new voltage scale is active only when the PLL is ON.
468 * @retval HAL Status
469 */
HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)470 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
471 {
472 uint32_t tickstart = 0;
473
474 assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));
475
476 /* Enable Power ctrl clock */
477 __HAL_RCC_PWR_CLK_ENABLE();
478
479 /* Check if the PLL is used as system clock or not */
480 if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) {
481 /* Disable the main PLL */
482 __HAL_RCC_PLL_DISABLE();
483
484 /* Get Start Tick */
485 tickstart = HAL_GetTick();
486 /* Wait till PLL is disabled */
487 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) {
488 if ((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) {
489 return HAL_TIMEOUT;
490 }
491 }
492
493 /* Set Range */
494 __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
495
496 /* Enable the main PLL */
497 __HAL_RCC_PLL_ENABLE();
498
499 /* Get Start Tick */
500 tickstart = HAL_GetTick();
501 /* Wait till PLL is ready */
502 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) {
503 if ((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) {
504 return HAL_TIMEOUT;
505 }
506 }
507
508 /* Get Start Tick */
509 tickstart = HAL_GetTick();
510 while ((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) {
511 if ((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) {
512 return HAL_TIMEOUT;
513 }
514 }
515 } else {
516 return HAL_ERROR;
517 }
518 return HAL_OK;
519 }
520
521 /**
522 * @}
523 */
524
525 /**
526 * @}
527 */
528
529 #endif /* HAL_PWR_MODULE_ENABLED */
530 /**
531 * @}
532 */
533
534 /**
535 * @}
536 */
537
538 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
539