1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_sdram.c
4 * @author MCD Application Team
5 * @version V1.0.1
6 * @date 25-June-2015
7 * @brief SDRAM HAL module driver.
8 * This file provides a generic firmware to drive SDRAM memories mounted
9 * as external device.
10 *
11 @verbatim
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
15 [..]
16 This driver is a generic layered driver which contains a set of APIs used to
17 control SDRAM memories. It uses the FMC layer functions to interface
18 with SDRAM devices.
19 The following sequence should be followed to configure the FMC to interface
20 with SDRAM memories:
21
22 (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
23 SDRAM_HandleTypeDef hdsram
24
25 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
26 values of the structure member.
27
28 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
29 base register instance for NOR or SDRAM device
30
31 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
32 FMC_SDRAM_TimingTypeDef Timing;
33 and fill its fields with the allowed values of the structure member.
34
35 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
36 performs the following sequence:
37
38 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
39 (##) Control register configuration using the FMC SDRAM interface function
40 FMC_SDRAM_Init()
41 (##) Timing register configuration using the FMC SDRAM interface function
42 FMC_SDRAM_Timing_Init()
43 (##) Program the SDRAM external device by applying its initialization sequence
44 according to the device plugged in your hardware. This step is mandatory
45 for accessing the SDRAM device.
46
47 (#) At this stage you can perform read/write accesses from/to the memory connected
48 to the SDRAM Bank. You can perform either polling or DMA transfer using the
49 following APIs:
50 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
51 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
52
53 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
54 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
55 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
56 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
57 structure.
58
59 (#) You can continuously monitor the SDRAM device HAL state by calling the function
60 HAL_SDRAM_GetState()
61
62 @endverbatim
63 ******************************************************************************
64 * @attention
65 *
66 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
67 *
68 * Redistribution and use in source and binary forms, with or without modification,
69 * are permitted provided that the following conditions are met:
70 * 1. Redistributions of source code must retain the above copyright notice,
71 * this list of conditions and the following disclaimer.
72 * 2. Redistributions in binary form must reproduce the above copyright notice,
73 * this list of conditions and the following disclaimer in the documentation
74 * and/or other materials provided with the distribution.
75 * 3. Neither the name of STMicroelectronics nor the names of its contributors
76 * may be used to endorse or promote products derived from this software
77 * without specific prior written permission.
78 *
79 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
80 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
82 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
85 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
86 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
87 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
88 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
89 *
90 ******************************************************************************
91 */
92
93 /* Includes ------------------------------------------------------------------*/
94 #include "stm32f7xx_hal.h"
95
96 /** @addtogroup STM32F7xx_HAL_Driver
97 * @{
98 */
99
100 /** @defgroup SDRAM SDRAM
101 * @brief SDRAM driver modules
102 * @{
103 */
104 #ifdef HAL_SDRAM_MODULE_ENABLED
105
106 /* Private typedef -----------------------------------------------------------*/
107 /* Private define ------------------------------------------------------------*/
108 /* Private macro -------------------------------------------------------------*/
109 /* Private variables ---------------------------------------------------------*/
110 /* Private functions ---------------------------------------------------------*/
111 /* Exported functions --------------------------------------------------------*/
112 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
113 * @{
114 */
115
116 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
117 * @brief Initialization and Configuration functions
118 *
119 @verbatim
120 ==============================================================================
121 ##### SDRAM Initialization and de_initialization functions #####
122 ==============================================================================
123 [..]
124 This section provides functions allowing to initialize/de-initialize
125 the SDRAM memory
126
127 @endverbatim
128 * @{
129 */
130
131 /**
132 * @brief Performs the SDRAM device initialization sequence.
133 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
134 * the configuration information for SDRAM module.
135 * @param Timing: Pointer to SDRAM control timing structure
136 * @retval HAL status
137 */
HAL_SDRAM_Init(SDRAM_HandleTypeDef * hsdram,FMC_SDRAM_TimingTypeDef * Timing)138 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
139 {
140 /* Check the SDRAM handle parameter */
141 if (hsdram == NULL) {
142 return HAL_ERROR;
143 }
144
145 if (hsdram->State == HAL_SDRAM_STATE_RESET) {
146 /* Allocate lock resource and initialize it */
147 hsdram->Lock = HAL_UNLOCKED;
148 /* Initialize the low level hardware (MSP) */
149 HAL_SDRAM_MspInit(hsdram);
150 }
151
152 /* Initialize the SDRAM controller state */
153 hsdram->State = HAL_SDRAM_STATE_BUSY;
154
155 /* Initialize SDRAM control Interface */
156 FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
157
158 /* Initialize SDRAM timing Interface */
159 FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
160
161 /* Update the SDRAM controller state */
162 hsdram->State = HAL_SDRAM_STATE_READY;
163
164 return HAL_OK;
165 }
166
167 /**
168 * @brief Perform the SDRAM device initialization sequence.
169 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
170 * the configuration information for SDRAM module.
171 * @retval HAL status
172 */
HAL_SDRAM_DeInit(SDRAM_HandleTypeDef * hsdram)173 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
174 {
175 /* Initialize the low level hardware (MSP) */
176 HAL_SDRAM_MspDeInit(hsdram);
177
178 /* Configure the SDRAM registers with their reset values */
179 FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
180
181 /* Reset the SDRAM controller state */
182 hsdram->State = HAL_SDRAM_STATE_RESET;
183
184 /* Release Lock */
185 __HAL_UNLOCK(hsdram);
186
187 return HAL_OK;
188 }
189
190 /**
191 * @brief SDRAM MSP Init.
192 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
193 * the configuration information for SDRAM module.
194 * @retval None
195 */
HAL_SDRAM_MspInit(SDRAM_HandleTypeDef * hsdram)196 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
197 {
198 /* NOTE: This function Should not be modified, when the callback is needed,
199 the HAL_SDRAM_MspInit could be implemented in the user file
200 */
201 }
202
203 /**
204 * @brief SDRAM MSP DeInit.
205 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
206 * the configuration information for SDRAM module.
207 * @retval None
208 */
HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef * hsdram)209 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
210 {
211 /* NOTE: This function Should not be modified, when the callback is needed,
212 the HAL_SDRAM_MspDeInit could be implemented in the user file
213 */
214 }
215
216 /**
217 * @brief This function handles SDRAM refresh error interrupt request.
218 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
219 * the configuration information for SDRAM module.
220 * @retval HAL status
221 */
HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef * hsdram)222 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
223 {
224 /* Check SDRAM interrupt Rising edge flag */
225 if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) {
226 /* SDRAM refresh error interrupt callback */
227 HAL_SDRAM_RefreshErrorCallback(hsdram);
228
229 /* Clear SDRAM refresh error interrupt pending bit */
230 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
231 }
232 }
233
234 /**
235 * @brief SDRAM Refresh error callback.
236 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
237 * the configuration information for SDRAM module.
238 * @retval None
239 */
HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef * hsdram)240 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
241 {
242 /* NOTE: This function Should not be modified, when the callback is needed,
243 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
244 */
245 }
246
247 /**
248 * @brief DMA transfer complete callback.
249 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
250 * the configuration information for the specified DMA module.
251 * @retval None
252 */
HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef * hdma)253 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
254 {
255 /* NOTE: This function Should not be modified, when the callback is needed,
256 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
257 */
258 }
259
260 /**
261 * @brief DMA transfer complete error callback.
262 * @param hdma: DMA handle
263 * @retval None
264 */
HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef * hdma)265 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
266 {
267 /* NOTE: This function Should not be modified, when the callback is needed,
268 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
269 */
270 }
271
272 /**
273 * @}
274 */
275
276 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
277 * @brief Input Output and memory control functions
278 *
279 @verbatim
280 ==============================================================================
281 ##### SDRAM Input and Output functions #####
282 ==============================================================================
283 [..]
284 This section provides functions allowing to use and control the SDRAM memory
285
286 @endverbatim
287 * @{
288 */
289
290 /**
291 * @brief Reads 8-bit data buffer from the SDRAM memory.
292 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
293 * the configuration information for SDRAM module.
294 * @param pAddress: Pointer to read start address
295 * @param pDstBuffer: Pointer to destination buffer
296 * @param BufferSize: Size of the buffer to read from memory
297 * @retval HAL status
298 */
HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint8_t * pDstBuffer,uint32_t BufferSize)299 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
300 {
301 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
302
303 /* Process Locked */
304 __HAL_LOCK(hsdram);
305
306 /* Check the SDRAM controller state */
307 if (hsdram->State == HAL_SDRAM_STATE_BUSY) {
308 return HAL_BUSY;
309 } else if (hsdram->State == HAL_SDRAM_STATE_PRECHARGED) {
310 return HAL_ERROR;
311 }
312
313 /* Read data from source */
314 for (; BufferSize != 0; BufferSize--) {
315 *pDstBuffer = *(__IO uint8_t *)pSdramAddress;
316 pDstBuffer++;
317 pSdramAddress++;
318 }
319
320 /* Process Unlocked */
321 __HAL_UNLOCK(hsdram);
322
323 return HAL_OK;
324 }
325
326
327 /**
328 * @brief Writes 8-bit data buffer to SDRAM memory.
329 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
330 * the configuration information for SDRAM module.
331 * @param pAddress: Pointer to write start address
332 * @param pSrcBuffer: Pointer to source buffer to write
333 * @param BufferSize: Size of the buffer to write to memory
334 * @retval HAL status
335 */
HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint8_t * pSrcBuffer,uint32_t BufferSize)336 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
337 {
338 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
339 uint32_t tmp = 0;
340
341 /* Process Locked */
342 __HAL_LOCK(hsdram);
343
344 /* Check the SDRAM controller state */
345 tmp = hsdram->State;
346
347 if (tmp == HAL_SDRAM_STATE_BUSY) {
348 return HAL_BUSY;
349 } else if ((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) {
350 return HAL_ERROR;
351 }
352
353 /* Write data to memory */
354 for (; BufferSize != 0; BufferSize--) {
355 *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
356 pSrcBuffer++;
357 pSdramAddress++;
358 }
359
360 /* Process Unlocked */
361 __HAL_UNLOCK(hsdram);
362
363 return HAL_OK;
364 }
365
366
367 /**
368 * @brief Reads 16-bit data buffer from the SDRAM memory.
369 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
370 * the configuration information for SDRAM module.
371 * @param pAddress: Pointer to read start address
372 * @param pDstBuffer: Pointer to destination buffer
373 * @param BufferSize: Size of the buffer to read from memory
374 * @retval HAL status
375 */
HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint16_t * pDstBuffer,uint32_t BufferSize)376 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
377 {
378 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
379
380 /* Process Locked */
381 __HAL_LOCK(hsdram);
382
383 /* Check the SDRAM controller state */
384 if (hsdram->State == HAL_SDRAM_STATE_BUSY) {
385 return HAL_BUSY;
386 } else if (hsdram->State == HAL_SDRAM_STATE_PRECHARGED) {
387 return HAL_ERROR;
388 }
389
390 /* Read data from source */
391 for (; BufferSize != 0; BufferSize--) {
392 *pDstBuffer = *(__IO uint16_t *)pSdramAddress;
393 pDstBuffer++;
394 pSdramAddress++;
395 }
396
397 /* Process Unlocked */
398 __HAL_UNLOCK(hsdram);
399
400 return HAL_OK;
401 }
402
403 /**
404 * @brief Writes 16-bit data buffer to SDRAM memory.
405 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
406 * the configuration information for SDRAM module.
407 * @param pAddress: Pointer to write start address
408 * @param pSrcBuffer: Pointer to source buffer to write
409 * @param BufferSize: Size of the buffer to write to memory
410 * @retval HAL status
411 */
HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint16_t * pSrcBuffer,uint32_t BufferSize)412 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
413 {
414 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
415 uint32_t tmp = 0;
416
417 /* Process Locked */
418 __HAL_LOCK(hsdram);
419
420 /* Check the SDRAM controller state */
421 tmp = hsdram->State;
422
423 if (tmp == HAL_SDRAM_STATE_BUSY) {
424 return HAL_BUSY;
425 } else if ((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) {
426 return HAL_ERROR;
427 }
428
429 /* Write data to memory */
430 for (; BufferSize != 0; BufferSize--) {
431 *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
432 pSrcBuffer++;
433 pSdramAddress++;
434 }
435
436 /* Process Unlocked */
437 __HAL_UNLOCK(hsdram);
438
439 return HAL_OK;
440 }
441
442 /**
443 * @brief Reads 32-bit data buffer from the SDRAM memory.
444 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
445 * the configuration information for SDRAM module.
446 * @param pAddress: Pointer to read start address
447 * @param pDstBuffer: Pointer to destination buffer
448 * @param BufferSize: Size of the buffer to read from memory
449 * @retval HAL status
450 */
HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)451 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
452 {
453 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
454
455 /* Process Locked */
456 __HAL_LOCK(hsdram);
457
458 /* Check the SDRAM controller state */
459 if (hsdram->State == HAL_SDRAM_STATE_BUSY) {
460 return HAL_BUSY;
461 } else if (hsdram->State == HAL_SDRAM_STATE_PRECHARGED) {
462 return HAL_ERROR;
463 }
464
465 /* Read data from source */
466 for (; BufferSize != 0; BufferSize--) {
467 *pDstBuffer = *(__IO uint32_t *)pSdramAddress;
468 pDstBuffer++;
469 pSdramAddress++;
470 }
471
472 /* Process Unlocked */
473 __HAL_UNLOCK(hsdram);
474
475 return HAL_OK;
476 }
477
478 /**
479 * @brief Writes 32-bit data buffer to SDRAM memory.
480 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
481 * the configuration information for SDRAM module.
482 * @param pAddress: Pointer to write start address
483 * @param pSrcBuffer: Pointer to source buffer to write
484 * @param BufferSize: Size of the buffer to write to memory
485 * @retval HAL status
486 */
HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)487 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
488 {
489 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
490 uint32_t tmp = 0;
491
492 /* Process Locked */
493 __HAL_LOCK(hsdram);
494
495 /* Check the SDRAM controller state */
496 tmp = hsdram->State;
497
498 if (tmp == HAL_SDRAM_STATE_BUSY) {
499 return HAL_BUSY;
500 } else if ((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) {
501 return HAL_ERROR;
502 }
503
504 /* Write data to memory */
505 for (; BufferSize != 0; BufferSize--) {
506 *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
507 pSrcBuffer++;
508 pSdramAddress++;
509 }
510
511 /* Process Unlocked */
512 __HAL_UNLOCK(hsdram);
513
514 return HAL_OK;
515 }
516
517 /**
518 * @brief Reads a Words data from the SDRAM memory using DMA transfer.
519 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
520 * the configuration information for SDRAM module.
521 * @param pAddress: Pointer to read start address
522 * @param pDstBuffer: Pointer to destination buffer
523 * @param BufferSize: Size of the buffer to read from memory
524 * @retval HAL status
525 */
HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)526 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
527 {
528 uint32_t tmp = 0;
529
530 /* Process Locked */
531 __HAL_LOCK(hsdram);
532
533 /* Check the SDRAM controller state */
534 tmp = hsdram->State;
535
536 if (tmp == HAL_SDRAM_STATE_BUSY) {
537 return HAL_BUSY;
538 } else if (tmp == HAL_SDRAM_STATE_PRECHARGED) {
539 return HAL_ERROR;
540 }
541
542 /* Configure DMA user callbacks */
543 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
544 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
545
546 /* Enable the DMA Stream */
547 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
548
549 /* Process Unlocked */
550 __HAL_UNLOCK(hsdram);
551
552 return HAL_OK;
553 }
554
555 /**
556 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
557 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
558 * the configuration information for SDRAM module.
559 * @param pAddress: Pointer to write start address
560 * @param pSrcBuffer: Pointer to source buffer to write
561 * @param BufferSize: Size of the buffer to write to memory
562 * @retval HAL status
563 */
HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)564 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
565 {
566 uint32_t tmp = 0;
567
568 /* Process Locked */
569 __HAL_LOCK(hsdram);
570
571 /* Check the SDRAM controller state */
572 tmp = hsdram->State;
573
574 if (tmp == HAL_SDRAM_STATE_BUSY) {
575 return HAL_BUSY;
576 } else if ((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) {
577 return HAL_ERROR;
578 }
579
580 /* Configure DMA user callbacks */
581 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
582 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
583
584 /* Enable the DMA Stream */
585 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
586
587 /* Process Unlocked */
588 __HAL_UNLOCK(hsdram);
589
590 return HAL_OK;
591 }
592
593 /**
594 * @}
595 */
596
597 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
598 * @brief management functions
599 *
600 @verbatim
601 ==============================================================================
602 ##### SDRAM Control functions #####
603 ==============================================================================
604 [..]
605 This subsection provides a set of functions allowing to control dynamically
606 the SDRAM interface.
607
608 @endverbatim
609 * @{
610 */
611
612 /**
613 * @brief Enables dynamically SDRAM write protection.
614 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
615 * the configuration information for SDRAM module.
616 * @retval HAL status
617 */
HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef * hsdram)618 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
619 {
620 /* Check the SDRAM controller state */
621 if (hsdram->State == HAL_SDRAM_STATE_BUSY) {
622 return HAL_BUSY;
623 }
624
625 /* Update the SDRAM state */
626 hsdram->State = HAL_SDRAM_STATE_BUSY;
627
628 /* Enable write protection */
629 FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
630
631 /* Update the SDRAM state */
632 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
633
634 return HAL_OK;
635 }
636
637 /**
638 * @brief Disables dynamically SDRAM write protection.
639 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
640 * the configuration information for SDRAM module.
641 * @retval HAL status
642 */
HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef * hsdram)643 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
644 {
645 /* Check the SDRAM controller state */
646 if (hsdram->State == HAL_SDRAM_STATE_BUSY) {
647 return HAL_BUSY;
648 }
649
650 /* Update the SDRAM state */
651 hsdram->State = HAL_SDRAM_STATE_BUSY;
652
653 /* Disable write protection */
654 FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
655
656 /* Update the SDRAM state */
657 hsdram->State = HAL_SDRAM_STATE_READY;
658
659 return HAL_OK;
660 }
661
662 /**
663 * @brief Sends Command to the SDRAM bank.
664 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
665 * the configuration information for SDRAM module.
666 * @param Command: SDRAM command structure
667 * @param Timeout: Timeout duration
668 * @retval HAL status
669 */
HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef * hsdram,FMC_SDRAM_CommandTypeDef * Command,uint32_t Timeout)670 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
671 {
672 /* Check the SDRAM controller state */
673 if (hsdram->State == HAL_SDRAM_STATE_BUSY) {
674 return HAL_BUSY;
675 }
676
677 /* Update the SDRAM state */
678 hsdram->State = HAL_SDRAM_STATE_BUSY;
679
680 /* Send SDRAM command */
681 FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
682
683 /* Update the SDRAM controller state state */
684 if (Command->CommandMode == FMC_SDRAM_CMD_PALL) {
685 hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
686 } else {
687 hsdram->State = HAL_SDRAM_STATE_READY;
688 }
689
690 return HAL_OK;
691 }
692
693 /**
694 * @brief Programs the SDRAM Memory Refresh rate.
695 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
696 * the configuration information for SDRAM module.
697 * @param RefreshRate: The SDRAM refresh rate value
698 * @retval HAL status
699 */
HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef * hsdram,uint32_t RefreshRate)700 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
701 {
702 /* Check the SDRAM controller state */
703 if (hsdram->State == HAL_SDRAM_STATE_BUSY) {
704 return HAL_BUSY;
705 }
706
707 /* Update the SDRAM state */
708 hsdram->State = HAL_SDRAM_STATE_BUSY;
709
710 /* Program the refresh rate */
711 FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
712
713 /* Update the SDRAM state */
714 hsdram->State = HAL_SDRAM_STATE_READY;
715
716 return HAL_OK;
717 }
718
719 /**
720 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
721 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
722 * the configuration information for SDRAM module.
723 * @param AutoRefreshNumber: The SDRAM auto Refresh number
724 * @retval HAL status
725 */
HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef * hsdram,uint32_t AutoRefreshNumber)726 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
727 {
728 /* Check the SDRAM controller state */
729 if (hsdram->State == HAL_SDRAM_STATE_BUSY) {
730 return HAL_BUSY;
731 }
732
733 /* Update the SDRAM state */
734 hsdram->State = HAL_SDRAM_STATE_BUSY;
735
736 /* Set the Auto-Refresh number */
737 FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
738
739 /* Update the SDRAM state */
740 hsdram->State = HAL_SDRAM_STATE_READY;
741
742 return HAL_OK;
743 }
744
745 /**
746 * @brief Returns the SDRAM memory current mode.
747 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
748 * the configuration information for SDRAM module.
749 * @retval The SDRAM memory mode.
750 */
HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef * hsdram)751 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
752 {
753 /* Return the SDRAM memory current mode */
754 return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
755 }
756
757 /**
758 * @}
759 */
760
761 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
762 * @brief Peripheral State functions
763 *
764 @verbatim
765 ==============================================================================
766 ##### SDRAM State functions #####
767 ==============================================================================
768 [..]
769 This subsection permits to get in run-time the status of the SDRAM controller
770 and the data flow.
771
772 @endverbatim
773 * @{
774 */
775
776 /**
777 * @brief Returns the SDRAM state.
778 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
779 * the configuration information for SDRAM module.
780 * @retval HAL state
781 */
HAL_SDRAM_GetState(SDRAM_HandleTypeDef * hsdram)782 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
783 {
784 return hsdram->State;
785 }
786
787 /**
788 * @}
789 */
790
791 /**
792 * @}
793 */
794 #endif /* HAL_SDRAM_MODULE_ENABLED */
795 /**
796 * @}
797 */
798
799 /**
800 * @}
801 */
802
803 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
804