1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Device driver for regulators in hi655x IC
4  *
5  * Copyright (c) 2016 HiSilicon Ltd.
6  *
7  * Authors:
8  * Chen Feng <puck.chen@hisilicon.com>
9  * Fei  Wang <w.f@huawei.com>
10  */
11 
12 #ifndef __HI655X_PMIC_H
13 #define __HI655X_PMIC_H
14 
15 #include <linux/gpio/consumer.h>
16 
17 /* Hi655x registers are mapped to memory bus in 4 bytes stride */
18 #define HI655X_STRIDE                   4
19 #define HI655X_BUS_ADDR(x)              ((x) << 2)
20 
21 #define HI655X_BITS                     8
22 
23 #define HI655X_NR_IRQ                   32
24 
25 #define HI655X_IRQ_STAT_BASE            (0x003 << 2)
26 #define HI655X_IRQ_MASK_BASE            (0x007 << 2)
27 #define HI655X_ANA_IRQM_BASE            (0x1b5 << 2)
28 #define HI655X_IRQ_ARRAY                4
29 #define HI655X_IRQ_MASK                 0xFF
30 #define HI655X_IRQ_CLR                  0xFF
31 #define HI655X_VER_REG                  0x00
32 
33 #define PMU_VER_START                   0x10
34 #define PMU_VER_END                     0x38
35 
36 #define RESERVE_INT                     7
37 #define PWRON_D20R_INT                  6
38 #define PWRON_D20F_INT                  5
39 #define PWRON_D4SR_INT                  4
40 #define VSYS_6P0_D200UR_INT             3
41 #define VSYS_UV_D3R_INT                 2
42 #define VSYS_2P5_R_INT                  1
43 #define OTMP_D1R_INT                    0
44 
45 #define RESERVE_INT_MASK                BIT(RESERVE_INT)
46 #define PWRON_D20R_INT_MASK             BIT(PWRON_D20R_INT)
47 #define PWRON_D20F_INT_MASK             BIT(PWRON_D20F_INT)
48 #define PWRON_D4SR_INT_MASK             BIT(PWRON_D4SR_INT)
49 #define VSYS_6P0_D200UR_INT_MASK        BIT(VSYS_6P0_D200UR_INT)
50 #define VSYS_UV_D3R_INT_MASK            BIT(VSYS_UV_D3R_INT)
51 #define VSYS_2P5_R_INT_MASK             BIT(VSYS_2P5_R_INT)
52 #define OTMP_D1R_INT_MASK               BIT(OTMP_D1R_INT)
53 
54 struct hi655x_pmic {
55 	struct resource *res;
56 	struct device *dev;
57 	struct regmap *regmap;
58 	struct gpio_desc *gpio;
59 	unsigned int ver;
60 	struct regmap_irq_chip_data *irq_data;
61 };
62 
63 #endif
64