1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #ifndef __HNAE3_H
5 #define __HNAE3_H
6
7 /* Names used in this framework:
8 * ae handle (handle):
9 * a set of queues provided by AE
10 * ring buffer queue (rbq):
11 * the channel between upper layer and the AE, can do tx and rx
12 * ring:
13 * a tx or rx channel within a rbq
14 * ring description (desc):
15 * an element in the ring with packet information
16 * buffer:
17 * a memory region referred by desc with the full packet payload
18 *
19 * "num" means a static number set as a parameter, "count" mean a dynamic
20 * number set while running
21 * "cb" means control block
22 */
23
24 #include <linux/acpi.h>
25 #include <linux/dcbnl.h>
26 #include <linux/delay.h>
27 #include <linux/device.h>
28 #include <linux/ethtool.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/pci.h>
32 #include <linux/pkt_sched.h>
33 #include <linux/types.h>
34 #include <net/pkt_cls.h>
35 #include <net/pkt_sched.h>
36
37 #define HNAE3_MOD_VERSION "1.0"
38
39 #define HNAE3_MIN_VECTOR_NUM 2 /* first one for misc, another for IO */
40
41 /* Device version */
42 #define HNAE3_DEVICE_VERSION_V1 0x00020
43 #define HNAE3_DEVICE_VERSION_V2 0x00021
44 #define HNAE3_DEVICE_VERSION_V3 0x00030
45
46 #define HNAE3_PCI_REVISION_BIT_SIZE 8
47
48 /* Device IDs */
49 #define HNAE3_DEV_ID_GE 0xA220
50 #define HNAE3_DEV_ID_25GE 0xA221
51 #define HNAE3_DEV_ID_25GE_RDMA 0xA222
52 #define HNAE3_DEV_ID_25GE_RDMA_MACSEC 0xA223
53 #define HNAE3_DEV_ID_50GE_RDMA 0xA224
54 #define HNAE3_DEV_ID_50GE_RDMA_MACSEC 0xA225
55 #define HNAE3_DEV_ID_100G_RDMA_MACSEC 0xA226
56 #define HNAE3_DEV_ID_200G_RDMA 0xA228
57 #define HNAE3_DEV_ID_VF 0xA22E
58 #define HNAE3_DEV_ID_RDMA_DCB_PFC_VF 0xA22F
59
60 #define HNAE3_CLASS_NAME_SIZE 16
61
62 #define HNAE3_DEV_INITED_B 0x0
63 #define HNAE3_DEV_SUPPORT_ROCE_B 0x1
64 #define HNAE3_DEV_SUPPORT_DCB_B 0x2
65 #define HNAE3_KNIC_CLIENT_INITED_B 0x3
66 #define HNAE3_UNIC_CLIENT_INITED_B 0x4
67 #define HNAE3_ROCE_CLIENT_INITED_B 0x5
68
69 #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) | \
70 BIT(HNAE3_DEV_SUPPORT_ROCE_B))
71
72 #define hnae3_dev_roce_supported(hdev) \
73 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)
74
75 #define hnae3_dev_dcb_supported(hdev) \
76 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B)
77
78 enum HNAE3_DEV_CAP_BITS {
79 HNAE3_DEV_SUPPORT_FD_B,
80 HNAE3_DEV_SUPPORT_GRO_B,
81 HNAE3_DEV_SUPPORT_FEC_B,
82 HNAE3_DEV_SUPPORT_UDP_GSO_B,
83 HNAE3_DEV_SUPPORT_QB_B,
84 HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B,
85 HNAE3_DEV_SUPPORT_PTP_B,
86 HNAE3_DEV_SUPPORT_INT_QL_B,
87 HNAE3_DEV_SUPPORT_HW_TX_CSUM_B,
88 HNAE3_DEV_SUPPORT_TX_PUSH_B,
89 HNAE3_DEV_SUPPORT_PHY_IMP_B,
90 HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B,
91 HNAE3_DEV_SUPPORT_HW_PAD_B,
92 HNAE3_DEV_SUPPORT_STASH_B,
93 HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B,
94 HNAE3_DEV_SUPPORT_PAUSE_B,
95 HNAE3_DEV_SUPPORT_RAS_IMP_B,
96 HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
97 HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B,
98 HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,
99 HNAE3_DEV_SUPPORT_MC_MAC_MNG_B,
100 HNAE3_DEV_SUPPORT_CQ_B,
101 HNAE3_DEV_SUPPORT_FEC_STATS_B,
102 HNAE3_DEV_SUPPORT_LANE_NUM_B,
103 };
104
105 #define hnae3_ae_dev_fd_supported(ae_dev) \
106 test_bit(HNAE3_DEV_SUPPORT_FD_B, (ae_dev)->caps)
107
108 #define hnae3_ae_dev_gro_supported(ae_dev) \
109 test_bit(HNAE3_DEV_SUPPORT_GRO_B, (ae_dev)->caps)
110
111 #define hnae3_dev_fec_supported(hdev) \
112 test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps)
113
114 #define hnae3_dev_udp_gso_supported(hdev) \
115 test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps)
116
117 #define hnae3_dev_qb_supported(hdev) \
118 test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps)
119
120 #define hnae3_dev_fd_forward_tc_supported(hdev) \
121 test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps)
122
123 #define hnae3_dev_ptp_supported(hdev) \
124 test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps)
125
126 #define hnae3_dev_int_ql_supported(hdev) \
127 test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps)
128
129 #define hnae3_dev_hw_csum_supported(hdev) \
130 test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, (hdev)->ae_dev->caps)
131
132 #define hnae3_dev_tx_push_supported(hdev) \
133 test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps)
134
135 #define hnae3_dev_phy_imp_supported(hdev) \
136 test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps)
137
138 #define hnae3_dev_ras_imp_supported(hdev) \
139 test_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, (hdev)->ae_dev->caps)
140
141 #define hnae3_dev_tqp_txrx_indep_supported(hdev) \
142 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps)
143
144 #define hnae3_dev_hw_pad_supported(hdev) \
145 test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps)
146
147 #define hnae3_dev_stash_supported(hdev) \
148 test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps)
149
150 #define hnae3_dev_pause_supported(hdev) \
151 test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, (hdev)->ae_dev->caps)
152
153 #define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \
154 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps)
155
156 #define hnae3_ae_dev_rxd_adv_layout_supported(ae_dev) \
157 test_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, (ae_dev)->caps)
158
159 #define hnae3_ae_dev_mc_mac_mng_supported(ae_dev) \
160 test_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, (ae_dev)->caps)
161
162 #define hnae3_ae_dev_cq_supported(ae_dev) \
163 test_bit(HNAE3_DEV_SUPPORT_CQ_B, (ae_dev)->caps)
164
165 #define hnae3_ae_dev_fec_stats_supported(ae_dev) \
166 test_bit(HNAE3_DEV_SUPPORT_FEC_STATS_B, (ae_dev)->caps)
167
168 #define hnae3_ae_dev_lane_num_supported(ae_dev) \
169 test_bit(HNAE3_DEV_SUPPORT_LANE_NUM_B, (ae_dev)->caps)
170
171 enum HNAE3_PF_CAP_BITS {
172 HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,
173 };
174 #define ring_ptr_move_fw(ring, p) \
175 ((ring)->p = ((ring)->p + 1) % (ring)->desc_num)
176 #define ring_ptr_move_bw(ring, p) \
177 ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num)
178
179 struct hnae3_handle;
180
181 struct hnae3_queue {
182 void __iomem *io_base;
183 void __iomem *mem_base;
184 struct hnae3_ae_algo *ae_algo;
185 struct hnae3_handle *handle;
186 int tqp_index; /* index in a handle */
187 u32 buf_size; /* size for hnae_desc->addr, preset by AE */
188 u16 tx_desc_num; /* total number of tx desc */
189 u16 rx_desc_num; /* total number of rx desc */
190 };
191
192 struct hns3_mac_stats {
193 u64 tx_pause_cnt;
194 u64 rx_pause_cnt;
195 };
196
197 /* hnae3 loop mode */
198 enum hnae3_loop {
199 HNAE3_LOOP_EXTERNAL,
200 HNAE3_LOOP_APP,
201 HNAE3_LOOP_SERIAL_SERDES,
202 HNAE3_LOOP_PARALLEL_SERDES,
203 HNAE3_LOOP_PHY,
204 HNAE3_LOOP_NONE,
205 };
206
207 enum hnae3_client_type {
208 HNAE3_CLIENT_KNIC,
209 HNAE3_CLIENT_ROCE,
210 };
211
212 /* mac media type */
213 enum hnae3_media_type {
214 HNAE3_MEDIA_TYPE_UNKNOWN,
215 HNAE3_MEDIA_TYPE_FIBER,
216 HNAE3_MEDIA_TYPE_COPPER,
217 HNAE3_MEDIA_TYPE_BACKPLANE,
218 HNAE3_MEDIA_TYPE_NONE,
219 };
220
221 /* must be consistent with definition in firmware */
222 enum hnae3_module_type {
223 HNAE3_MODULE_TYPE_UNKNOWN = 0x00,
224 HNAE3_MODULE_TYPE_FIBRE_LR = 0x01,
225 HNAE3_MODULE_TYPE_FIBRE_SR = 0x02,
226 HNAE3_MODULE_TYPE_AOC = 0x03,
227 HNAE3_MODULE_TYPE_CR = 0x04,
228 HNAE3_MODULE_TYPE_KR = 0x05,
229 HNAE3_MODULE_TYPE_TP = 0x06,
230 };
231
232 enum hnae3_fec_mode {
233 HNAE3_FEC_AUTO = 0,
234 HNAE3_FEC_BASER,
235 HNAE3_FEC_RS,
236 HNAE3_FEC_LLRS,
237 HNAE3_FEC_NONE,
238 HNAE3_FEC_USER_DEF,
239 };
240
241 enum hnae3_reset_notify_type {
242 HNAE3_UP_CLIENT,
243 HNAE3_DOWN_CLIENT,
244 HNAE3_INIT_CLIENT,
245 HNAE3_UNINIT_CLIENT,
246 };
247
248 enum hnae3_hw_error_type {
249 HNAE3_PPU_POISON_ERROR,
250 HNAE3_CMDQ_ECC_ERROR,
251 HNAE3_IMP_RD_POISON_ERROR,
252 HNAE3_ROCEE_AXI_RESP_ERROR,
253 };
254
255 enum hnae3_reset_type {
256 HNAE3_VF_RESET,
257 HNAE3_VF_FUNC_RESET,
258 HNAE3_VF_PF_FUNC_RESET,
259 HNAE3_VF_FULL_RESET,
260 HNAE3_FLR_RESET,
261 HNAE3_FUNC_RESET,
262 HNAE3_GLOBAL_RESET,
263 HNAE3_IMP_RESET,
264 HNAE3_NONE_RESET,
265 HNAE3_MAX_RESET,
266 };
267
268 enum hnae3_port_base_vlan_state {
269 HNAE3_PORT_BASE_VLAN_DISABLE,
270 HNAE3_PORT_BASE_VLAN_ENABLE,
271 HNAE3_PORT_BASE_VLAN_MODIFY,
272 HNAE3_PORT_BASE_VLAN_NOCHANGE,
273 };
274
275 enum hnae3_dbg_cmd {
276 HNAE3_DBG_CMD_TM_NODES,
277 HNAE3_DBG_CMD_TM_PRI,
278 HNAE3_DBG_CMD_TM_QSET,
279 HNAE3_DBG_CMD_TM_MAP,
280 HNAE3_DBG_CMD_TM_PG,
281 HNAE3_DBG_CMD_TM_PORT,
282 HNAE3_DBG_CMD_TC_SCH_INFO,
283 HNAE3_DBG_CMD_QOS_PAUSE_CFG,
284 HNAE3_DBG_CMD_QOS_PRI_MAP,
285 HNAE3_DBG_CMD_QOS_DSCP_MAP,
286 HNAE3_DBG_CMD_QOS_BUF_CFG,
287 HNAE3_DBG_CMD_DEV_INFO,
288 HNAE3_DBG_CMD_TX_BD,
289 HNAE3_DBG_CMD_RX_BD,
290 HNAE3_DBG_CMD_MAC_UC,
291 HNAE3_DBG_CMD_MAC_MC,
292 HNAE3_DBG_CMD_MNG_TBL,
293 HNAE3_DBG_CMD_LOOPBACK,
294 HNAE3_DBG_CMD_PTP_INFO,
295 HNAE3_DBG_CMD_INTERRUPT_INFO,
296 HNAE3_DBG_CMD_RESET_INFO,
297 HNAE3_DBG_CMD_IMP_INFO,
298 HNAE3_DBG_CMD_NCL_CONFIG,
299 HNAE3_DBG_CMD_REG_BIOS_COMMON,
300 HNAE3_DBG_CMD_REG_SSU,
301 HNAE3_DBG_CMD_REG_IGU_EGU,
302 HNAE3_DBG_CMD_REG_RPU,
303 HNAE3_DBG_CMD_REG_NCSI,
304 HNAE3_DBG_CMD_REG_RTC,
305 HNAE3_DBG_CMD_REG_PPP,
306 HNAE3_DBG_CMD_REG_RCB,
307 HNAE3_DBG_CMD_REG_TQP,
308 HNAE3_DBG_CMD_REG_MAC,
309 HNAE3_DBG_CMD_REG_DCB,
310 HNAE3_DBG_CMD_VLAN_CONFIG,
311 HNAE3_DBG_CMD_QUEUE_MAP,
312 HNAE3_DBG_CMD_RX_QUEUE_INFO,
313 HNAE3_DBG_CMD_TX_QUEUE_INFO,
314 HNAE3_DBG_CMD_FD_TCAM,
315 HNAE3_DBG_CMD_FD_COUNTER,
316 HNAE3_DBG_CMD_MAC_TNL_STATUS,
317 HNAE3_DBG_CMD_SERV_INFO,
318 HNAE3_DBG_CMD_UMV_INFO,
319 HNAE3_DBG_CMD_PAGE_POOL_INFO,
320 HNAE3_DBG_CMD_COAL_INFO,
321 HNAE3_DBG_CMD_UNKNOWN,
322 };
323
324 enum hnae3_tc_map_mode {
325 HNAE3_TC_MAP_MODE_PRIO,
326 HNAE3_TC_MAP_MODE_DSCP,
327 };
328
329 struct hnae3_vector_info {
330 u8 __iomem *io_addr;
331 int vector;
332 };
333
334 #define HNAE3_RING_TYPE_B 0
335 #define HNAE3_RING_TYPE_TX 0
336 #define HNAE3_RING_TYPE_RX 1
337 #define HNAE3_RING_GL_IDX_S 0
338 #define HNAE3_RING_GL_IDX_M GENMASK(1, 0)
339 #define HNAE3_RING_GL_RX 0
340 #define HNAE3_RING_GL_TX 1
341
342 #define HNAE3_FW_VERSION_BYTE3_SHIFT 24
343 #define HNAE3_FW_VERSION_BYTE3_MASK GENMASK(31, 24)
344 #define HNAE3_FW_VERSION_BYTE2_SHIFT 16
345 #define HNAE3_FW_VERSION_BYTE2_MASK GENMASK(23, 16)
346 #define HNAE3_FW_VERSION_BYTE1_SHIFT 8
347 #define HNAE3_FW_VERSION_BYTE1_MASK GENMASK(15, 8)
348 #define HNAE3_FW_VERSION_BYTE0_SHIFT 0
349 #define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0)
350
351 struct hnae3_ring_chain_node {
352 struct hnae3_ring_chain_node *next;
353 u32 tqp_index;
354 u32 flag;
355 u32 int_gl_idx;
356 };
357
358 #define HNAE3_IS_TX_RING(node) \
359 (((node)->flag & 1 << HNAE3_RING_TYPE_B) == HNAE3_RING_TYPE_TX)
360
361 /* device specification info from firmware */
362 struct hnae3_dev_specs {
363 u32 mac_entry_num; /* number of mac-vlan table entry */
364 u32 mng_entry_num; /* number of manager table entry */
365 u32 max_tm_rate;
366 u16 rss_ind_tbl_size;
367 u16 rss_key_size;
368 u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */
369 u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */
370 u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */
371 u16 max_frm_size;
372 u16 max_qset_num;
373 u16 umv_size;
374 u16 mc_mac_size;
375 u32 mac_stats_num;
376 };
377
378 struct hnae3_client_ops {
379 int (*init_instance)(struct hnae3_handle *handle);
380 void (*uninit_instance)(struct hnae3_handle *handle, bool reset);
381 void (*link_status_change)(struct hnae3_handle *handle, bool state);
382 int (*reset_notify)(struct hnae3_handle *handle,
383 enum hnae3_reset_notify_type type);
384 void (*process_hw_error)(struct hnae3_handle *handle,
385 enum hnae3_hw_error_type);
386 };
387
388 #define HNAE3_CLIENT_NAME_LENGTH 16
389 struct hnae3_client {
390 char name[HNAE3_CLIENT_NAME_LENGTH];
391 unsigned long state;
392 enum hnae3_client_type type;
393 const struct hnae3_client_ops *ops;
394 struct list_head node;
395 };
396
397 #define HNAE3_DEV_CAPS_MAX_NUM 96
398 struct hnae3_ae_dev {
399 struct pci_dev *pdev;
400 const struct hnae3_ae_ops *ops;
401 struct list_head node;
402 u32 flag;
403 unsigned long hw_err_reset_req;
404 struct hnae3_dev_specs dev_specs;
405 u32 dev_version;
406 unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)];
407 void *priv;
408 };
409
410 /* This struct defines the operation on the handle.
411 *
412 * init_ae_dev(): (mandatory)
413 * Get PF configure from pci_dev and initialize PF hardware
414 * uninit_ae_dev()
415 * Disable PF device and release PF resource
416 * register_client
417 * Register client to ae_dev
418 * unregister_client()
419 * Unregister client from ae_dev
420 * start()
421 * Enable the hardware
422 * stop()
423 * Disable the hardware
424 * start_client()
425 * Inform the hclge that client has been started
426 * stop_client()
427 * Inform the hclge that client has been stopped
428 * get_status()
429 * Get the carrier state of the back channel of the handle, 1 for ok, 0 for
430 * non-ok
431 * get_ksettings_an_result()
432 * Get negotiation status,speed and duplex
433 * get_media_type()
434 * Get media type of MAC
435 * check_port_speed()
436 * Check target speed whether is supported
437 * adjust_link()
438 * Adjust link status
439 * set_loopback()
440 * Set loopback
441 * set_promisc_mode
442 * Set promisc mode
443 * request_update_promisc_mode
444 * request to hclge(vf) to update promisc mode
445 * set_mtu()
446 * set mtu
447 * get_pauseparam()
448 * get tx and rx of pause frame use
449 * set_pauseparam()
450 * set tx and rx of pause frame use
451 * set_autoneg()
452 * set auto autonegotiation of pause frame use
453 * get_autoneg()
454 * get auto autonegotiation of pause frame use
455 * restart_autoneg()
456 * restart autonegotiation
457 * halt_autoneg()
458 * halt/resume autonegotiation when autonegotiation on
459 * get_coalesce_usecs()
460 * get usecs to delay a TX interrupt after a packet is sent
461 * get_rx_max_coalesced_frames()
462 * get Maximum number of packets to be sent before a TX interrupt.
463 * set_coalesce_usecs()
464 * set usecs to delay a TX interrupt after a packet is sent
465 * set_coalesce_frames()
466 * set Maximum number of packets to be sent before a TX interrupt.
467 * get_mac_addr()
468 * get mac address
469 * set_mac_addr()
470 * set mac address
471 * add_uc_addr
472 * Add unicast addr to mac table
473 * rm_uc_addr
474 * Remove unicast addr from mac table
475 * set_mc_addr()
476 * Set multicast address
477 * add_mc_addr
478 * Add multicast address to mac table
479 * rm_mc_addr
480 * Remove multicast address from mac table
481 * update_stats()
482 * Update Old network device statistics
483 * get_mac_stats()
484 * get mac pause statistics including tx_cnt and rx_cnt
485 * get_ethtool_stats()
486 * Get ethtool network device statistics
487 * get_strings()
488 * Get a set of strings that describe the requested objects
489 * get_sset_count()
490 * Get number of strings that @get_strings will write
491 * update_led_status()
492 * Update the led status
493 * set_led_id()
494 * Set led id
495 * get_regs()
496 * Get regs dump
497 * get_regs_len()
498 * Get the len of the regs dump
499 * get_rss_key_size()
500 * Get rss key size
501 * get_rss()
502 * Get rss table
503 * set_rss()
504 * Set rss table
505 * get_tc_size()
506 * Get tc size of handle
507 * get_vector()
508 * Get vector number and vector information
509 * put_vector()
510 * Put the vector in hdev
511 * map_ring_to_vector()
512 * Map rings to vector
513 * unmap_ring_from_vector()
514 * Unmap rings from vector
515 * reset_queue()
516 * Reset queue
517 * get_fw_version()
518 * Get firmware version
519 * get_mdix_mode()
520 * Get media typr of phy
521 * enable_vlan_filter()
522 * Enable vlan filter
523 * set_vlan_filter()
524 * Set vlan filter config of Ports
525 * set_vf_vlan_filter()
526 * Set vlan filter config of vf
527 * enable_hw_strip_rxvtag()
528 * Enable/disable hardware strip vlan tag of packets received
529 * set_gro_en
530 * Enable/disable HW GRO
531 * add_arfs_entry
532 * Check the 5-tuples of flow, and create flow director rule
533 * get_vf_config
534 * Get the VF configuration setting by the host
535 * set_vf_link_state
536 * Set VF link status
537 * set_vf_spoofchk
538 * Enable/disable spoof check for specified vf
539 * set_vf_trust
540 * Enable/disable trust for specified vf, if the vf being trusted, then
541 * it can enable promisc mode
542 * set_vf_rate
543 * Set the max tx rate of specified vf.
544 * set_vf_mac
545 * Configure the default MAC for specified VF
546 * get_module_eeprom
547 * Get the optical module eeprom info.
548 * add_cls_flower
549 * Add clsflower rule
550 * del_cls_flower
551 * Delete clsflower rule
552 * cls_flower_active
553 * Check if any cls flower rule exist
554 * dbg_read_cmd
555 * Execute debugfs read command.
556 * set_tx_hwts_info
557 * Save information for 1588 tx packet
558 * get_rx_hwts
559 * Get 1588 rx hwstamp
560 * get_ts_info
561 * Get phc info
562 * clean_vf_config
563 * Clean residual vf info after disable sriov
564 */
565 struct hnae3_ae_ops {
566 int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev);
567 void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev);
568 void (*reset_prepare)(struct hnae3_ae_dev *ae_dev,
569 enum hnae3_reset_type rst_type);
570 void (*reset_done)(struct hnae3_ae_dev *ae_dev);
571 int (*init_client_instance)(struct hnae3_client *client,
572 struct hnae3_ae_dev *ae_dev);
573 void (*uninit_client_instance)(struct hnae3_client *client,
574 struct hnae3_ae_dev *ae_dev);
575 int (*start)(struct hnae3_handle *handle);
576 void (*stop)(struct hnae3_handle *handle);
577 int (*client_start)(struct hnae3_handle *handle);
578 void (*client_stop)(struct hnae3_handle *handle);
579 int (*get_status)(struct hnae3_handle *handle);
580 void (*get_ksettings_an_result)(struct hnae3_handle *handle,
581 u8 *auto_neg, u32 *speed, u8 *duplex,
582 u32 *lane_num);
583
584 int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed,
585 u8 duplex, u8 lane_num);
586
587 void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type,
588 u8 *module_type);
589 int (*check_port_speed)(struct hnae3_handle *handle, u32 speed);
590 void (*get_fec_stats)(struct hnae3_handle *handle,
591 struct ethtool_fec_stats *fec_stats);
592 void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability,
593 u8 *fec_mode);
594 int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode);
595 void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex);
596 int (*set_loopback)(struct hnae3_handle *handle,
597 enum hnae3_loop loop_mode, bool en);
598
599 int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc,
600 bool en_mc_pmc);
601 void (*request_update_promisc_mode)(struct hnae3_handle *handle);
602 int (*set_mtu)(struct hnae3_handle *handle, int new_mtu);
603
604 void (*get_pauseparam)(struct hnae3_handle *handle,
605 u32 *auto_neg, u32 *rx_en, u32 *tx_en);
606 int (*set_pauseparam)(struct hnae3_handle *handle,
607 u32 auto_neg, u32 rx_en, u32 tx_en);
608
609 int (*set_autoneg)(struct hnae3_handle *handle, bool enable);
610 int (*get_autoneg)(struct hnae3_handle *handle);
611 int (*restart_autoneg)(struct hnae3_handle *handle);
612 int (*halt_autoneg)(struct hnae3_handle *handle, bool halt);
613
614 void (*get_coalesce_usecs)(struct hnae3_handle *handle,
615 u32 *tx_usecs, u32 *rx_usecs);
616 void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle,
617 u32 *tx_frames, u32 *rx_frames);
618 int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout);
619 int (*set_coalesce_frames)(struct hnae3_handle *handle,
620 u32 coalesce_frames);
621 void (*get_coalesce_range)(struct hnae3_handle *handle,
622 u32 *tx_frames_low, u32 *rx_frames_low,
623 u32 *tx_frames_high, u32 *rx_frames_high,
624 u32 *tx_usecs_low, u32 *rx_usecs_low,
625 u32 *tx_usecs_high, u32 *rx_usecs_high);
626
627 void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p);
628 int (*set_mac_addr)(struct hnae3_handle *handle, const void *p,
629 bool is_first);
630 int (*do_ioctl)(struct hnae3_handle *handle,
631 struct ifreq *ifr, int cmd);
632 int (*add_uc_addr)(struct hnae3_handle *handle,
633 const unsigned char *addr);
634 int (*rm_uc_addr)(struct hnae3_handle *handle,
635 const unsigned char *addr);
636 int (*set_mc_addr)(struct hnae3_handle *handle, void *addr);
637 int (*add_mc_addr)(struct hnae3_handle *handle,
638 const unsigned char *addr);
639 int (*rm_mc_addr)(struct hnae3_handle *handle,
640 const unsigned char *addr);
641 void (*set_tso_stats)(struct hnae3_handle *handle, int enable);
642 void (*update_stats)(struct hnae3_handle *handle,
643 struct net_device_stats *net_stats);
644 void (*get_stats)(struct hnae3_handle *handle, u64 *data);
645 void (*get_mac_stats)(struct hnae3_handle *handle,
646 struct hns3_mac_stats *mac_stats);
647 void (*get_strings)(struct hnae3_handle *handle,
648 u32 stringset, u8 *data);
649 int (*get_sset_count)(struct hnae3_handle *handle, int stringset);
650
651 void (*get_regs)(struct hnae3_handle *handle, u32 *version,
652 void *data);
653 int (*get_regs_len)(struct hnae3_handle *handle);
654
655 u32 (*get_rss_key_size)(struct hnae3_handle *handle);
656 int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key,
657 u8 *hfunc);
658 int (*set_rss)(struct hnae3_handle *handle, const u32 *indir,
659 const u8 *key, const u8 hfunc);
660 int (*set_rss_tuple)(struct hnae3_handle *handle,
661 struct ethtool_rxnfc *cmd);
662 int (*get_rss_tuple)(struct hnae3_handle *handle,
663 struct ethtool_rxnfc *cmd);
664
665 int (*get_tc_size)(struct hnae3_handle *handle);
666
667 int (*get_vector)(struct hnae3_handle *handle, u16 vector_num,
668 struct hnae3_vector_info *vector_info);
669 int (*put_vector)(struct hnae3_handle *handle, int vector_num);
670 int (*map_ring_to_vector)(struct hnae3_handle *handle,
671 int vector_num,
672 struct hnae3_ring_chain_node *vr_chain);
673 int (*unmap_ring_from_vector)(struct hnae3_handle *handle,
674 int vector_num,
675 struct hnae3_ring_chain_node *vr_chain);
676
677 int (*reset_queue)(struct hnae3_handle *handle);
678 u32 (*get_fw_version)(struct hnae3_handle *handle);
679 void (*get_mdix_mode)(struct hnae3_handle *handle,
680 u8 *tp_mdix_ctrl, u8 *tp_mdix);
681
682 int (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable);
683 int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto,
684 u16 vlan_id, bool is_kill);
685 int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid,
686 u16 vlan, u8 qos, __be16 proto);
687 int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable);
688 void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle);
689 enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev,
690 unsigned long *addr);
691 void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev,
692 enum hnae3_reset_type rst_type);
693 void (*get_channels)(struct hnae3_handle *handle,
694 struct ethtool_channels *ch);
695 void (*get_tqps_and_rss_info)(struct hnae3_handle *h,
696 u16 *alloc_tqps, u16 *max_rss_size);
697 int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num,
698 bool rxfh_configured);
699 void (*get_flowctrl_adv)(struct hnae3_handle *handle,
700 u32 *flowctrl_adv);
701 int (*set_led_id)(struct hnae3_handle *handle,
702 enum ethtool_phys_id_state status);
703 void (*get_link_mode)(struct hnae3_handle *handle,
704 unsigned long *supported,
705 unsigned long *advertising);
706 int (*add_fd_entry)(struct hnae3_handle *handle,
707 struct ethtool_rxnfc *cmd);
708 int (*del_fd_entry)(struct hnae3_handle *handle,
709 struct ethtool_rxnfc *cmd);
710 int (*get_fd_rule_cnt)(struct hnae3_handle *handle,
711 struct ethtool_rxnfc *cmd);
712 int (*get_fd_rule_info)(struct hnae3_handle *handle,
713 struct ethtool_rxnfc *cmd);
714 int (*get_fd_all_rules)(struct hnae3_handle *handle,
715 struct ethtool_rxnfc *cmd, u32 *rule_locs);
716 void (*enable_fd)(struct hnae3_handle *handle, bool enable);
717 int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id,
718 u16 flow_id, struct flow_keys *fkeys);
719 int (*dbg_read_cmd)(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd,
720 char *buf, int len);
721 pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev);
722 bool (*get_hw_reset_stat)(struct hnae3_handle *handle);
723 bool (*ae_dev_resetting)(struct hnae3_handle *handle);
724 unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle);
725 int (*set_gro_en)(struct hnae3_handle *handle, bool enable);
726 u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id);
727 void (*set_timer_task)(struct hnae3_handle *handle, bool enable);
728 int (*mac_connect_phy)(struct hnae3_handle *handle);
729 void (*mac_disconnect_phy)(struct hnae3_handle *handle);
730 int (*get_vf_config)(struct hnae3_handle *handle, int vf,
731 struct ifla_vf_info *ivf);
732 int (*set_vf_link_state)(struct hnae3_handle *handle, int vf,
733 int link_state);
734 int (*set_vf_spoofchk)(struct hnae3_handle *handle, int vf,
735 bool enable);
736 int (*set_vf_trust)(struct hnae3_handle *handle, int vf, bool enable);
737 int (*set_vf_rate)(struct hnae3_handle *handle, int vf,
738 int min_tx_rate, int max_tx_rate, bool force);
739 int (*set_vf_mac)(struct hnae3_handle *handle, int vf, u8 *p);
740 int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset,
741 u32 len, u8 *data);
742 bool (*get_cmdq_stat)(struct hnae3_handle *handle);
743 int (*add_cls_flower)(struct hnae3_handle *handle,
744 struct flow_cls_offload *cls_flower, int tc);
745 int (*del_cls_flower)(struct hnae3_handle *handle,
746 struct flow_cls_offload *cls_flower);
747 bool (*cls_flower_active)(struct hnae3_handle *handle);
748 int (*get_phy_link_ksettings)(struct hnae3_handle *handle,
749 struct ethtool_link_ksettings *cmd);
750 int (*set_phy_link_ksettings)(struct hnae3_handle *handle,
751 const struct ethtool_link_ksettings *cmd);
752 bool (*set_tx_hwts_info)(struct hnae3_handle *handle,
753 struct sk_buff *skb);
754 void (*get_rx_hwts)(struct hnae3_handle *handle, struct sk_buff *skb,
755 u32 nsec, u32 sec);
756 int (*get_ts_info)(struct hnae3_handle *handle,
757 struct ethtool_ts_info *info);
758 int (*get_link_diagnosis_info)(struct hnae3_handle *handle,
759 u32 *status_code);
760 void (*clean_vf_config)(struct hnae3_ae_dev *ae_dev, int num_vfs);
761 int (*get_dscp_prio)(struct hnae3_handle *handle, u8 dscp,
762 u8 *tc_map_mode, u8 *priority);
763 };
764
765 struct hnae3_dcb_ops {
766 /* IEEE 802.1Qaz std */
767 int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *);
768 int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *);
769 int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *);
770 int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *);
771 int (*ieee_setapp)(struct hnae3_handle *h, struct dcb_app *app);
772 int (*ieee_delapp)(struct hnae3_handle *h, struct dcb_app *app);
773
774 /* DCBX configuration */
775 u8 (*getdcbx)(struct hnae3_handle *);
776 u8 (*setdcbx)(struct hnae3_handle *, u8);
777
778 int (*setup_tc)(struct hnae3_handle *handle,
779 struct tc_mqprio_qopt_offload *mqprio_qopt);
780 };
781
782 struct hnae3_ae_algo {
783 const struct hnae3_ae_ops *ops;
784 struct list_head node;
785 const struct pci_device_id *pdev_id_table;
786 };
787
788 #define HNAE3_INT_NAME_LEN 32
789 #define HNAE3_ITR_COUNTDOWN_START 100
790
791 #define HNAE3_MAX_TC 8
792 #define HNAE3_MAX_USER_PRIO 8
793 struct hnae3_tc_info {
794 u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */
795 u16 tqp_count[HNAE3_MAX_TC];
796 u16 tqp_offset[HNAE3_MAX_TC];
797 u8 max_tc; /* Total number of TCs */
798 u8 num_tc; /* Total number of enabled TCs */
799 bool mqprio_active;
800 };
801
802 #define HNAE3_MAX_DSCP 64
803 #define HNAE3_PRIO_ID_INVALID 0xff
804 struct hnae3_knic_private_info {
805 struct net_device *netdev; /* Set by KNIC client when init instance */
806 u16 rss_size; /* Allocated RSS queues */
807 u16 req_rss_size;
808 u16 rx_buf_len;
809 u16 num_tx_desc;
810 u16 num_rx_desc;
811 u32 tx_spare_buf_size;
812
813 struct hnae3_tc_info tc_info;
814 u8 tc_map_mode;
815 u8 dscp_app_cnt;
816 u8 dscp_prio[HNAE3_MAX_DSCP];
817
818 u16 num_tqps; /* total number of TQPs in this handle */
819 struct hnae3_queue **tqp; /* array base of all TQPs in this instance */
820 const struct hnae3_dcb_ops *dcb_ops;
821
822 u16 int_rl_setting;
823 void __iomem *io_base;
824 };
825
826 struct hnae3_roce_private_info {
827 struct net_device *netdev;
828 void __iomem *roce_io_base;
829 void __iomem *roce_mem_base;
830 int base_vector;
831 int num_vectors;
832
833 /* The below attributes defined for RoCE client, hnae3 gives
834 * initial values to them, and RoCE client can modify and use
835 * them.
836 */
837 unsigned long reset_state;
838 unsigned long instance_state;
839 unsigned long state;
840 };
841
842 #define HNAE3_SUPPORT_APP_LOOPBACK BIT(0)
843 #define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1)
844 #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK BIT(2)
845 #define HNAE3_SUPPORT_VF BIT(3)
846 #define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK BIT(4)
847 #define HNAE3_SUPPORT_EXTERNAL_LOOPBACK BIT(5)
848
849 #define HNAE3_USER_UPE BIT(0) /* unicast promisc enabled by user */
850 #define HNAE3_USER_MPE BIT(1) /* mulitcast promisc enabled by user */
851 #define HNAE3_BPE BIT(2) /* broadcast promisc enable */
852 #define HNAE3_OVERFLOW_UPE BIT(3) /* unicast mac vlan overflow */
853 #define HNAE3_OVERFLOW_MPE BIT(4) /* multicast mac vlan overflow */
854 #define HNAE3_UPE (HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE)
855 #define HNAE3_MPE (HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE)
856
857 enum hnae3_pflag {
858 HNAE3_PFLAG_LIMIT_PROMISC,
859 HNAE3_PFLAG_MAX
860 };
861
862 struct hnae3_handle {
863 struct hnae3_client *client;
864 struct pci_dev *pdev;
865 void *priv;
866 struct hnae3_ae_algo *ae_algo; /* the class who provides this handle */
867 u64 flags; /* Indicate the capabilities for this handle */
868
869 union {
870 struct net_device *netdev; /* first member */
871 struct hnae3_knic_private_info kinfo;
872 struct hnae3_roce_private_info rinfo;
873 };
874
875 u32 numa_node_mask; /* for multi-chip support */
876
877 enum hnae3_port_base_vlan_state port_base_vlan_state;
878
879 u8 netdev_flags;
880 struct dentry *hnae3_dbgfs;
881 /* protects concurrent contention between debugfs commands */
882 struct mutex dbgfs_lock;
883 char **dbgfs_buf;
884
885 /* Network interface message level enabled bits */
886 u32 msg_enable;
887
888 unsigned long supported_pflags;
889 unsigned long priv_flags;
890 };
891
892 #define hnae3_set_field(origin, mask, shift, val) \
893 do { \
894 (origin) &= (~(mask)); \
895 (origin) |= ((val) << (shift)) & (mask); \
896 } while (0)
897 #define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift))
898
899 #define hnae3_set_bit(origin, shift, val) \
900 hnae3_set_field(origin, 0x1 << (shift), shift, val)
901 #define hnae3_get_bit(origin, shift) \
902 hnae3_get_field(origin, 0x1 << (shift), shift)
903
904 #define HNAE3_FORMAT_MAC_ADDR_LEN 18
905 #define HNAE3_FORMAT_MAC_ADDR_OFFSET_0 0
906 #define HNAE3_FORMAT_MAC_ADDR_OFFSET_4 4
907 #define HNAE3_FORMAT_MAC_ADDR_OFFSET_5 5
908
hnae3_format_mac_addr(char * format_mac_addr,const u8 * mac_addr)909 static inline void hnae3_format_mac_addr(char *format_mac_addr,
910 const u8 *mac_addr)
911 {
912 snprintf(format_mac_addr, HNAE3_FORMAT_MAC_ADDR_LEN, "%02x:**:**:**:%02x:%02x",
913 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_0],
914 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_4],
915 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_5]);
916 }
917
918 int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev);
919 void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev);
920
921 void hnae3_unregister_ae_algo_prepare(struct hnae3_ae_algo *ae_algo);
922 void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo);
923 void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo);
924
925 void hnae3_unregister_client(struct hnae3_client *client);
926 int hnae3_register_client(struct hnae3_client *client);
927
928 void hnae3_set_client_init_flag(struct hnae3_client *client,
929 struct hnae3_ae_dev *ae_dev,
930 unsigned int inited);
931 #endif
932