1 #ifndef __ASM_ARM_ARM64_SYSREGS_H 2 #define __ASM_ARM_ARM64_SYSREGS_H 3 4 #include <xen/stringify.h> 5 6 /* AArch 64 System Register Encodings */ 7 #define __HSR_SYSREG_c0 0 8 #define __HSR_SYSREG_c1 1 9 #define __HSR_SYSREG_c2 2 10 #define __HSR_SYSREG_c3 3 11 #define __HSR_SYSREG_c4 4 12 #define __HSR_SYSREG_c5 5 13 #define __HSR_SYSREG_c6 6 14 #define __HSR_SYSREG_c7 7 15 #define __HSR_SYSREG_c8 8 16 #define __HSR_SYSREG_c9 9 17 #define __HSR_SYSREG_c10 10 18 #define __HSR_SYSREG_c11 11 19 #define __HSR_SYSREG_c12 12 20 #define __HSR_SYSREG_c13 13 21 #define __HSR_SYSREG_c14 14 22 #define __HSR_SYSREG_c15 15 23 24 #define __HSR_SYSREG_0 0 25 #define __HSR_SYSREG_1 1 26 #define __HSR_SYSREG_2 2 27 #define __HSR_SYSREG_3 3 28 #define __HSR_SYSREG_4 4 29 #define __HSR_SYSREG_5 5 30 #define __HSR_SYSREG_6 6 31 #define __HSR_SYSREG_7 7 32 33 /* These are used to decode traps with HSR.EC==HSR_EC_SYSREG */ 34 #define HSR_SYSREG(op0,op1,crn,crm,op2) \ 35 ((__HSR_SYSREG_##op0) << HSR_SYSREG_OP0_SHIFT) | \ 36 ((__HSR_SYSREG_##op1) << HSR_SYSREG_OP1_SHIFT) | \ 37 ((__HSR_SYSREG_##crn) << HSR_SYSREG_CRN_SHIFT) | \ 38 ((__HSR_SYSREG_##crm) << HSR_SYSREG_CRM_SHIFT) | \ 39 ((__HSR_SYSREG_##op2) << HSR_SYSREG_OP2_SHIFT) 40 41 #define HSR_SYSREG_DCISW HSR_SYSREG(1,0,c7,c6,2) 42 #define HSR_SYSREG_DCCSW HSR_SYSREG(1,0,c7,c10,2) 43 #define HSR_SYSREG_DCCISW HSR_SYSREG(1,0,c7,c14,2) 44 45 #define HSR_SYSREG_MDSCR_EL1 HSR_SYSREG(2,0,c0,c2,2) 46 #define HSR_SYSREG_MDRAR_EL1 HSR_SYSREG(2,0,c1,c0,0) 47 #define HSR_SYSREG_OSLAR_EL1 HSR_SYSREG(2,0,c1,c0,4) 48 #define HSR_SYSREG_OSLSR_EL1 HSR_SYSREG(2,0,c1,c1,4) 49 #define HSR_SYSREG_OSDLR_EL1 HSR_SYSREG(2,0,c1,c3,4) 50 #define HSR_SYSREG_DBGPRCR_EL1 HSR_SYSREG(2,0,c1,c4,4) 51 #define HSR_SYSREG_MDCCSR_EL0 HSR_SYSREG(2,3,c0,c1,0) 52 53 #define HSR_SYSREG_DBGBVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,4) 54 #define HSR_SYSREG_DBGBCRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,5) 55 #define HSR_SYSREG_DBGWVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,6) 56 #define HSR_SYSREG_DBGWCRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,7) 57 58 #define HSR_SYSREG_DBG_CASES(REG) case HSR_SYSREG_##REG##n_EL1(0): \ 59 case HSR_SYSREG_##REG##n_EL1(1): \ 60 case HSR_SYSREG_##REG##n_EL1(2): \ 61 case HSR_SYSREG_##REG##n_EL1(3): \ 62 case HSR_SYSREG_##REG##n_EL1(4): \ 63 case HSR_SYSREG_##REG##n_EL1(5): \ 64 case HSR_SYSREG_##REG##n_EL1(6): \ 65 case HSR_SYSREG_##REG##n_EL1(7): \ 66 case HSR_SYSREG_##REG##n_EL1(8): \ 67 case HSR_SYSREG_##REG##n_EL1(9): \ 68 case HSR_SYSREG_##REG##n_EL1(10): \ 69 case HSR_SYSREG_##REG##n_EL1(11): \ 70 case HSR_SYSREG_##REG##n_EL1(12): \ 71 case HSR_SYSREG_##REG##n_EL1(13): \ 72 case HSR_SYSREG_##REG##n_EL1(14): \ 73 case HSR_SYSREG_##REG##n_EL1(15) 74 75 #define HSR_SYSREG_SCTLR_EL1 HSR_SYSREG(3,0,c1, c0,0) 76 #define HSR_SYSREG_ACTLR_EL1 HSR_SYSREG(3,0,c1, c0,1) 77 #define HSR_SYSREG_TTBR0_EL1 HSR_SYSREG(3,0,c2, c0,0) 78 #define HSR_SYSREG_TTBR1_EL1 HSR_SYSREG(3,0,c2, c0,1) 79 #define HSR_SYSREG_TCR_EL1 HSR_SYSREG(3,0,c2, c0,2) 80 #define HSR_SYSREG_AFSR0_EL1 HSR_SYSREG(3,0,c5, c1,0) 81 #define HSR_SYSREG_AFSR1_EL1 HSR_SYSREG(3,0,c5, c1,1) 82 #define HSR_SYSREG_ESR_EL1 HSR_SYSREG(3,0,c5, c2,0) 83 #define HSR_SYSREG_FAR_EL1 HSR_SYSREG(3,0,c6, c0,0) 84 #define HSR_SYSREG_PMINTENSET_EL1 HSR_SYSREG(3,0,c9,c14,1) 85 #define HSR_SYSREG_PMINTENCLR_EL1 HSR_SYSREG(3,0,c9,c14,2) 86 #define HSR_SYSREG_MAIR_EL1 HSR_SYSREG(3,0,c10,c2,0) 87 #define HSR_SYSREG_AMAIR_EL1 HSR_SYSREG(3,0,c10,c3,0) 88 #define HSR_SYSREG_ICC_SGI1R_EL1 HSR_SYSREG(3,0,c12,c11,5) 89 #define HSR_SYSREG_ICC_ASGI1R_EL1 HSR_SYSREG(3,1,c12,c11,6) 90 #define HSR_SYSREG_ICC_SGI0R_EL1 HSR_SYSREG(3,2,c12,c11,7) 91 #define HSR_SYSREG_ICC_SRE_EL1 HSR_SYSREG(3,0,c12,c12,5) 92 #define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1) 93 94 #define HSR_SYSREG_PMCR_EL0 HSR_SYSREG(3,3,c9,c12,0) 95 #define HSR_SYSREG_PMCNTENSET_EL0 HSR_SYSREG(3,3,c9,c12,1) 96 #define HSR_SYSREG_PMCNTENCLR_EL0 HSR_SYSREG(3,3,c9,c12,2) 97 #define HSR_SYSREG_PMOVSCLR_EL0 HSR_SYSREG(3,3,c9,c12,3) 98 #define HSR_SYSREG_PMSWINC_EL0 HSR_SYSREG(3,3,c9,c12,4) 99 #define HSR_SYSREG_PMSELR_EL0 HSR_SYSREG(3,3,c9,c12,5) 100 #define HSR_SYSREG_PMCEID0_EL0 HSR_SYSREG(3,3,c9,c12,6) 101 #define HSR_SYSREG_PMCEID1_EL0 HSR_SYSREG(3,3,c9,c12,7) 102 103 #define HSR_SYSREG_PMCCNTR_EL0 HSR_SYSREG(3,3,c9,c13,0) 104 #define HSR_SYSREG_PMXEVTYPER_EL0 HSR_SYSREG(3,3,c9,c13,1) 105 #define HSR_SYSREG_PMXEVCNTR_EL0 HSR_SYSREG(3,3,c9,c13,2) 106 107 #define HSR_SYSREG_PMUSERENR_EL0 HSR_SYSREG(3,3,c9,c14,0) 108 #define HSR_SYSREG_PMOVSSET_EL0 HSR_SYSREG(3,3,c9,c14,3) 109 110 #define HSR_SYSREG_CNTPCT_EL0 HSR_SYSREG(3,3,c14,c0,0) 111 #define HSR_SYSREG_CNTP_TVAL_EL0 HSR_SYSREG(3,3,c14,c2,0) 112 #define HSR_SYSREG_CNTP_CTL_EL0 HSR_SYSREG(3,3,c14,c2,1) 113 #define HSR_SYSREG_CNTP_CVAL_EL0 HSR_SYSREG(3,3,c14,c2,2) 114 115 /* 116 * GIC System register assembly aliases picked from kernel 117 */ 118 #define ICC_PMR_EL1 S3_0_C4_C6_0 119 #define ICC_DIR_EL1 S3_0_C12_C11_1 120 #define ICC_SGI1R_EL1 S3_0_C12_C11_5 121 #define ICC_EOIR1_EL1 S3_0_C12_C12_1 122 #define ICC_IAR1_EL1 S3_0_C12_C12_0 123 #define ICC_BPR1_EL1 S3_0_C12_C12_3 124 #define ICC_CTLR_EL1 S3_0_C12_C12_4 125 #define ICC_SRE_EL1 S3_0_C12_C12_5 126 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 127 128 #define ICH_VSEIR_EL2 S3_4_C12_C9_4 129 #define ICC_SRE_EL2 S3_4_C12_C9_5 130 #define ICH_HCR_EL2 S3_4_C12_C11_0 131 #define ICH_VTR_EL2 S3_4_C12_C11_1 132 #define ICH_MISR_EL2 S3_4_C12_C11_2 133 #define ICH_EISR_EL2 S3_4_C12_C11_3 134 #define ICH_ELSR_EL2 S3_4_C12_C11_5 135 #define ICH_VMCR_EL2 S3_4_C12_C11_7 136 137 #define __LR0_EL2(x) S3_4_C12_C12_ ## x 138 #define __LR8_EL2(x) S3_4_C12_C13_ ## x 139 140 #define ICH_LR0_EL2 __LR0_EL2(0) 141 #define ICH_LR1_EL2 __LR0_EL2(1) 142 #define ICH_LR2_EL2 __LR0_EL2(2) 143 #define ICH_LR3_EL2 __LR0_EL2(3) 144 #define ICH_LR4_EL2 __LR0_EL2(4) 145 #define ICH_LR5_EL2 __LR0_EL2(5) 146 #define ICH_LR6_EL2 __LR0_EL2(6) 147 #define ICH_LR7_EL2 __LR0_EL2(7) 148 #define ICH_LR8_EL2 __LR8_EL2(0) 149 #define ICH_LR9_EL2 __LR8_EL2(1) 150 #define ICH_LR10_EL2 __LR8_EL2(2) 151 #define ICH_LR11_EL2 __LR8_EL2(3) 152 #define ICH_LR12_EL2 __LR8_EL2(4) 153 #define ICH_LR13_EL2 __LR8_EL2(5) 154 #define ICH_LR14_EL2 __LR8_EL2(6) 155 #define ICH_LR15_EL2 __LR8_EL2(7) 156 157 #define __AP0Rx_EL2(x) S3_4_C12_C8_ ## x 158 #define ICH_AP0R0_EL2 __AP0Rx_EL2(0) 159 #define ICH_AP0R1_EL2 __AP0Rx_EL2(1) 160 #define ICH_AP0R2_EL2 __AP0Rx_EL2(2) 161 #define ICH_AP0R3_EL2 __AP0Rx_EL2(3) 162 163 #define __AP1Rx_EL2(x) S3_4_C12_C9_ ## x 164 #define ICH_AP1R0_EL2 __AP1Rx_EL2(0) 165 #define ICH_AP1R1_EL2 __AP1Rx_EL2(1) 166 #define ICH_AP1R2_EL2 __AP1Rx_EL2(2) 167 #define ICH_AP1R3_EL2 __AP1Rx_EL2(3) 168 169 #endif /* _ASM_ARM_ARM64_SYSREGS_H */ 170 171 /* 172 * Local variables: 173 * mode: C 174 * c-file-style: "BSD" 175 * c-basic-offset: 4 176 * indent-tabs-mode: nil 177 * End: 178 */ 179