1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2021 NXP 4 * I2C driver for I2C Controller 5 */ 6 7 #ifndef __DRIVERS_LS_I2C_H 8 #define __DRIVERS_LS_I2C_H 9 10 #include <io.h> 11 #include <stdint.h> 12 #include <tee_api_types.h> 13 14 /* 15 * Module Disable 16 * 0b - The module is enabled. You must clear this field before any other IBCR 17 * fields have any effect. 18 * 1b - The module is reset and disabled. This is the power-on reset situation. 19 * When high, the interface is held in reset, but registers can still be 20 * accessed. Status register fields (IBSR) are not valid when the module 21 * is disabled. 22 */ 23 #define I2C_IBCR_MDIS U(0x80) 24 25 /* I2c Bus Interrupt Enable */ 26 #define I2C_IBCR_IBIE U(0x40) 27 28 /* 29 * Master / Slave Mode 0b - Slave mode 1b - Master mode 30 * When you change this field from 0 to 1, the module generates a START signal 31 * on the bus and selects the master mode. When you change this field from 1 to 32 * 0, the module generates a STOP signal and changes the operation mode from 33 * master to slave. You should generate a STOP signal only if IBSR[IBIF]=1. 34 * The module clears this field without generating a STOP signal when the 35 * master loses arbitration. 36 */ 37 #define I2C_IBCR_MSSL U(0x20) 38 39 /* 0b - Receive 1b - Transmit */ 40 #define I2C_IBCR_TXRX U(0x10) 41 42 /* 43 * Data acknowledge disable 44 * Values written to this field are only used when the I2C module is a receiver, 45 * not a transmitter. 46 * 0b - The module sends an acknowledge signal to the bus at the 9th clock bit 47 * after receiving one byte of data. 48 * 1b - The module does not send an acknowledge-signal response (that is, 49 * acknowledge bit = 1). 50 */ 51 #define I2C_IBCR_NOACK U(0x08) 52 53 /* 54 * Repeat START 55 * If the I2C module is the current bus master, and you program RSTA=1, the I2C 56 * module generates a repeated START condition. This field always reads as a 0. 57 * If you attempt a repeated START at the wrong time, if the bus is owned by 58 * another master the result is loss of arbitration. 59 */ 60 #define I2C_IBCR_RSTA U(0x04) 61 62 /* DMA enable */ 63 #define I2C_IBCR_DMAEN U(0x02) 64 65 /* Transfer Complete */ 66 #define I2C_IBSR_TCF U(0x80) 67 68 /* I2C bus Busy. 0b - Bus is idle, 1b - Bus is busy */ 69 #define I2C_IBSR_IBB U(0x20) 70 71 /* Arbitration Lost. software must clear this field by writing a one to it. */ 72 #define I2C_IBSR_IBAL U(0x10) 73 74 /* I2C bus interrupt flag */ 75 #define I2C_IBSR_IBIF U(0x02) 76 77 /* 78 * Received acknowledge 79 * 0b - Acknowledge received 80 * 1b - No acknowledge received 81 */ 82 #define I2C_IBSR_RXAK U(0x01) 83 84 /* Bus idle interrupt enable */ 85 #define I2C_IBIC_BIIE U(0x80) 86 87 /* Glitch filter enable */ 88 #define I2C_IBDBG_GLFLT_EN U(0x08) 89 90 #define I2C_FLAG_WRITE U(0x00000000) 91 #define I2C_FLAG_READ U(0x00000001) 92 93 #define I2C_BUS_TEST_BUSY true 94 #define I2C_BUS_TEST_IDLE !I2C_BUS_TEST_BUSY 95 #define I2C_BUS_TEST_RX_ACK true 96 #define I2C_BUS_NO_TEST_RX_ACK !I2C_BUS_TEST_RX_ACK 97 98 #define I2C_NUM_RETRIES U(500) 99 100 struct i2c_regs { 101 uint8_t ibad; /* I2c Bus Address Register */ 102 uint8_t ibfd; /* I2c Bus Frequency Divider Register */ 103 uint8_t ibcr; /* I2c Bus Control Register */ 104 uint8_t ibsr; /* I2c Bus Status Register */ 105 uint8_t ibdr; /* I2C Bus Data I/O Register */ 106 uint8_t ibic; /* I2C Bus Interrupt Config Register */ 107 uint8_t ibdbg; /* I2C Bus Debug Register */ 108 }; 109 110 /* 111 * sorted list of clock divisor, ibfd register value pairs 112 */ 113 struct i2c_clock_divisor_pair { 114 uint16_t divisor; 115 uint8_t ibfd; /* I2c Bus Frequency Divider Register value */ 116 }; 117 118 /* 119 * I2C device operation 120 * The i2c_operation describes a subset of an I2C transaction in which 121 * the I2C controller is either sending or receiving bytes from the bus. 122 * Some transactions will consist of a single operation while others will 123 * be two or more. 124 */ 125 struct i2c_operation { 126 /* Flags to qualify the I2C operation. */ 127 uint32_t flags; 128 129 /* 130 * Number of bytes to send to or receive from the I2C device.A ping 131 * is indicated by setting the length_in_bytes to zero. 132 */ 133 unsigned int length_in_bytes; 134 135 /* 136 * Pointer to a buffer containing the data to send or to receive from 137 * the I2C device. The Buffer must be at least length_in_bytes in size. 138 */ 139 uint8_t *buffer; 140 }; 141 142 /* 143 * Structure to initialize I2C controller. 144 */ 145 struct ls_i2c_data { 146 /* I2C Controller to initialize */ 147 uint8_t i2c_controller; 148 /* 149 * base will be filled by i2c_init() which will be used in 150 * subsequent calls for reading/writing data. 151 */ 152 vaddr_t base; 153 /* I2C bus clock frequency */ 154 uint64_t i2c_bus_clock; 155 /* I2C speed */ 156 uint64_t speed; 157 }; 158 159 /* 160 * Structure to fill for I2C read/write operation 161 */ 162 struct i2c_reg_request { 163 /* 164 * Number of operations to perform. 165 * This will depend on peripheral for which it is used. 166 */ 167 unsigned int operation_count; 168 /* Operation to perform */ 169 struct i2c_operation *operation; 170 }; 171 172 /* 173 * Initialize I2C Controller, based on data passed in 174 * i2c_data. 175 */ 176 TEE_Result i2c_init(struct ls_i2c_data *i2c_data); 177 178 /* 179 * Software reset of the entire I2C module. 180 * The module is reset and disabled. 181 * Status register fields (IBSR) are cleared. 182 * base Base Address of I2c controller's registers 183 */ 184 void i2c_reset(vaddr_t base); 185 186 /* 187 * Transfer data to/from I2c slave device 188 * base Base Address of I2c controller's registers 189 * slave_address Slave Address from which data is to be read 190 * i2c_operation Pointer to an i2c_operation structure 191 * operation_count Number of operations. 192 */ 193 TEE_Result i2c_bus_xfer(vaddr_t base, uint32_t slave_address, 194 struct i2c_operation *i2c_operation, 195 unsigned int operation_count); 196 197 #endif /* __DRIVERS_LS_I2C_H */ 198