1 /**
2 ******************************************************************************
3 * @file rtl8721d_i2c.c
4 * @author
5 * @version V1.0.0
6 * @date 2016-05-17
7 * @brief This file contains all the functions prototypes for the I2C firmware
8 * library, including the following functionalities of theIntel-Integrated
9 * Circuit (I2C) peripheral:
10 * - Initialization
11 * - I2C Speed Setting
12 * - I2C Slave Address Updating
13 * - Receive/Send Data Interface
14 * - I2C Peripheral Control (disable/enable)
15 * - I2C SleepMode Control
16 * - Output pin Configuration
17 * - Interrupts and flags management
18 *
19 * @verbatim
20 *
21 * ===================================================================
22 * How to use this driver
23 * ===================================================================
24 * 1. Enable peripheral clock using the follwoing functions(it is enabled by default)
25 * RCC_PeriphClockCmd(APBPeriph_I2Cx, APBPeriph_I2Cx_CLOCK, ENABLE); for I2C0
26 *
27 * 2. Configure the I2C pinmux.
28 * Pinmux_Config(Pin_Num, PINMUX_FUNCTION_I2C)
29 *
30 * 3. Call I2C_Init(I2Cx, I2C_InitStruct) to configure the i2c with the corresponding configuration
31 *
32 * 4. Enable the NVIC and the corresponding interrupt using the function
33 * I2C_INTConfig() and register the i2c irq handler if you need to use interrupt mode.
34 *
35 * 5. When using the DMA mode
36 * - GDMA related configurations(source address/destination address/block size etc.)
37 * - Enable the DMA using the I2C_DMAControl() function
38 *
39 * 6. Enable i2c module using I2C_Cmd(I2Cx, NewState)
40 *
41 * @Note: All other functions can be used separately to modify, if needed,
42 * a specific feature of the I2C.
43 *
44 * @endverbatim
45 *
46 ******************************************************************************
47 * @attention
48 *
49 * This module is a confidential and proprietary property of RealTek and
50 * possession or use of this module requires written permission of RealTek.
51 *
52 * Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
53 ******************************************************************************
54 */
55
56 #include "ameba_soc.h"
57
58 const I2C_DevTable I2C_DEV_TABLE[1] = {
59 {I2C0_DEV, GDMA_HANDSHAKE_INTERFACE_I2C0_TX, GDMA_HANDSHAKE_INTERFACE_I2C0_RX, I2C0_IRQ_LP},
60 };
61
62 u32 I2C_SLAVEWRITE_PATCH;
63 u32 IC_FS_SCL_HCNT_TRIM;
64 u32 IC_FS_SCL_LCNT_TRIM;
65
66 /**
67 * @brief Fills each I2C_InitStruct member with its default value.
68 * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
69 * @retval None
70 */
I2C_StructInit(I2C_InitTypeDef * I2C_InitStruct)71 void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
72 {
73 /* Load HAL initial data structure default value */
74 I2C_InitStruct->I2CMaster = I2C_MASTER_MODE;
75 I2C_InitStruct->I2CAddrMod = I2C_ADDR_7BIT;
76 I2C_InitStruct->I2CSpdMod = I2C_SS_MODE;
77 I2C_InitStruct->I2CClk = 100;
78 I2C_InitStruct->I2CIPClk = 10000000;
79 I2C_InitStruct->I2CAckAddr = 0x11;
80 I2C_InitStruct->I2CSdaHd = 2;
81 I2C_InitStruct->I2CSlvSetup = 0x3;
82 I2C_InitStruct->I2CRXTL = 0x00;
83 I2C_InitStruct->I2CTXTL = 0x10;
84 I2C_InitStruct->I2CMstReSTR = DISABLE;
85 I2C_InitStruct->I2CMstGC = DISABLE;
86 I2C_InitStruct->I2CMstStartB = DISABLE;
87 I2C_InitStruct->I2CSlvNoAck = DISABLE;
88 I2C_InitStruct->I2CFilter = 0x101;
89 I2C_InitStruct->I2CTxDMARqLv = 0x09;
90 I2C_InitStruct->I2CRxDMARqLv = 0x03;
91 I2C_InitStruct->I2CAckAddr1 = 0x12;
92 }
93
94 /**
95 * @brief Initializes the I2Cx peripheral according to the specified
96 * parameters in the I2C_InitStruct.
97 * @param I2Cx: where I2Cx can be I2C0_DEV .
98 * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that contains
99 * the configuration information for the specified I2C peripheral.
100 * @retval None
101 */
I2C_Init(I2C_TypeDef * I2Cx,I2C_InitTypeDef * I2C_InitStruct)102 void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef* I2C_InitStruct)
103 {
104 u8 Specical;
105
106 /* Check the parameters */
107 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
108 assert_param(IS_I2C_ADDR_MODE(I2C_InitStruct->I2CAddrMod));
109 assert_param(IS_I2C_SPEED_MODE(I2C_InitStruct->I2CSpdMod));
110
111 /* Disable the IC first */
112 I2Cx->IC_ENABLE &= ~BIT_CTRL_IC_ENABLE;
113
114 /* Master case*/
115 if (I2C_InitStruct->I2CMaster) {
116 /*RESTART MUST be set in these condition in Master mode.
117 But it might be NOT compatible in old slaves.*/
118 if ((I2C_InitStruct->I2CAddrMod == I2C_ADDR_10BIT) || (I2C_InitStruct->I2CSpdMod == I2C_HS_MODE) || (I2C_InitStruct->I2CMstStartB != 0))
119 I2C_InitStruct->I2CMstReSTR = ENABLE;
120
121 I2Cx->IC_CON = (BIT_CTRL_IC_CON_IC_SLAVE_DISABLE_1 |
122 BIT_CTRL_IC_CON_IC_SLAVE_DISABLE |
123 (I2C_InitStruct->I2CMstReSTR << 5) |
124 (I2C_InitStruct->I2CSpdMod << 1) |
125 (I2C_InitStruct->I2CMaster));
126
127 /* To set target addr.*/
128 Specical = 0;
129 if ((I2C_InitStruct->I2CMstGC != 0) || (I2C_InitStruct->I2CMstStartB != 0))
130 Specical = 1;
131
132 I2Cx->IC_TAR = ((I2C_InitStruct->I2CAddrMod << 12) |
133 (Specical << 11) |
134 (I2C_InitStruct->I2CMstStartB << 10) |
135 (I2C_InitStruct->I2CAckAddr & BIT_CTRL_IC_TAR));
136
137 /* To Set I2C clock*/
138 I2C_SetSpeed(I2Cx, I2C_InitStruct->I2CSpdMod, I2C_InitStruct->I2CClk, I2C_InitStruct->I2CIPClk);
139 } /*if (Master)*/
140 else {
141 I2Cx->IC_CON = ((I2C_InitStruct->I2CMaster << 7) |
142 (I2C_InitStruct->I2CMaster << 6) |
143 (I2C_InitStruct->I2CAddrMod << 3) |
144 (I2C_InitStruct->I2CSpdMod << 1) |
145 (I2C_InitStruct->I2CMaster));
146
147 /* To set slave0 addr. */
148 I2Cx->IC_SAR = (I2C_InitStruct->I2CAckAddr & BIT_CTRL_IC_SAR);
149 /* To set slave1 addr. */
150 I2Cx->IC_SAR1 = (I2C_InitStruct->I2CAckAddr1 & BIT_CTRL_IC_SAR1);
151 /* To set slave no ack */
152 I2Cx->IC_SLV_DATA_NACK_ONLY = I2C_InitStruct->I2CSlvNoAck;
153 /* Set ack general call. */
154 I2Cx->IC_ACK_GENERAL_CALL = (I2C_InitStruct->I2CSlvAckGC & BIT_CTRL_IC_ACK_GENERAL_CALL);
155 /* to set SDA setup time */
156 I2Cx->IC_SDA_SETUP = (I2C_InitStruct->I2CSlvSetup & BIT_CTRL_IC_SDA_SETUP);
157 }
158 /* To set SDA hold time */
159 I2Cx->IC_SDA_HOLD = (I2C_InitStruct->I2CSdaHd & BIT_CTRL_IC_SDA_HOLD);
160
161 /* To set TX_Empty Level */
162 I2Cx->IC_TX_TL = I2C_InitStruct->I2CTXTL;
163
164 /* To set RX_Full Level */
165 I2Cx->IC_RX_TL = I2C_InitStruct->I2CRXTL;
166
167 /* To set IC_FILTER */
168 I2Cx->IC_FILTER = I2C_InitStruct->I2CFilter;
169
170 /* To set TX/RX FIFO level */
171 I2Cx->IC_DMA_TDLR = I2C_InitStruct->I2CTxDMARqLv;
172 I2Cx->IC_DMA_RDLR = I2C_InitStruct->I2CRxDMARqLv;
173
174 /*I2C Clear all interrupts first*/
175 I2C_ClearAllINT(I2Cx);
176
177 /*I2C Disable all interrupts first*/
178 I2C_INTConfig(I2Cx, 0xFFFFFFFF, DISABLE);
179 }
180
181 /**
182 * @brief Master sets I2C Speed Mode.
183 * @param I2Cx: where I2Cx can be I2C0_DEV.
184 * @param SpdMd: I2C Speed Mode.
185 * This parameter can be one of the following values:
186 * @arg I2C_SS_MODE:
187 * @arg I2C_FS_MODE:
188 * @arg I2C_HS_MODE:(not support in amebaD )
189 * @param I2Clk: I2C Bus Clock, unit is KHz.
190 * This parameter can be one of the following values:
191 * @arg 50:
192 * @arg 100:
193 * @arg 400:
194 * @arg 1000:
195 * @arg 3000:
196 * @param IPClk: I2C IP Clock, unit is Hz.
197 * @retval None
198 */
I2C_SetSpeed(I2C_TypeDef * I2Cx,u32 SpdMd,u32 I2Clk,u32 I2CIPClk)199 void I2C_SetSpeed(I2C_TypeDef *I2Cx, u32 SpdMd, u32 I2Clk, u32 I2CIPClk)
200 {
201 u32 ICHLcnt;
202 u32 ICHtime;
203 u32 ICLtime;
204 u32 IPClkM = I2CIPClk /1000000;
205
206 /* Check the parameters */
207 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
208
209 switch (SpdMd)
210 {
211 case I2C_SS_MODE:
212 {
213 ICHtime = ((1000000/I2Clk)*I2C_SS_MIN_SCL_HTIME)/(I2C_SS_MIN_SCL_HTIME+I2C_SS_MIN_SCL_LTIME);
214 ICLtime = ((1000000/I2Clk)*I2C_SS_MIN_SCL_LTIME)/(I2C_SS_MIN_SCL_HTIME+I2C_SS_MIN_SCL_LTIME);
215
216 ICHLcnt = (ICHtime * IPClkM)/1000;
217 I2Cx->IC_SS_SCL_HCNT = ICHLcnt + 1;
218 ICHLcnt = (ICLtime * IPClkM)/1000;
219 I2Cx->IC_SS_SCL_LCNT = ICHLcnt;
220
221 break;
222 }
223
224 case I2C_FS_MODE:
225 {
226 ICHtime = ((1000000/I2Clk)*I2C_FS_MIN_SCL_HTIME)/(I2C_FS_MIN_SCL_HTIME+I2C_FS_MIN_SCL_LTIME);
227 ICLtime = ((1000000/I2Clk)*I2C_FS_MIN_SCL_LTIME)/(I2C_FS_MIN_SCL_HTIME+I2C_FS_MIN_SCL_LTIME);
228
229 ICHLcnt = (ICHtime * IPClkM)/1000;
230 if (ICHLcnt > IC_FS_SCL_HCNT_TRIM)/*this part is according to the fine-tune result*/
231 ICHLcnt -= IC_FS_SCL_HCNT_TRIM;
232 I2Cx->IC_FS_SCL_HCNT = ICHLcnt + 1;
233
234 ICHLcnt = (ICLtime * IPClkM)/1000;
235 if (ICHLcnt > IC_FS_SCL_LCNT_TRIM)/*this part is according to the fine-tune result*/
236 ICHLcnt -= IC_FS_SCL_LCNT_TRIM;
237 I2Cx->IC_FS_SCL_LCNT = ICHLcnt;
238
239 break;
240 }
241
242 case I2C_HS_MODE:
243 {
244 /*set Fast mode count for Master code*/
245 ICHtime = ((1000000/I2Clk)*I2C_FS_MIN_SCL_HTIME)/(I2C_FS_MIN_SCL_HTIME+I2C_FS_MIN_SCL_LTIME);
246 ICLtime = ((1000000/I2Clk)*I2C_FS_MIN_SCL_LTIME)/(I2C_FS_MIN_SCL_HTIME+I2C_FS_MIN_SCL_LTIME);
247
248 ICHLcnt = (ICHtime * IPClkM)/1000;
249 I2Cx->IC_FS_SCL_HCNT = ICHLcnt + 1;
250
251 ICHLcnt = (ICLtime * IPClkM)/1000;
252 I2Cx->IC_FS_SCL_LCNT = ICHLcnt;
253
254 ICHtime = ((1000000/I2Clk)*I2C_HS_MIN_SCL_HTIME_100)/(I2C_HS_MIN_SCL_HTIME_100+I2C_HS_MIN_SCL_LTIME_100);
255 ICLtime = ((1000000/I2Clk)*I2C_HS_MIN_SCL_LTIME_100)/(I2C_HS_MIN_SCL_HTIME_100+I2C_HS_MIN_SCL_LTIME_100);
256
257 ICHLcnt = (ICHtime * IPClkM)/1000;
258 //if (ICHLcnt>8)/*this part is according to the fine-tune result*/
259 // ICHLcnt -= 3;
260 I2Cx->IC_HS_SCL_HCNT = ICHLcnt;
261
262 ICHLcnt = (ICLtime * IPClkM)/1000;
263 //if (ICHLcnt>6)/*this part is according to the fine-tune result*/
264 // ICHLcnt -= 6;
265 I2Cx->IC_HS_SCL_LCNT = ICHLcnt;
266
267 break;
268 }
269
270 default:
271 break;
272 }
273 }
274
275 /**
276 * @brief Master transmits the address byte to select the slave device.
277 * @param I2Cx: where I2Cx can be I2C0_DEV.
278 * @param Address: specifies the slave address which will be transmitted
279 * @retval None.
280 */
I2C_SetSlaveAddress(I2C_TypeDef * I2Cx,u16 Address)281 void I2C_SetSlaveAddress(I2C_TypeDef *I2Cx, u16 Address)
282 {
283 u32 tar = I2Cx->IC_TAR & ~(BIT_CTRL_IC_TAR);
284
285 /* Check the parameters */
286 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
287
288 /*set target address to generate start signal*/
289 I2Cx->IC_TAR = (Address & BIT_CTRL_IC_TAR) | tar;
290 }
291
292 /**
293 * @brief Checks whether the specified I2C flag is set or not.
294 * @param I2Cx: where I2Cx can be I2C0_DEV .
295 * @param I2C_FLAG: specifies the flag to check.
296 * This parameter can be one of the following values:
297 * @arg BIT_IC_STATUS_BUS_BUSY:
298 * @arg I2C_FLAG_SLV_ACTIVITY:
299 * @arg I2C_FLAG_MST_ACTIVITY:
300 * @arg I2C_FLAG_RFF:
301 * @arg I2C_FLAG_RFNE:
302 * @arg I2C_FLAG_TFE:
303 * @arg I2C_FLAG_TFNF:
304 * @arg I2C_FLAG_ACTIVITY:
305 * @retval The new state of I2C_FLAG:
306 * - 1: the specified I2C flag is set
307 * - 0: the specified I2C flag is not set
308 */
I2C_CheckFlagState(I2C_TypeDef * I2Cx,u32 I2C_FLAG)309 u8 I2C_CheckFlagState(I2C_TypeDef *I2Cx, u32 I2C_FLAG)
310 {
311 u8 bit_status = 0;
312
313 /* Check the parameters */
314 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
315
316 if((I2Cx->IC_STATUS & I2C_FLAG) != 0)
317 {
318 /* I2C_FLAG is set */
319 bit_status = 1;
320 }
321
322 /* Return the I2C_FLAG status */
323 return bit_status;
324 }
325
326 /**
327 * @brief ENABLE/DISABLE the I2C's interrupt bits..
328 * @param I2Cx: where I2Cx can be I2C0_DEV .
329 * @param I2C_IT: specifies the I2Cx interrupt sources to be enabled or disabled.
330 * This parameter can be one or combinations of the following values:
331 * @arg BIT_IC_INTR_MASK_M_DMA_I2C_DONE: I2C DMA Done Interrupt
332 * @arg BIT_IC_INTR_MASK_M_ADDR_2_MATCH: I2C slave1 Address Match Interrupt
333 * @arg BIT_IC_INTR_MASK_M_ADDR_1_MATCH: I2C slave0 Address Match Interrupt
334 * @arg BIT_IC_INTR_MASK_M_GEN_CALL: General Call Interrupt
335 * @arg BIT_IC_INTR_MASK_M_START_DET: Start or Restart Condition Interrupt
336 * @arg BIT_IC_INTR_MASK_M_STOP_DET: Stop Condition Interrupt
337 * @arg BIT_IC_INTR_MASK_M_ACTIVITY: I2C Activity Interrupt
338 * @arg BIT_IC_INTR_MASK_M_RX_DONE: Slave Transmitter RX Done Interrupt
339 * @arg BIT_IC_INTR_MASK_M_TX_ABRT: Transmit Abort Interrupt
340 * @arg BIT_IC_INTR_MASK_M_RD_REQ: Read Request Interrupt
341 * @arg BIT_IC_INTR_MASK_M_TX_EMPTY: Transmit FIFO Empty Interrupt
342 * @arg BIT_IC_INTR_MASK_M_TX_OVER: Transmit FIFO Over Interrupt
343 * @arg BIT_IC_INTR_MASK_M_RX_FULL: Receive FIFO Full Interrupt
344 * @arg BIT_IC_INTR_MASK_M_RX_OVER: Receive FIFO Over Interrupt
345 * @arg BIT_IC_INTR_MASK_M_RX_UNDER: Receive FIFO Under Interrupt
346 * @param NewState: specifies the state of the interrupt.
347 * This parameter can be: ENABLE or DISABLE.
348 * @retval None
349 */
I2C_INTConfig(I2C_TypeDef * I2Cx,u32 I2C_IT,u32 NewState)350 void I2C_INTConfig(I2C_TypeDef *I2Cx, u32 I2C_IT, u32 NewState)
351 {
352 u32 TempVal = I2Cx->IC_INTR_MASK;
353
354 /* Check the parameters */
355 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
356
357 if (NewState == ENABLE) {
358 TempVal |= I2C_IT;
359 } else {
360 TempVal &= ~I2C_IT;
361 }
362
363 I2Cx->IC_INTR_MASK = TempVal;
364 }
365
366 /**
367 * @brief Clears the specified I2C interrupt pending bit.
368 * @param I2Cx: where I2Cx can be I2C0_DEV.
369 * @param INTrBit: specifies the interrupt to be cleared.
370 * This parameter can be one of the following values:
371 * @arg BIT_IC_INTR_STAT_R_ADDR_2_MATCH: I2C slave1 Address Match Interrupt
372 * @arg BIT_IC_INTR_STAT_R_ADDR_1_MATCH: I2C slave0 Address Match Interrupt
373 * @arg BIT_IC_INTR_STAT_R_GEN_CALL: General Call Interrupt
374 * @arg BIT_IC_INTR_STAT_R_START_DET: Start or Restart Condition Interrupt
375 * @arg BIT_IC_INTR_STAT_R_STOP_DET: Stop Condition Interrupt
376 * @arg BIT_IC_INTR_STAT_R_ACTIVITY: I2C Activity Interrupt
377 * @arg BIT_IC_INTR_STAT_R_RX_DONE: Slave Transmitter RX Done Interrupt
378 * @arg BIT_IC_INTR_STAT_R_TX_ABRT: Transmit Abort Interrupt
379 * @arg BIT_IC_INTR_STAT_R_RD_REQ: Read Request Interrupt
380 * @arg BIT_IC_INTR_STAT_R_TX_EMPTY: Transmit FIFO Empty Interrupt
381 * @arg BIT_IC_INTR_STAT_R_TX_OVER: Transmit FIFO Over Interrupt
382 * @arg BIT_IC_INTR_STAT_R_RX_FULL: Receive FIFO Full Interrupt
383 * @arg BIT_IC_INTR_STAT_R_RX_OVER: Receive FIFO Over Interrupt
384 * @arg BIT_IC_INTR_STAT_R_RX_UNDER: Receive FIFO Under Interrupt
385 * @note BIT_IC_INTR_STAT_R_TX_EMPTY is automatically cleared by hardware when the buffer
386 * level goes above the I2CTXTL threshold.
387 * BIT_IC_INTR_STAT_R_RX_FULL is automatically cleared by hardware when the buffer
388 * level goes below the I2CRXTL threshold.
389 * @retval None
390 */
I2C_ClearINT(I2C_TypeDef * I2Cx,u32 INTrBit)391 void I2C_ClearINT(I2C_TypeDef *I2Cx, u32 INTrBit)
392 {
393 /* Check the parameters */
394 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
395
396 switch (INTrBit) {
397 case BIT_IC_INTR_STAT_R_ADDR_2_MATCH:
398 I2Cx->IC_CLR_ADDR_MATCH;
399 break;
400 case BIT_IC_INTR_STAT_R_ADDR_1_MATCH:
401 I2Cx->IC_CLR_ADDR_MATCH;
402 break;
403 case BIT_IC_INTR_STAT_R_GEN_CALL:
404 I2Cx->IC_CLR_GEN_CALL;
405 break;
406 case BIT_IC_INTR_STAT_R_START_DET:
407 I2Cx->IC_CLR_START_DET;
408 break;
409 case BIT_IC_INTR_STAT_R_STOP_DET:
410 I2Cx->IC_CLR_STOP_DET;
411 break;
412 case BIT_IC_INTR_STAT_R_ACTIVITY:
413 I2Cx->IC_CLR_ACTIVITY;
414 break;
415 case BIT_IC_INTR_STAT_R_RX_DONE:
416 I2Cx->IC_CLR_RX_DONE;
417 break;
418 case BIT_IC_INTR_STAT_R_TX_ABRT:
419 I2Cx->IC_CLR_TX_ABRT;
420 break;
421 case BIT_IC_INTR_STAT_R_RD_REQ:
422 I2Cx->IC_CLR_RD_REQ;
423 break;
424 case BIT_IC_INTR_STAT_R_TX_OVER:
425 I2Cx->IC_CLR_TX_OVER;
426 break;
427 case BIT_IC_INTR_STAT_R_RX_OVER:
428 I2Cx->IC_CLR_RX_OVER;
429 break;
430 case BIT_IC_INTR_STAT_R_RX_UNDER:
431 I2Cx->IC_CLR_RX_UNDER;
432 break;
433 case BIT_IC_INTR_STAT_R_TX_EMPTY:
434 case BIT_IC_INTR_STAT_R_RX_FULL:
435 default:
436 break;
437 }
438 }
439
440 /**
441 * @brief Clears all of the I2C interrupt pending bit.
442 * @param I2Cx: where I2Cx can be I2C0_DEV .
443 * @retval None
444 */
I2C_ClearAllINT(I2C_TypeDef * I2Cx)445 void I2C_ClearAllINT(I2C_TypeDef *I2Cx)
446 {
447 /* Check the parameters */
448 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
449
450 I2Cx->IC_CLR_INTR;
451 }
452
453 /**
454 * @brief Get I2C Raw Interrupt Status.
455 * @param I2Cx: where I2Cx can be I2C0_DEV .
456 * @retval raw interrupt status
457 */
I2C_GetRawINT(I2C_TypeDef * I2Cx)458 u32 I2C_GetRawINT(I2C_TypeDef *I2Cx)
459 {
460 /* Check the parameters */
461 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
462
463 return I2Cx->IC_RAW_INTR_STAT;
464 }
465
466 /**
467 * @brief Get I2C interrupt status.
468 * @param I2Cx: where I2Cx can be I2C0_DEV .
469 * @retval interrupt status
470 */
I2C_GetINT(I2C_TypeDef * I2Cx)471 u32 I2C_GetINT(I2C_TypeDef *I2Cx)
472 {
473 /* Check the parameters */
474 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
475
476 return I2Cx->IC_INTR_STAT;
477 }
478
479 /**
480 * @brief Master sends single byte through the I2Cx peripheral according to the set of the upper layer.
481 * @param I2Cx: where I2Cx can be I2C0_DEV .
482 * @param pBuf: point to the data that to be write.
483 * @param I2CCmd: specifies whether a read from FIFO or a write to FIFO is performed.
484 * @param I2CStop: specifies whether a STOP is issued after the byte is sent or received.
485 * @param I2CReSTR: specifies whether a RESTART is issued after the byte is sent or received.
486 * @retval None
487 */
I2C_MasterSendNullData(I2C_TypeDef * I2Cx,u8 * pBuf,u8 I2CCmd,u8 I2CStop,u8 I2CReSTR)488 void I2C_MasterSendNullData(I2C_TypeDef *I2Cx, u8* pBuf, u8 I2CCmd, u8 I2CStop, u8 I2CReSTR)
489 {
490 /* Check the parameters */
491 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
492
493 I2Cx->IC_DATA_CMD = *(pBuf) |
494 (1 << 11) |
495 (I2CReSTR << 10) |
496 (I2CCmd << 8) |
497 (I2CStop << 9);
498 }
499
500 /**
501 * @brief Master sends single byte through the I2Cx peripheral according to the set of the upper layer.
502 * @param I2Cx: where I2Cx can be I2C0_DEV .
503 * @param pBuf: point to the data that to be write.
504 * @param I2CCmd: specifies whether a read from FIFO or a write to FIFO is performed.
505 * @param I2CStop: specifies whether a STOP is issued after the byte is sent or received.
506 * @param I2CReSTR: specifies whether a RESTART is issued after the byte is sent or received.
507 * @retval None
508 */
I2C_MasterSend(I2C_TypeDef * I2Cx,u8 * pBuf,u8 I2CCmd,u8 I2CStop,u8 I2CReSTR)509 void I2C_MasterSend(I2C_TypeDef *I2Cx, u8* pBuf, u8 I2CCmd, u8 I2CStop, u8 I2CReSTR)
510 {
511 /* Check the parameters */
512 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
513
514 I2Cx->IC_DATA_CMD = *(pBuf) |
515 (I2CReSTR << 10) |
516 (I2CCmd << 8) |
517 (I2CStop << 9);
518 }
519
520 /**
521 * @brief Slave sends single byte through the I2Cx peripheral after receiving read request of Master.
522 * @param I2Cx: where I2Cx can be I2C0_DEV.
523 * @param Data: data to be transmitted.
524 * @param StopState: specifies whether a STOP is issued after the byte is sent.
525 * @retval None
526 */
I2C_SlaveSend(I2C_TypeDef * I2Cx,u8 Data)527 void I2C_SlaveSend(I2C_TypeDef *I2Cx, u8 Data)
528 {
529 /* Check the parameters */
530 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
531
532 I2Cx->IC_DATA_CMD = Data;
533 }
534
535 /**
536 * @brief Returns the most recent received data by the I2Cx peripheral.
537 * @param I2Cx: where I2Cx can be I2C0_DEV .
538 * @retval The value of the received data.
539 */
I2C_ReceiveData(I2C_TypeDef * I2Cx)540 u8 I2C_ReceiveData(I2C_TypeDef *I2Cx)
541 {
542 /* Check the parameters */
543 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
544
545 /* Return the data in the DR register */
546 return (u8)I2Cx->IC_DATA_CMD;
547 }
548
549 /**
550 * @brief Send data with special length in master mode through the I2Cx peripheral.
551 * @param I2Cx: where I2Cx can be I2C0_DEV.
552 * @param pBuf: point to the data to be transmitted.
553 * @param len: the length of data that to be transmitted.
554 * @retval None
555 */
I2C_MasterWrite(I2C_TypeDef * I2Cx,u8 * pBuf,u8 len)556 void I2C_MasterWrite(I2C_TypeDef *I2Cx, u8* pBuf, u8 len)
557 {
558 u8 cnt = 0;
559
560 /* Check the parameters */
561 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
562
563 /* Write in the DR register the data to be sent */
564 for(cnt = 0; cnt < len; cnt++)
565 {
566 while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_TFNF)) == 0);
567
568 if(cnt >= len - 1)
569 {
570 /*generate stop signal*/
571 I2Cx->IC_DATA_CMD = (*pBuf++) | (1 << 9);
572 }
573 else
574 {
575 I2Cx->IC_DATA_CMD = (*pBuf++);
576 }
577 }
578
579 while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_TFE)) == 0);
580 }
581
582 /**
583 * @brief Send data with special length in master mode through the I2Cx peripheral.
584 * @param I2Cx: where I2Cx can be I2C0_DEV .
585 * @param pBuf: point to the data to be transmitted.
586 * @param len: the length of data that to be transmitted.
587 * @retval: The length of data that have been sent to tx fifo
588 */
I2C_MasterWriteBrk(I2C_TypeDef * I2Cx,u8 * pBuf,u8 len)589 u8 I2C_MasterWriteBrk(I2C_TypeDef *I2Cx, u8* pBuf, u8 len)
590 {
591 u8 cnt = 0;
592
593 /* Check the parameters */
594 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
595
596 /* Write in the DR register the data to be sent */
597 for(cnt = 0; cnt < len; cnt++)
598 {
599 while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_TFNF)) == 0);
600
601 if(cnt >= len - 1)
602 {
603 /*generate stop signal*/
604 I2Cx->IC_DATA_CMD = (*pBuf++) | (1 << 9);
605 }
606 else
607 {
608 I2Cx->IC_DATA_CMD = (*pBuf++);
609 }
610
611 while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_TFE)) == 0) {
612 if(I2C_GetRawINT(I2Cx) & BIT_IC_RAW_INTR_STAT_TX_ABRT) {
613 I2C_ClearAllINT(I2Cx);
614 return cnt;
615 }
616 }
617 }
618
619 return cnt;
620 }
621
622 /**
623 * @brief Read data with special length in master mode through the I2Cx peripheral under DW IP.
624 * @note Under DW IP, master must send two times read cmd:
625 * flow is:
626 * step 1: master request first data entry
627 * step 2: slave send first data entry
628 * step 3: master send seconed read cmd to ack first data and request second data
629 * step 4: slave send second data
630 * step 5: master rx full interrupt receive fisrt data and ack second data and request third data.
631 * loop step 4 and step 5.
632 * so last slave data have no ack, this is permitted by the spec.
633 * @param I2Cx: where I2Cx can be I2C0_DEV .
634 * @param pBuf: point to the buffer to hold the received data.
635 * @param len: the length of data that to be received.
636 * @retval None
637 */
I2C_MasterReadDW(I2C_TypeDef * I2Cx,u8 * pBuf,u8 len)638 void I2C_MasterReadDW(I2C_TypeDef *I2Cx, u8* pBuf, u8 len)
639 {
640 u8 cnt = 0;
641
642 /* Check the parameters */
643 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
644
645 /* read in the DR register the data to be received */
646 for(cnt = 0; cnt < len; cnt++)
647 {
648 if(cnt >= len - 1)
649 {
650 /* generate stop singal */
651 I2Cx->IC_DATA_CMD = 0x0003 << 8;
652 }
653 else
654 {
655 I2Cx->IC_DATA_CMD = 0x0001 << 8;
656 }
657
658 /* read data */
659 if(cnt > 0)
660 {
661 /* wait for I2C_FLAG_RFNE flag */
662 while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_RFNE)) == 0);
663 *pBuf++ = (u8)I2Cx->IC_DATA_CMD;
664 }
665 }
666
667 /* recv last data and NACK */
668 while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_RFNE)) == 0);
669 *pBuf++ = (u8)I2Cx->IC_DATA_CMD;
670 }
671
672 /**
673 * @brief Read data with special length in master mode through the I2Cx peripheral under in-house IP.
674 * @param I2Cx: where I2Cx can be I2C0_DEV .
675 * @param pBuf: point to the buffer to hold the received data.
676 * @param len: the length of data that to be received.
677 * @retval The length of data that have received from rx fifo.
678 */
I2C_MasterRead(I2C_TypeDef * I2Cx,u8 * pBuf,u8 len)679 u8 I2C_MasterRead(I2C_TypeDef *I2Cx, u8* pBuf, u8 len)
680 {
681 u8 cnt = 0;
682
683 /* Check the parameters */
684 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
685
686 /* read in the DR register the data to be received */
687 for(cnt = 0; cnt < len; cnt++)
688 {
689 if(cnt >= len - 1)
690 {
691 /* generate stop singal */
692 I2Cx->IC_DATA_CMD = 0x0003 << 8;
693 }
694 else
695 {
696 I2Cx->IC_DATA_CMD = 0x0001 << 8;
697 }
698
699 /* wait for I2C_FLAG_RFNE flag */
700 while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_RFNE)) == 0) {
701 if(I2C_GetRawINT(I2Cx) & BIT_IC_RAW_INTR_STAT_TX_ABRT) {
702 I2C_ClearAllINT(I2Cx);
703 return cnt;
704 }
705 }
706 *pBuf++ = (u8)I2Cx->IC_DATA_CMD;
707 }
708
709 return cnt;
710 }
711
712 /**
713 * @brief Send data with special length in slave mode through the I2Cx peripheral.
714 * @param I2Cx: where I2Cx can be I2C0_DEV.
715 * @param pBuf: point to the data to be transmitted.
716 * @param len: the length of data that to be transmitted.
717 * @retval None
718 */
I2C_SlaveWrite(I2C_TypeDef * I2Cx,u8 * pBuf,u8 len)719 void I2C_SlaveWrite(I2C_TypeDef *I2Cx, u8* pBuf, u8 len)
720 {
721 u8 cnt = 0;
722
723 /* Check the parameters */
724 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
725
726 for(cnt = 0; cnt < len; cnt++) {
727 /* Check I2C RD Request flag */
728 while((I2Cx->IC_RAW_INTR_STAT & BIT_IC_RAW_INTR_STAT_RD_REQ) == 0);
729
730 if (I2C_SLAVEWRITE_PATCH) {
731 I2Cx->IC_CLR_RD_REQ;
732 }
733 /* Check I2C TX FIFO status */
734 while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_TFNF)) == 0);
735
736 I2Cx->IC_DATA_CMD = (*pBuf++);
737 }
738 while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_TFE)) == 0);
739 }
740
741 /**
742 * @brief Read data with special length in slave mode through the I2Cx peripheral.
743 * @param I2Cx: where I2Cx can be I2C0_DEV.
744 * @param pBuf: point to the buffer to hold the received data.
745 * @param len: the length of data that to be received.
746 * @retval None
747 */
I2C_SlaveRead(I2C_TypeDef * I2Cx,u8 * pBuf,u8 len)748 void I2C_SlaveRead(I2C_TypeDef *I2Cx, u8* pBuf, u8 len)
749 {
750 u8 cnt = 0;
751
752 /* Check the parameters */
753 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
754
755 for(cnt = 0; cnt < len; cnt++) {
756 /* Check I2C RX FIFO status */
757 while((I2C_CheckFlagState(I2Cx, (BIT_IC_STATUS_RFNE | BIT_IC_STATUS_RFF))) == 0);
758
759 *pBuf++ = (u8)I2Cx->IC_DATA_CMD;
760 }
761 }
762 /**
763 * @brief Sends data and read data in master mode through the I2Cx peripheral.
764 * @param I2Cx: where I2Cx can be I2C0_DEV.
765 * @param pWriteBuf: Byte to be transmitted.
766 * @param Writelen: Byte number to be transmitted.
767 * @param pReadBuf: Byte to be received.
768 * @param Readlen: Byte number to be received.
769 * @retval None
770 */
I2C_MasterRepeatRead(I2C_TypeDef * I2Cx,u8 * pWriteBuf,u8 Writelen,u8 * pReadBuf,u8 Readlen)771 void I2C_MasterRepeatRead(I2C_TypeDef* I2Cx, u8* pWriteBuf, u8 Writelen, u8* pReadBuf, u8 Readlen)
772 {
773
774 u8 cnt = 0;
775
776 /* Check the parameters */
777 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
778
779 /* write in the DR register the data to be sent */
780 for(cnt = 0; cnt < Writelen; cnt++)
781 {
782 while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_TFNF)) == 0);
783
784 if(cnt >= Writelen - 1)
785 {
786 /*generate restart signal*/
787 I2Cx->IC_DATA_CMD = (*pWriteBuf++) | (1 << 10);
788 }
789 else
790 {
791 I2Cx->IC_DATA_CMD = (*pWriteBuf++);
792 }
793 }
794
795 /*Wait I2C TX FIFO not full*/
796 while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_TFNF)) == 0);
797
798 I2C_MasterRead(I2Cx, pReadBuf, Readlen);
799 }
800
801 /**
802 * @brief Enables or disables the specified I2C peripheral, this is one bit register.
803 * @param I2Cx: where I2Cx can be I2C0_DEV .
804 * @param NewState: new state of the I2Cx peripheral.
805 * This parameter can be: ENABLE or DISABLE.
806 * @retval None
807 */
I2C_Cmd(I2C_TypeDef * I2Cx,u8 NewState)808 void I2C_Cmd(I2C_TypeDef *I2Cx, u8 NewState)
809 {
810 /* Check the parameters */
811 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
812
813 if (NewState != DISABLE)
814 {
815 /* Enable the selected I2C peripheral */
816 I2Cx->IC_ENABLE |= BIT_CTRL_IC_ENABLE;
817 }
818 else
819 {
820 /* Disable the selected I2C peripheral */
821 I2Cx->IC_ENABLE &= ~BIT_CTRL_IC_ENABLE;
822 }
823 }
824
825 /**
826 * @brief Enable I2C Tx or Rx DMA.
827 * @param I2Cx: where I2Cx can be I2C0_DEV.
828 * @param DmaCtrl: control Transmit DMA Enable or Receive DMA Enable
829 * This parameter can be one of the following values:
830 * @arg BIT_IC_DMA_CR_TDMAE:
831 * @arg BIT_IC_DMA_CR_RDMAE:
832 * @param NewState: the new state of the DMA function.
833 * This parameter can be: ENABLE or DISABLE.
834 * @retval None
835 */
I2C_DMAControl(I2C_TypeDef * I2Cx,u32 DmaCtrl,u8 NewState)836 void I2C_DMAControl(I2C_TypeDef *I2Cx, u32 DmaCtrl, u8 NewState)
837 {
838 u32 I2CDMAEn = I2Cx->IC_DMA_CR;
839
840 /* Check the parameters */
841 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
842
843 if (NewState == ENABLE)
844 I2CDMAEn |= DmaCtrl;
845 else
846 I2CDMAEn &= ~DmaCtrl;
847
848 I2Cx->IC_DMA_CR = I2CDMAEn;
849 }
850
851 /**
852 * @brief Initializes the I2Cx Control Register DMA mode.
853 * @param I2Cx: where I2Cx can be I2C0_DEV.
854 * @param I2C_DmaCmd: Command to control the read or write operation and
855 * the action after the last data transferred.
856 * This parameter can be one or combinations of the following values:
857 * @arg BIT_IC_DMA_CMD_RESTART
858 * @arg BIT_IC_DMA_CMD_STOP
859 * @arg BIT_IC_DMA_CMD_RW
860 * @arg BIT_IC_DMA_CMD_ENABLE
861 * @param I2C_DmaBLen: length of data.
862 * This parameter must be set to a value in the 0-0xFFFF range.
863 * @retval None
864 */
I2C_DmaMode1Config(I2C_TypeDef * I2Cx,u32 I2C_DmaCmd,u32 I2C_DmaBLen)865 void I2C_DmaMode1Config(I2C_TypeDef *I2Cx, u32 I2C_DmaCmd, u32 I2C_DmaBLen)
866 {
867 /* Check the parameters */
868 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
869 assert_param(IS_I2C_DMA_DATA_LEN(I2C_DmaBLen));
870
871 I2Cx->IC_DMA_MOD = I2C_DMA_REGISTER;
872 I2Cx->IC_DMA_DAT_LEN = I2C_DmaBLen;
873 I2Cx->IC_DMA_CMD = I2C_DmaCmd;
874 }
875
876 /**
877 * @brief Initializes the I2C Discripter DMA mode.
878 * @param I2Cx: where I2Cx can be I2C0_DEV .
879 * @param I2C_DmaCmd: set BIT[0] of IC_DMA_CMD to enable DMA mode.
880 * @param I2C_DmaBLen: length of data.
881 * This parameter must be set to a value in the 0-0xFF range.
882 * @retval None
883 */
I2C_DmaMode2Config(I2C_TypeDef * I2Cx,u32 I2C_DmaCmd,u32 I2C_DmaBLen)884 void I2C_DmaMode2Config(I2C_TypeDef *I2Cx, u32 I2C_DmaCmd, u32 I2C_DmaBLen)
885 {
886 /* Check the parameters */
887 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
888 assert_param(IS_I2C_DMA_DATA_LEN(I2C_DmaBLen));
889
890 I2Cx->IC_DMA_MOD = I2C_DMA_DESCRIPTOR;
891 I2Cx->IC_DMA_CMD = I2C_DmaCmd;
892 }
893
894 /**
895 * @brief Init and Enable I2C TX GDMA.
896 * @param Index: 0 .
897 * @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
898 * the configuration information for the GDMA peripheral.
899 * @param CallbackData: GDMA callback data.
900 * @param CallbackFunc: GDMA callback function.
901 * @param pTxBuf: Tx Buffer.
902 * @param TxCount: Tx Count.
903 * @retval TRUE/FLASE
904 * @note can not support legacy DMA mode
905 */
I2C_TXGDMA_Init(u8 Index,GDMA_InitTypeDef * GDMA_InitStruct,void * CallbackData,IRQ_FUN CallbackFunc,u8 * pTxBuf,int TxCount)906 BOOL I2C_TXGDMA_Init(
907 u8 Index,
908 GDMA_InitTypeDef *GDMA_InitStruct,
909 void *CallbackData,
910 IRQ_FUN CallbackFunc,
911 u8 *pTxBuf,
912 int TxCount
913 )
914 {
915 u8 GdmaChnl;
916
917 assert_param(GDMA_InitStruct != NULL);
918
919 GdmaChnl = GDMA_ChnlAlloc(0, (IRQ_FUN)CallbackFunc, (u32)CallbackData, 12);
920 if (GdmaChnl == 0xFF) {
921 /* No Available DMA channel */
922 return _FALSE;
923 }
924
925 _memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
926
927 GDMA_InitStruct->MuliBlockCunt = 0;
928 GDMA_InitStruct->MaxMuliBlock = 1;
929
930 GDMA_InitStruct->GDMA_DIR = TTFCMemToPeri;
931 GDMA_InitStruct->GDMA_DstHandshakeInterface = I2C_DEV_TABLE[Index].Tx_HandshakeInterface;
932 GDMA_InitStruct->GDMA_DstAddr = (u32)&I2C_DEV_TABLE[Index].I2Cx->IC_DATA_CMD;
933 GDMA_InitStruct->GDMA_Index = 0;
934 GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
935 GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType);
936
937 GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
938 GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte;
939 GDMA_InitStruct->GDMA_DstInc = NoChange;
940 GDMA_InitStruct->GDMA_SrcInc = IncType;
941
942 if (((TxCount & 0x03)==0) && (((u32)(pTxBuf) & 0x03)==0)) {
943 /* 4-bytes aligned, move 4 bytes each transfer */
944 GDMA_InitStruct->GDMA_SrcMsize = MsizeOne;
945 GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthFourBytes;
946 GDMA_InitStruct->GDMA_BlockSize = TxCount >> 2;
947 } else {
948 /* move 1 byte each transfer */
949 GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
950 GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthOneByte;
951 GDMA_InitStruct->GDMA_BlockSize = TxCount;
952 }
953
954 assert_param(GDMA_InitStruct->GDMA_BlockSize <= 4096);
955
956 GDMA_InitStruct->GDMA_SrcAddr = (u32)(pTxBuf);
957
958 GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
959 GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
960
961 return _TRUE;
962 }
963
964 /**
965 * @brief Init and Enable I2C RX GDMA.
966 * @param I2C Index: 0.
967 * @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
968 * the configuration information for the GDMA peripheral.
969 * @param CallbackData: GDMA callback data.
970 * @param CallbackFunc: GDMA callback function.
971 * @param pRxBuf: Rx Buffer.
972 * @param RxCount: Rx Count.
973 * @retval TRUE/FLASE
974 * @note support Master or Slave RXDMA
975 */
I2C_RXGDMA_Init(u8 Index,GDMA_InitTypeDef * GDMA_InitStruct,void * CallbackData,IRQ_FUN CallbackFunc,u8 * pRxBuf,int RxCount)976 BOOL I2C_RXGDMA_Init(
977 u8 Index,
978 GDMA_InitTypeDef *GDMA_InitStruct,
979 void *CallbackData,
980 IRQ_FUN CallbackFunc,
981 u8 *pRxBuf,
982 int RxCount
983 )
984 {
985 u8 GdmaChnl;
986
987 assert_param(GDMA_InitStruct != NULL);
988
989 GdmaChnl = GDMA_ChnlAlloc(0, (IRQ_FUN)CallbackFunc, (u32)CallbackData, 12);
990 if (GdmaChnl == 0xFF) {
991 /* No Available DMA channel */
992 return _FALSE;
993 }
994
995 _memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
996
997 GDMA_InitStruct->GDMA_DIR = TTFCPeriToMem;
998 GDMA_InitStruct->GDMA_ReloadSrc = 0;
999 GDMA_InitStruct->GDMA_SrcHandshakeInterface = I2C_DEV_TABLE[Index].Rx_HandshakeInterface;
1000 GDMA_InitStruct->GDMA_SrcAddr = (u32)&I2C_DEV_TABLE[Index].I2Cx->IC_DATA_CMD;
1001 GDMA_InitStruct->GDMA_Index = 0;
1002 GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
1003 GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType);
1004 GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
1005 GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthOneByte;
1006 GDMA_InitStruct->GDMA_DstInc = IncType;
1007 GDMA_InitStruct->GDMA_SrcInc = NoChange;
1008
1009 if (((u32)(pRxBuf) & 0x03)==0) {
1010 /* 4-bytes aligned, move 4 bytes each DMA transaction */
1011 GDMA_InitStruct->GDMA_DstMsize = MsizeOne;
1012 GDMA_InitStruct->GDMA_DstDataWidth = TrWidthFourBytes;
1013 } else {
1014 /* move 1 byte each DMA transaction */
1015 GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
1016 GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte;
1017 }
1018
1019 GDMA_InitStruct->GDMA_BlockSize = RxCount;
1020 GDMA_InitStruct->GDMA_DstAddr = (u32)(pRxBuf);
1021
1022 assert_param(GDMA_InitStruct->GDMA_BlockSize <= 4096);
1023
1024 /* multi block close */
1025 GDMA_InitStruct->MuliBlockCunt = 0;
1026 GDMA_InitStruct->GDMA_ReloadSrc = 0;
1027 GDMA_InitStruct->MaxMuliBlock = 1;
1028
1029 GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
1030 GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
1031
1032 return _TRUE;
1033 }
1034
1035 /**
1036 * @brief Clock-gated I2C clock domain for address matching interrupts wake up.
1037 * @param I2Cx: where I2Cx can be I2C0_DEV.
1038 * @param NewState: the new state of the Rx Path.
1039 * This parameter can be: ENABLE or DISABLE.
1040 * @retval None
1041 */
I2C_Sleep_Cmd(I2C_TypeDef * I2Cx,u32 NewStatus)1042 void I2C_Sleep_Cmd(I2C_TypeDef *I2Cx, u32 NewStatus)
1043 {
1044 /* Check the parameters */
1045 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
1046
1047 if (NewStatus != DISABLE) {
1048 I2C_INTConfig(I2Cx, BIT_IC_INTR_MASK_M_ADDR_1_MATCH|BIT_IC_INTR_MASK_M_ADDR_2_MATCH, ENABLE);
1049
1050 I2Cx->IC_SLEEP |= BIT_IC_SLEEP_CLOCK_CONTROL;
1051 } else {
1052 I2C_INTConfig(I2Cx, BIT_IC_INTR_MASK_M_ADDR_1_MATCH|BIT_IC_INTR_MASK_M_ADDR_2_MATCH, DISABLE);
1053
1054 I2Cx->IC_SLEEP &= ~BIT_IC_SLEEP_CLOCK_CONTROL;
1055 }
1056 }
1057
1058 /**
1059 * @brief Wake up clock domain of Clock-gated I2C after address matching interrupts.
1060 * @param I2Cx: where I2Cx can be I2C0_DEV.
1061 * @retval None
1062 */
I2C_WakeUp(I2C_TypeDef * I2Cx)1063 void I2C_WakeUp(I2C_TypeDef *I2Cx)
1064 {
1065 /* Check the parameters */
1066 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
1067
1068 I2C_ClearINT(I2Cx, BIT_IC_INTR_STAT_R_ADDR_2_MATCH);
1069 I2C_ClearINT(I2Cx, BIT_IC_INTR_STAT_R_ADDR_1_MATCH);
1070
1071 I2C_Sleep_Cmd(I2Cx, DISABLE);
1072 }
1073
1074 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
1075