1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef INTERNAL_I2C_REG_H 9 #define INTERNAL_I2C_REG_H 10 11 #include <stdint.h> 12 13 typedef union { 14 uint8_t DATA; 15 struct { 16 uint32_t FBT : 1; /* B00 First Byte Transfer */ 17 uint32_t reserved1 : 2; /* B01-02 Reserved */ 18 uint32_t TRX : 1; /* B03 Transfer/Receive */ 19 uint32_t LRB : 1; /* B04 LAST Received Bit */ 20 uint32_t reserved2 : 1; /* B05 Reserved */ 21 uint32_t RSC : 1; /* B06 Repeated Start Condition */ 22 uint32_t BB : 1; /* B07 Bus busy */ 23 } bit_COMMON; 24 struct { 25 uint32_t reserved1 : 1; /* B00 Reserved */ 26 uint32_t GCA : 1; /* B01 General Call Address */ 27 uint32_t AAS : 1; /* B02 Address As Target */ 28 uint32_t reserved2 : 2; /* B03-04 Reserved */ 29 uint32_t AL : 1; /* B05 Arbitration Lost */ 30 uint32_t reserved3 : 2; /* B06-07 Reserved */ 31 } bit_F_I2C; 32 } I2C_UN_BSR_t; 33 34 typedef union { 35 uint8_t DATA; 36 struct { 37 uint32_t reserved1 : 6; /* B00-05 Reserved */ 38 uint32_t HS : 1; /* B06 Hi Speed Mode */ 39 uint32_t MAS : 1; /* B07 Controller Code */ 40 } bit_F_I2C_SP1; 41 } I2C_UN_BS2R_t; 42 43 typedef union { 44 uint8_t DATA; 45 struct { 46 uint32_t INT : 1; /* B00 INTerrupt */ 47 uint32_t INTE : 1; /* B01 INTerrupt Enable */ 48 uint32_t reserved1 : 1; /* B02 Reserved */ 49 uint32_t ACK : 1; /* B03 Acknowledge Enable */ 50 uint32_t MSS : 1; /* B04 Controller Target Select 1:Controller */ 51 uint32_t SCC : 1; /* B05 Start Condition Continue */ 52 uint32_t BEIE : 1; /* B06 Bus Error Interrupt Enable */ 53 uint32_t BER : 1; /* B07 Bus Error */ 54 } bit_COMMON; 55 struct { 56 uint32_t reserved1 : 2; /* B00-01 Reserved */ 57 uint32_t GCAA : 1; /* B02 General Call Address Acknowledge */ 58 uint32_t reserved2 : 5; /* B03-07 Reserved */ 59 } bit_F_I2C; 60 } I2C_UN_BCR_t; 61 62 typedef union { 63 uint8_t DATA; 64 struct { 65 uint32_t SCLL : 1; /* B00 SCL Low drive */ 66 uint32_t SDAL : 1; /* B01 SDA Low drive */ 67 uint32_t reserved1 : 2; /* B02-B03 Reserved */ 68 uint32_t SCLS : 1; /* B04 SCL Status(Read Only) */ 69 uint32_t SDAS : 1; /* B05 SDA Status(Read Only) */ 70 uint32_t reserved2 : 2; /* B06-B07 Reserved */ 71 } bit_COMMON; 72 struct { 73 uint32_t reserved1 : 7; /* B00-07 Reserved */ 74 uint32_t EN : 1; /* B07 Enable */ 75 } bit_F_I2C_SP1; 76 } I2C_UN_BC2R_t; 77 78 typedef union { 79 uint8_t DATA; 80 struct { 81 uint32_t A : 7; /* B00-B06 Address */ 82 uint32_t reserved1 : 1; /* B07 Reserved */ 83 } bit_COMMON; 84 } I2C_UN_ADR_t; 85 86 typedef union { 87 uint8_t DATA; 88 struct { 89 uint32_t D : 8; /* B00-B07 Serial Data */ 90 } bit_COMMON; 91 } I2C_UN_DAR_t; 92 93 typedef union { 94 uint8_t DATA; 95 struct { 96 uint32_t NF : 5; /* B00-04 Noise Filter Select for Sm/FM/FM+ */ 97 uint32_t NFH : 3; /* B05-07 Noise Filter Select for Hs */ 98 } bit_F_I2C_SP1; 99 } I2C_UN_NFR_t; 100 101 typedef union { 102 uint8_t DATA; 103 struct { 104 uint32_t TLW : 8; 105 } bit_F_I2C_SP1; 106 } I2C_UN_TLWR_t; 107 108 typedef union { 109 uint8_t DATA; 110 struct { 111 uint32_t TLW : 8; 112 } bit_F_I2C_SP1; 113 } I2C_UN_TLW2R_t; 114 115 typedef union { 116 uint8_t DATA; 117 struct { 118 uint32_t THW : 8; 119 } bit_F_I2C_SP1; 120 } I2C_UN_THWR_t; 121 122 typedef union { 123 uint8_t DATA; 124 struct { 125 uint32_t THW : 8; 126 } bit_F_I2C_SP1; 127 } I2C_UN_THW2R_t; 128 129 typedef union { 130 uint8_t DATA; 131 struct { 132 uint32_t TBF : 8; 133 } bit_F_I2C_SP1; 134 } I2C_UN_TBFR_t; 135 136 typedef union { 137 uint8_t DATA; 138 struct { 139 uint32_t TBF : 8; 140 } bit_F_I2C_SP1; 141 } I2C_UN_TBF2R_t; 142 143 typedef union { 144 uint8_t DATA; 145 struct { 146 uint32_t TRS : 8; 147 } bit_F_I2C_SP1; 148 } I2C_UN_TRSR_t; 149 150 typedef union { 151 uint8_t DATA; 152 struct { 153 uint32_t TRS : 8; 154 } bit_F_I2C_SP1; 155 } I2C_UN_TRS2R_t; 156 157 typedef union { 158 uint8_t DATA; 159 struct { 160 uint32_t TSH : 8; 161 } bit_F_I2C_SP1; 162 } I2C_UN_TSHR_t; 163 164 typedef union { 165 uint8_t DATA; 166 struct { 167 uint32_t TSH : 8; 168 } bit_F_I2C_SP1; 169 } I2C_UN_TSH2R_t; 170 171 typedef union { 172 uint8_t DATA; 173 struct { 174 uint32_t TPS : 8; 175 } bit_F_I2C_SP1; 176 } I2C_UN_TPSR_t; 177 178 typedef union { 179 uint8_t DATA; 180 struct { 181 uint32_t TPS : 8; 182 } bit_F_I2C_SP1; 183 } I2C_UN_TPS2R_t; 184 185 typedef union { 186 uint8_t DATA; 187 struct { 188 uint32_t TLWH : 8; 189 } bit_F_I2C_SP1; 190 } I2C_UN_TLWRH_t; 191 192 typedef union { 193 uint8_t DATA; 194 struct { 195 uint32_t THWH : 8; 196 } bit_F_I2C_SP1; 197 } I2C_UN_THWRH_t; 198 199 typedef union { 200 uint8_t DATA; 201 struct { 202 uint32_t TRSH : 8; 203 } bit_F_I2C_SP1; 204 } I2C_UN_TRSRH_t; 205 206 typedef union { 207 uint8_t DATA; 208 struct { 209 uint32_t TSHH : 8; 210 } bit_F_I2C_SP1; 211 } I2C_UN_TSHRH_t; 212 213 typedef union { 214 uint8_t DATA; 215 struct { 216 uint32_t TPSH : 8; 217 } bit_F_I2C_SP1; 218 } I2C_UN_TPSRH_t; 219 220 typedef union { 221 uint8_t DATA; 222 struct { 223 uint32_t CS : 5; /* B00-B04 Clock Period Select 4-0 */ 224 uint32_t EN : 1; /* B05 Enable */ 225 uint32_t FM : 1; /* B06 High Speed Mode */ 226 uint32_t reserved1 : 1; /* B07 Reserved */ 227 } bit_F_I2C; 228 } I2C_UN_CCR_t; 229 230 typedef union { 231 uint8_t DATA; 232 struct { 233 uint32_t CS : 6; /* B00-B05 Clock Period Select 10-5 */ 234 uint32_t TST : 2; /* B06-B07 TST1, TST0 */ 235 } bit_F_I2C; 236 } I2C_UN_CSR_t; 237 238 typedef union { 239 uint8_t DATA; 240 struct { 241 uint32_t FS : 4; /* B00-B03 Bus Clock Frequency Select 3-0 */ 242 uint32_t reserved1 : 4; /* B04-B07 Reserved */ 243 } bit_F_I2C; 244 } I2C_UN_FSR_t; 245 246 /*! 247 * \brief SYNQUACER I2C register address definitions 248 */ 249 #define I2C_REG_ADDR_BSR (0x00U) 250 #define I2C_REG_ADDR_BCR (0x04U) 251 #define I2C_REG_ADDR_CCR (0x08U) 252 #define I2C_REG_ADDR_ADR (0x0CU) 253 #define I2C_REG_ADDR_DAR (0x10U) 254 #define I2C_REG_ADDR_CSR (0x14U) 255 #define I2C_REG_ADDR_FSR (0x18U) 256 #define I2C_REG_ADDR_BC2R (0x1CU) 257 258 #define I2C_SP1_REG_ADDR_BSR ((0x00U) << 2) 259 #define I2C_SP1_REG_ADDR_BS2R ((0x01U) << 2) 260 #define I2C_SP1_REG_ADDR_BCR ((0x02U) << 2) 261 #define I2C_SP1_REG_ADDR_BC2R ((0x03U) << 2) 262 #define I2C_SP1_REG_ADDR_ADR ((0x04U) << 2) 263 #define I2C_SP1_REG_ADDR_DAR ((0x05U) << 2) 264 #define I2C_SP1_REG_ADDR_NFR ((0x06U) << 2) 265 #define I2C_SP1_REG_ADDR_TLWR ((0x07U) << 2) 266 #define I2C_SP1_REG_ADDR_TLW2R ((0x08U) << 2) 267 #define I2C_SP1_REG_ADDR_THWR ((0x09U) << 2) 268 #define I2C_SP1_REG_ADDR_THW2R ((0x0AU) << 2) 269 #define I2C_SP1_REG_ADDR_TBFR ((0x0BU) << 2) 270 #define I2C_SP1_REG_ADDR_TBF2R ((0x0CU) << 2) 271 #define I2C_SP1_REG_ADDR_TRSR ((0x0DU) << 2) 272 #define I2C_SP1_REG_ADDR_TRS2R ((0x0EU) << 2) 273 #define I2C_SP1_REG_ADDR_TSHR ((0x0FU) << 2) 274 #define I2C_SP1_REG_ADDR_TSH2R ((0x10U) << 2) 275 #define I2C_SP1_REG_ADDR_TPSR ((0x11U) << 2) 276 #define I2C_SP1_REG_ADDR_TPS2R ((0x12U) << 2) 277 #define I2C_SP1_REG_ADDR_TLWRH ((0x13U) << 2) 278 #define I2C_SP1_REG_ADDR_THWRH ((0x14U) << 2) 279 #define I2C_SP1_REG_ADDR_TRSRH ((0x15U) << 2) 280 #define I2C_SP1_REG_ADDR_TSHRH ((0x16U) << 2) 281 #define I2C_SP1_REG_ADDR_TPSRH ((0x17U) << 2) 282 283 #endif /* INTERNAL_I2C_REG_H */ 284