1 /*
2  * Copyright 2014, General Dynamics C4 Systems
3  *
4  * SPDX-License-Identifier: GPL-2.0-only
5  */
6 
7 #pragma once
8 
9 #include <arch/types.h>
10 #include <arch/object/structures.h>
11 #include <arch/machine/hardware.h>
12 #include <arch/machine/pat.h>
13 #include <arch/machine/cpu_registers.h>
14 #include <model/statedata.h>
15 #include <arch/model/statedata.h>
16 #include <object/interrupt.h>
17 
18 #define IA32_APIC_BASE_MSR      0x01B
19 #define IA32_ARCH_CAPABILITIES_MSR 0x10A
20 #define IA32_SYSENTER_CS_MSR    0x174
21 #define IA32_SYSENTER_ESP_MSR   0x175
22 #define IA32_SYSENTER_EIP_MSR   0x176
23 #define IA32_TSC_DEADLINE_MSR   0x6e0
24 #define IA32_FS_BASE_MSR        0xC0000100
25 #define IA32_GS_BASE_MSR        0xC0000101
26 #define IA32_LSTAR_MSR          0xC0000082
27 #define IA32_STAR_MSR           0xC0000081
28 #define IA32_FMASK_MSR          0xC0000084
29 #define IA32_EFER_MSR 0xC0000080
30 #define IA32_PLATFORM_INFO_MSR  0xCE
31 #define IA32_XSS_MSR            0xD0A
32 #define IA32_FEATURE_CONTROL_MSR 0x3A
33 #define IA32_KERNEL_GS_BASE_MSR 0xC0000102
34 #define IA32_VMX_BASIC_MSR      0x480
35 #define IA32_VMX_PINBASED_CTLS_MSR 0x481
36 #define IA32_VMX_PROCBASED_CTLS_MSR 0x482
37 #define IA32_VMX_PROCBASED_CTLS2_MSR 0x48B
38 #define IA32_VMX_EXIT_CTLS_MSR  0x483
39 #define IA32_VMX_ENTRY_CTLS_MSR 0x484
40 #define IA32_VMX_TRUE_PINBASED_CTLS_MSR 0x48D
41 #define IA32_VMX_TRUE_PROCBASED_CTLS_MSR 0x48E
42 #define IA32_VMX_TRUE_EXIT_CTLS_MSR 0x48F
43 #define IA32_VMX_TRUE_ENTRY_CTLS_MSR 0x490
44 #define IA32_VMX_CR0_FIXED0_MSR 0x486
45 #define IA32_VMX_CR0_FIXED1_MSR 0x487
46 #define IA32_VMX_CR4_FIXED0_MSR 0x488
47 #define IA32_VMX_CR4_FIXED1_MSR 0x489
48 #define IA32_VMX_EPT_VPID_CAP_MSR 0x48C
49 
50 #define IA32_PREFETCHER_COMPATIBLE_FAMILIES_ID (0x06)
51 
52 /* These values taken from:
53  *  * Intel manuals, Vol3, table 35-1.
54  *  * https://software.intel.com/en-us/articles/intel-architecture-and-processor-identification-with-cpuid-model-and-family-numbers
55  */
56 #define SKYLAKE_1_MODEL_ID      0x4E
57 #define SKYLAKE_2_MODEL_ID      0x5E
58 #define BROADWELL_1_MODEL_ID    0x4D
59 #define BROADWELL_2_MODEL_ID    0x56
60 #define BROADWELL_3_MODEL_ID    0x4F
61 #define BROADWELL_4_MODEL_ID    0x47
62 #define BROADWELL_5_MODEL_ID    0x3D
63 #define HASWELL_1_MODEL_ID      0x3C
64 #define HASWELL_2_MODEL_ID      0x3F
65 #define HASWELL_3_MODEL_ID      0x45
66 #define HASWELL_4_MODEL_ID      0x46
67 #define IVY_BRIDGE_1_MODEL_ID   0x9A
68 #define IVY_BRIDGE_2_MODEL_ID   0x3E
69 #define IVY_BRIDGE_3_MODEL_ID   0x3A
70 #define SANDY_BRIDGE_1_MODEL_ID 0x2A /* Sandy Bridge */
71 #define SANDY_BRIDGE_2_MODEL_ID 0x2D /* Sandy Bridge-E, Sandy Bridge-EN and Sandy Bridge-EP */
72 #define WESTMERE_1_MODEL_ID     0x25 /* Arrandale and Clarksdale */
73 #define WESTMERE_2_MODEL_ID     0x2C /* Gulftown and Westmere-EP */
74 #define WESTMERE_3_MODEL_ID     0x2F /* Westemere-EX */
75 #define NEHALEM_1_MODEL_ID      0x1E /* Clarksfield, Lynnfield and Jasper Forest */
76 #define NEHALEM_2_MODEL_ID      0x1A /* Bloomfield and Nehalem-EP */
77 #define NEHALEM_3_MODEL_ID      0x2E /* Nehalem-EX */
78 
79 #define X86_CPUID_VENDOR_STRING_MAXLENGTH   (12)
80 #define X86_CPU_MODEL_STRING_MAXLENGTH      (47)
81 
82 /* This article discloses prefetcher control on Intel processors; Nehalem, Westmere, Sandy Bridge,
83    Ivy Bridge, Haswell, and Broadwell. It is currently undocumented in the regular intel manuals.
84    https://software.intel.com/en-us/articles/disclosure-of-hw-prefetcher-control-on-some-intel-processors */
85 #define IA32_PREFETCHER_MSR                 0x1A4
86 #define IA32_PREFETCHER_MSR_L2              BIT(0)
87 #define IA32_PREFETCHER_MSR_L2_ADJACENT     BIT(1)
88 #define IA32_PREFETCHER_MSR_DCU             BIT(2)
89 #define IA32_PREFETCHER_MSR_DCU_IP          BIT(3)
90 
91 #define IA32_SPEC_CTRL_MSR                  0x48
92 #define IA32_SPEC_CTRL_MSR_IBRS             BIT(0) /* Indirect Branch Restricted Speculation */
93 #define IA32_SPEC_CTRL_MSR_STIBP            BIT(1) /* Single Thread Indirect Branch Predictors */
94 
95 #define IA32_PRED_CMD_MSR                   0x49
96 
97 word_t PURE getRestartPC(tcb_t *thread);
98 void setNextPC(tcb_t *thread, word_t v);
99 
x86_rdmsr(const uint32_t reg)100 static uint64_t x86_rdmsr(const uint32_t reg)
101 {
102     uint32_t low, high;
103     uint64_t value;
104     asm volatile("rdmsr" : "=a"(low), "=d"(high) : "c"(reg));
105     value = ((uint64_t)high << 32) | (uint64_t)low;
106     return value;
107 }
108 
109 /* Read model specific register */
x86_rdmsr_low(const uint32_t reg)110 static inline uint32_t x86_rdmsr_low(const uint32_t reg)
111 {
112     return (uint32_t)x86_rdmsr(reg);
113 }
114 
x86_rdmsr_high(const uint32_t reg)115 static inline uint32_t x86_rdmsr_high(const uint32_t reg)
116 {
117     return (uint32_t)(x86_rdmsr(reg) >> 32ull);
118 }
119 
120 /* Write model specific register */
x86_wrmsr_parts(const uint32_t reg,const uint32_t high,const uint32_t low)121 static inline void x86_wrmsr_parts(const uint32_t reg, const uint32_t high, const uint32_t low)
122 {
123     asm volatile("wrmsr" :: "a"(low), "d"(high), "c"(reg));
124 }
125 
x86_wrmsr(const uint32_t reg,const uint64_t val)126 static inline void x86_wrmsr(const uint32_t reg, const uint64_t val)
127 {
128     uint32_t low = (uint32_t)val;
129     uint32_t high = (uint32_t)(val >> 32);
130     x86_wrmsr_parts(reg, high, low);
131 }
132 
133 /* Read different parts of CPUID */
x86_cpuid_edx(uint32_t eax,uint32_t ecx)134 static inline uint32_t x86_cpuid_edx(uint32_t eax, uint32_t ecx)
135 {
136     uint32_t edx, ebx;
137     asm volatile("cpuid"
138                  : "=a"(eax),
139                  "=b"(ebx),
140                  "=c"(ecx),
141                  "=d"(edx)
142                  : "a"(eax), "c"(ecx)
143                  : "memory");
144     return edx;
145 }
146 
x86_cpuid_eax(uint32_t eax,uint32_t ecx)147 static inline uint32_t x86_cpuid_eax(uint32_t eax, uint32_t ecx)
148 {
149     uint32_t edx, ebx;
150     asm volatile("cpuid"
151                  : "=a"(eax),
152                  "=b"(ebx),
153                  "=c"(ecx),
154                  "=d"(edx)
155                  : "a"(eax), "c"(ecx)
156                  : "memory");
157     return eax;
158 }
159 
x86_cpuid_ecx(uint32_t eax,uint32_t ecx)160 static inline uint32_t x86_cpuid_ecx(uint32_t eax, uint32_t ecx)
161 {
162     uint32_t edx, ebx;
163     asm volatile("cpuid"
164                  : "=a"(eax),
165                  "=b"(ebx),
166                  "=c"(ecx),
167                  "=d"(edx)
168                  : "a"(eax), "c"(ecx)
169                  : "memory");
170     return ecx;
171 }
172 
x86_cpuid_ebx(uint32_t eax,uint32_t ecx)173 static inline uint32_t x86_cpuid_ebx(uint32_t eax, uint32_t ecx)
174 {
175     uint32_t edx, ebx;
176     asm volatile("cpuid"
177                  : "=a"(eax),
178                  "=b"(ebx),
179                  "=c"(ecx),
180                  "=d"(edx)
181                  : "a"(eax), "c"(ecx)
182                  : "memory");
183     return ebx;
184 }
185 
x86_rdtsc(void)186 static inline uint64_t x86_rdtsc(void)
187 {
188     uint32_t hi, lo;
189     asm volatile("rdtsc"
190                  : "=a"(lo),
191                  "=d"(hi)
192                 );
193     return ((uint64_t) hi) << 32llu | (uint64_t) lo;
194 }
195 
196 #ifdef ENABLE_SMP_SUPPORT
arch_pause(void)197 static inline void arch_pause(void)
198 {
199     asm volatile("pause");
200 }
201 #endif /* ENABLE_SMP_SUPPORT */
202 
203 enum x86_vendor {
204     X86_VENDOR_INTEL = 0,
205     X86_VENDOR_AMD,
206     X86_VENDOR_OTHER
207 };
208 
209 typedef struct _x86_cpu_identity {
210     uint8_t family, model, stepping, extended_family, extended_model;
211     uint8_t brand;
212 } x86_cpu_identity_t;
213 
214 typedef struct _cpu_identity {
215     enum x86_vendor vendor;
216     char vendor_string[X86_CPUID_VENDOR_STRING_MAXLENGTH + 1];
217 
218     /* Adjusted and normalized family, model and stepping values as recommended
219      * by Intel. The name "display" was chosen because that's the nomenclature
220      * Intel uses.
221      */
222     x86_cpu_identity_t display;
223 } cpu_identity_t;
224 
225 /* This, and all its adjoint routines will be called at init time; see boot.c */
226 BOOT_CODE bool_t x86_cpuid_initialize(void);
227 
228 /** To be used by code that wants to know the family/model/stepping/brand of
229  * a CPU.
230  */
231 x86_cpu_identity_t *x86_cpuid_get_model_info(void);
232 
233 /** To be used by code that wants to get the CPU vendor name.
234  */
235 cpu_identity_t *x86_cpuid_get_identity(void);
236 
237 /*
238  * Forward declarations here as these may instead be later defined in
239  * mode-specific machine.h
240  */
241 
242 static inline void x86_write_fs_base_impl(word_t base);
243 static inline word_t x86_read_fs_base_impl(void);
244 static inline void x86_write_gs_base_impl(word_t base);
245 static inline word_t x86_read_gs_base_impl(void);
246 
247 #ifdef CONFIG_FSGSBASE_MSR
248 
x86_write_fs_base_impl(word_t base)249 static inline void x86_write_fs_base_impl(word_t base)
250 {
251     x86_wrmsr(IA32_FS_BASE_MSR, base);
252 }
253 
x86_read_fs_base_impl(void)254 static inline word_t x86_read_fs_base_impl(void)
255 {
256     return x86_rdmsr(IA32_FS_BASE_MSR);
257 }
258 
259 #endif
260 
261 
262 #ifdef CONFIG_FSGSBASE_INST
263 
264 /*
265  * With fsgsbase, these registers can and are allowed to be changed from
266  * user-space.
267  *
268  * These calls are also cheap as they read from the hidden register
269  * state for the segment selectors rather than from the GDT.
270  */
271 
x86_write_fs_base(word_t base,cpu_id_t cpu)272 static inline void x86_write_fs_base(word_t base, cpu_id_t cpu)
273 {
274     x86_write_fs_base_impl(base);
275 }
276 
x86_write_gs_base(word_t base,cpu_id_t cpu)277 static inline void x86_write_gs_base(word_t base, cpu_id_t cpu)
278 {
279     x86_write_gs_base_impl(base);
280 }
281 
x86_read_fs_base(cpu_id_t cpu)282 static inline word_t x86_read_fs_base(cpu_id_t cpu)
283 {
284     return x86_read_fs_base_impl();
285 }
286 
x86_read_gs_base(cpu_id_t cpu)287 static inline word_t x86_read_gs_base(cpu_id_t cpu)
288 {
289     return x86_read_gs_base_impl();
290 }
291 
292 #else
293 
294 /* Writing the fs/gs bases can be expensive (especially if it requires a MSR
295    write), so we avoid actually writing them if they aren't actually changed. */
296 
x86_write_fs_base(word_t base,cpu_id_t cpu)297 static inline void x86_write_fs_base(word_t base, cpu_id_t cpu)
298 {
299     if (base != ARCH_NODE_STATE_ON_CORE(x86KSCurrentFSBase, cpu)) {
300         ARCH_NODE_STATE_ON_CORE(x86KSCurrentFSBase, cpu) = base;
301         x86_write_fs_base_impl(base);
302     }
303 }
304 
x86_write_gs_base(word_t base,cpu_id_t cpu)305 static inline void x86_write_gs_base(word_t base, cpu_id_t cpu)
306 {
307     if (likely(base != ARCH_NODE_STATE_ON_CORE(x86KSCurrentGSBase, cpu))) {
308         ARCH_NODE_STATE_ON_CORE(x86KSCurrentGSBase, cpu) = base;
309         x86_write_gs_base_impl(base);
310     }
311 }
312 
x86_read_fs_base(cpu_id_t cpu)313 static inline word_t x86_read_fs_base(cpu_id_t cpu)
314 {
315     return ARCH_NODE_STATE_ON_CORE(x86KSCurrentFSBase, cpu);
316 }
317 
x86_read_gs_base(cpu_id_t cpu)318 static inline word_t x86_read_gs_base(cpu_id_t cpu)
319 {
320     return ARCH_NODE_STATE_ON_CORE(x86KSCurrentGSBase, cpu);
321 }
322 
323 #endif
324 
325 
x86_load_fsgs_base(tcb_t * thread,cpu_id_t cpu)326 static inline void x86_load_fsgs_base(tcb_t *thread, cpu_id_t cpu)
327 {
328     /*
329      * Restore the FS and GS base registers.
330      *
331      * These should only be accessed inside the kernel, between the
332      * entry and exit calls to swapgs if used.
333      */
334     word_t fs_base = getRegister(thread, FS_BASE);
335     x86_write_fs_base(fs_base, cpu);
336     word_t gs_base = getRegister(thread, GS_BASE);
337     x86_write_gs_base(gs_base, cpu);
338 }
339 
340 /* Cleaning memory before user-level access */
clearMemory(void * ptr,unsigned int bits)341 static inline void clearMemory(void *ptr, unsigned int bits)
342 {
343     memzero(ptr, BIT(bits));
344     /* no cleaning of caches necessary on IA-32 */
345 }
346 
347 /* Initialises MSRs required to setup sysenter and sysexit */
348 void init_sysenter_msrs(void);
349 
350 /* Read/write memory fence */
x86_mfence(void)351 static inline void x86_mfence(void)
352 {
353     asm volatile("mfence" ::: "memory");
354 }
355 
356 /* Get page fault address from CR2 register */
getFaultAddr(void)357 static inline unsigned long getFaultAddr(void)
358 {
359     return read_cr2();
360 }
361 
362 static inline void x86_set_tls_segment_base(word_t tls_base);
363 
364 /* Update the value of the actual register to hold the expected value */
Arch_setTLSRegister(word_t tls_base)365 static inline exception_t Arch_setTLSRegister(word_t tls_base)
366 {
367     word_t sanitised = Mode_sanitiseRegister(TLS_BASE, tls_base);
368 
369     if (sanitised != tls_base) {
370         return EXCEPTION_SYSCALL_ERROR;
371     }
372 
373 #ifndef CONFIG_FSGSBASE_INST
374     /*
375      * The context is only updated from the register on a context switch
376      * if the FSGS instructions are enabled. When they aren't it must be
377      * manually stored here.
378      */
379     setRegister(NODE_STATE(ksCurThread), TLS_BASE, tls_base);
380 #endif
381 
382     x86_set_tls_segment_base(sanitised);
383 
384     return EXCEPTION_NONE;
385 }
386 
387 /* we do not cache the IBRS value as writing the enable bit is meaningful even if it
388  * is already set. On some processors if the enable bit was set it must be 're-written'
389  * in order for a higher privilege to correctly not have its branch predictions affected */
x86_enable_ibrs(void)390 static inline void x86_enable_ibrs(void)
391 {
392     /* we always enable the STIBP bit since we want it on if its supported and it
393      * isn't a fault to set the bit if support is missing */
394     x86_wrmsr(IA32_SPEC_CTRL_MSR, IA32_SPEC_CTRL_MSR_IBRS | IA32_SPEC_CTRL_MSR_STIBP);
395 }
396 
x86_disable_ibrs(void)397 static inline void x86_disable_ibrs(void)
398 {
399     /* we always enable the STIBP bit since we want it on if its supported and it
400      * isn't a fault to set the bit if support is missing */
401     x86_wrmsr(IA32_SPEC_CTRL_MSR, IA32_SPEC_CTRL_MSR_STIBP);
402 }
403 
x86_ibpb(void)404 static inline void x86_ibpb(void)
405 {
406     x86_wrmsr(IA32_PRED_CMD_MSR, 1);
407 }
408 
x86_flush_rsb(void)409 static inline void x86_flush_rsb(void)
410 {
411     /* perform 32 near calls with a non zero displacement to flush the rsb with
412      * speculation traps. */
413     word_t iter = 32;
414     asm volatile(
415         "1:\n"
416         "sub $2, %[iter]\n"
417         "call 2f\n"
418         "pause\n"
419         "jmp 1b\n"
420         "2:\n"
421         "call 3f\n"
422         "pause\n"
423         "jmp 2b\n"
424         "3:\n"
425         "cmp $0, %[iter]\n"
426         "jne 1b\n"
427 #ifdef CONFIG_ARCH_X86_64
428         "add %[stack_amount], %%rsp\n"
429 #else
430         "add %[stack_amount], %%esp\n"
431 #endif
432         : [iter]"+r"(iter)
433         : [stack_amount]"i"(sizeof(word_t) * iter)
434         : "cc"
435     );
436 }
437 
438 /* sysenter entry point */
439 void handle_syscall(void);
440 
441 /** MODIFIES: phantom_machine_state */
442 void int_00(void);
443 /** MODIFIES: phantom_machine_state */
444 void int_01(void);
445 /** MODIFIES: phantom_machine_state */
446 void int_02(void);
447 /** MODIFIES: phantom_machine_state */
448 void int_03(void);
449 /** MODIFIES: phantom_machine_state */
450 void int_04(void);
451 /** MODIFIES: phantom_machine_state */
452 void int_05(void);
453 /** MODIFIES: phantom_machine_state */
454 void int_06(void);
455 /** MODIFIES: phantom_machine_state */
456 void int_07(void);
457 /** MODIFIES: phantom_machine_state */
458 void int_08(void);
459 /** MODIFIES: phantom_machine_state */
460 void int_09(void);
461 /** MODIFIES: phantom_machine_state */
462 void int_0a(void);
463 /** MODIFIES: phantom_machine_state */
464 void int_0b(void);
465 /** MODIFIES: phantom_machine_state */
466 void int_0c(void);
467 /** MODIFIES: phantom_machine_state */
468 void int_0d(void);
469 /** MODIFIES: phantom_machine_state */
470 void int_0e(void);
471 /** MODIFIES: phantom_machine_state */
472 void int_0f(void);
473 
474 /** MODIFIES: phantom_machine_state */
475 void int_10(void);
476 /** MODIFIES: phantom_machine_state */
477 void int_11(void);
478 /** MODIFIES: phantom_machine_state */
479 void int_12(void);
480 /** MODIFIES: phantom_machine_state */
481 void int_13(void);
482 /** MODIFIES: phantom_machine_state */
483 void int_14(void);
484 /** MODIFIES: phantom_machine_state */
485 void int_15(void);
486 /** MODIFIES: phantom_machine_state */
487 void int_16(void);
488 /** MODIFIES: phantom_machine_state */
489 void int_17(void);
490 /** MODIFIES: phantom_machine_state */
491 void int_18(void);
492 /** MODIFIES: phantom_machine_state */
493 void int_19(void);
494 /** MODIFIES: phantom_machine_state */
495 void int_1a(void);
496 /** MODIFIES: phantom_machine_state */
497 void int_1b(void);
498 /** MODIFIES: phantom_machine_state */
499 void int_1c(void);
500 /** MODIFIES: phantom_machine_state */
501 void int_1d(void);
502 /** MODIFIES: phantom_machine_state */
503 void int_1e(void);
504 /** MODIFIES: phantom_machine_state */
505 void int_1f(void);
506 
507 /** MODIFIES: phantom_machine_state */
508 void int_20(void);
509 /** MODIFIES: phantom_machine_state */
510 void int_21(void);
511 /** MODIFIES: phantom_machine_state */
512 void int_22(void);
513 /** MODIFIES: phantom_machine_state */
514 void int_23(void);
515 /** MODIFIES: phantom_machine_state */
516 void int_24(void);
517 /** MODIFIES: phantom_machine_state */
518 void int_25(void);
519 /** MODIFIES: phantom_machine_state */
520 void int_26(void);
521 /** MODIFIES: phantom_machine_state */
522 void int_27(void);
523 /** MODIFIES: phantom_machine_state */
524 void int_28(void);
525 /** MODIFIES: phantom_machine_state */
526 void int_29(void);
527 /** MODIFIES: phantom_machine_state */
528 void int_2a(void);
529 /** MODIFIES: phantom_machine_state */
530 void int_2b(void);
531 /** MODIFIES: phantom_machine_state */
532 void int_2c(void);
533 /** MODIFIES: phantom_machine_state */
534 void int_2d(void);
535 /** MODIFIES: phantom_machine_state */
536 void int_2e(void);
537 /** MODIFIES: phantom_machine_state */
538 void int_2f(void);
539 
540 /** MODIFIES: phantom_machine_state */
541 void int_30(void);
542 /** MODIFIES: phantom_machine_state */
543 void int_31(void);
544 /** MODIFIES: phantom_machine_state */
545 void int_32(void);
546 /** MODIFIES: phantom_machine_state */
547 void int_33(void);
548 /** MODIFIES: phantom_machine_state */
549 void int_34(void);
550 /** MODIFIES: phantom_machine_state */
551 void int_35(void);
552 /** MODIFIES: phantom_machine_state */
553 void int_36(void);
554 /** MODIFIES: phantom_machine_state */
555 void int_37(void);
556 /** MODIFIES: phantom_machine_state */
557 void int_38(void);
558 /** MODIFIES: phantom_machine_state */
559 void int_39(void);
560 /** MODIFIES: phantom_machine_state */
561 void int_3a(void);
562 /** MODIFIES: phantom_machine_state */
563 void int_3b(void);
564 /** MODIFIES: phantom_machine_state */
565 void int_3c(void);
566 /** MODIFIES: phantom_machine_state */
567 void int_3d(void);
568 /** MODIFIES: phantom_machine_state */
569 void int_3e(void);
570 /** MODIFIES: phantom_machine_state */
571 void int_3f(void);
572 
573 /** MODIFIES: phantom_machine_state */
574 void int_40(void);
575 /** MODIFIES: phantom_machine_state */
576 void int_41(void);
577 /** MODIFIES: phantom_machine_state */
578 void int_42(void);
579 /** MODIFIES: phantom_machine_state */
580 void int_43(void);
581 /** MODIFIES: phantom_machine_state */
582 void int_44(void);
583 /** MODIFIES: phantom_machine_state */
584 void int_45(void);
585 /** MODIFIES: phantom_machine_state */
586 void int_46(void);
587 /** MODIFIES: phantom_machine_state */
588 void int_47(void);
589 /** MODIFIES: phantom_machine_state */
590 void int_48(void);
591 /** MODIFIES: phantom_machine_state */
592 void int_49(void);
593 /** MODIFIES: phantom_machine_state */
594 void int_4a(void);
595 /** MODIFIES: phantom_machine_state */
596 void int_4b(void);
597 /** MODIFIES: phantom_machine_state */
598 void int_4c(void);
599 /** MODIFIES: phantom_machine_state */
600 void int_4d(void);
601 /** MODIFIES: phantom_machine_state */
602 void int_4e(void);
603 /** MODIFIES: phantom_machine_state */
604 void int_4f(void);
605 
606 /** MODIFIES: phantom_machine_state */
607 void int_50(void);
608 /** MODIFIES: phantom_machine_state */
609 void int_51(void);
610 /** MODIFIES: phantom_machine_state */
611 void int_52(void);
612 /** MODIFIES: phantom_machine_state */
613 void int_53(void);
614 /** MODIFIES: phantom_machine_state */
615 void int_54(void);
616 /** MODIFIES: phantom_machine_state */
617 void int_55(void);
618 /** MODIFIES: phantom_machine_state */
619 void int_56(void);
620 /** MODIFIES: phantom_machine_state */
621 void int_57(void);
622 /** MODIFIES: phantom_machine_state */
623 void int_58(void);
624 /** MODIFIES: phantom_machine_state */
625 void int_59(void);
626 /** MODIFIES: phantom_machine_state */
627 void int_5a(void);
628 /** MODIFIES: phantom_machine_state */
629 void int_5b(void);
630 /** MODIFIES: phantom_machine_state */
631 void int_5c(void);
632 /** MODIFIES: phantom_machine_state */
633 void int_5d(void);
634 /** MODIFIES: phantom_machine_state */
635 void int_5e(void);
636 /** MODIFIES: phantom_machine_state */
637 void int_5f(void);
638 
639 /** MODIFIES: phantom_machine_state */
640 void int_60(void);
641 /** MODIFIES: phantom_machine_state */
642 void int_61(void);
643 /** MODIFIES: phantom_machine_state */
644 void int_62(void);
645 /** MODIFIES: phantom_machine_state */
646 void int_63(void);
647 /** MODIFIES: phantom_machine_state */
648 void int_64(void);
649 /** MODIFIES: phantom_machine_state */
650 void int_65(void);
651 /** MODIFIES: phantom_machine_state */
652 void int_66(void);
653 /** MODIFIES: phantom_machine_state */
654 void int_67(void);
655 /** MODIFIES: phantom_machine_state */
656 void int_68(void);
657 /** MODIFIES: phantom_machine_state */
658 void int_69(void);
659 /** MODIFIES: phantom_machine_state */
660 void int_6a(void);
661 /** MODIFIES: phantom_machine_state */
662 void int_6b(void);
663 /** MODIFIES: phantom_machine_state */
664 void int_6c(void);
665 /** MODIFIES: phantom_machine_state */
666 void int_6d(void);
667 /** MODIFIES: phantom_machine_state */
668 void int_6e(void);
669 /** MODIFIES: phantom_machine_state */
670 void int_6f(void);
671 
672 /** MODIFIES: phantom_machine_state */
673 void int_70(void);
674 /** MODIFIES: phantom_machine_state */
675 void int_71(void);
676 /** MODIFIES: phantom_machine_state */
677 void int_72(void);
678 /** MODIFIES: phantom_machine_state */
679 void int_73(void);
680 /** MODIFIES: phantom_machine_state */
681 void int_74(void);
682 /** MODIFIES: phantom_machine_state */
683 void int_75(void);
684 /** MODIFIES: phantom_machine_state */
685 void int_76(void);
686 /** MODIFIES: phantom_machine_state */
687 void int_77(void);
688 /** MODIFIES: phantom_machine_state */
689 void int_78(void);
690 /** MODIFIES: phantom_machine_state */
691 void int_79(void);
692 /** MODIFIES: phantom_machine_state */
693 void int_7a(void);
694 /** MODIFIES: phantom_machine_state */
695 void int_7b(void);
696 /** MODIFIES: phantom_machine_state */
697 void int_7c(void);
698 /** MODIFIES: phantom_machine_state */
699 void int_7d(void);
700 /** MODIFIES: phantom_machine_state */
701 void int_7e(void);
702 /** MODIFIES: phantom_machine_state */
703 void int_7f(void);
704 
705 /** MODIFIES: phantom_machine_state */
706 void int_80(void);
707 /** MODIFIES: phantom_machine_state */
708 void int_81(void);
709 /** MODIFIES: phantom_machine_state */
710 void int_82(void);
711 /** MODIFIES: phantom_machine_state */
712 void int_83(void);
713 /** MODIFIES: phantom_machine_state */
714 void int_84(void);
715 /** MODIFIES: phantom_machine_state */
716 void int_85(void);
717 /** MODIFIES: phantom_machine_state */
718 void int_86(void);
719 /** MODIFIES: phantom_machine_state */
720 void int_87(void);
721 /** MODIFIES: phantom_machine_state */
722 void int_88(void);
723 /** MODIFIES: phantom_machine_state */
724 void int_89(void);
725 /** MODIFIES: phantom_machine_state */
726 void int_8a(void);
727 /** MODIFIES: phantom_machine_state */
728 void int_8b(void);
729 /** MODIFIES: phantom_machine_state */
730 void int_8c(void);
731 /** MODIFIES: phantom_machine_state */
732 void int_8d(void);
733 /** MODIFIES: phantom_machine_state */
734 void int_8e(void);
735 /** MODIFIES: phantom_machine_state */
736 void int_8f(void);
737 
738 /** MODIFIES: phantom_machine_state */
739 void int_90(void);
740 /** MODIFIES: phantom_machine_state */
741 void int_91(void);
742 /** MODIFIES: phantom_machine_state */
743 void int_92(void);
744 /** MODIFIES: phantom_machine_state */
745 void int_93(void);
746 /** MODIFIES: phantom_machine_state */
747 void int_94(void);
748 /** MODIFIES: phantom_machine_state */
749 void int_95(void);
750 /** MODIFIES: phantom_machine_state */
751 void int_96(void);
752 /** MODIFIES: phantom_machine_state */
753 void int_97(void);
754 /** MODIFIES: phantom_machine_state */
755 void int_98(void);
756 /** MODIFIES: phantom_machine_state */
757 void int_99(void);
758 /** MODIFIES: phantom_machine_state */
759 void int_9a(void);
760 /** MODIFIES: phantom_machine_state */
761 void int_9b(void);
762 /** MODIFIES: phantom_machine_state */
763 void int_9c(void);
764 /** MODIFIES: phantom_machine_state */
765 void int_9d(void);
766 /** MODIFIES: phantom_machine_state */
767 void int_9e(void);
768 /** MODIFIES: phantom_machine_state */
769 void int_9f(void);
770 
771 /** MODIFIES: phantom_machine_state */
772 void int_a0(void);
773 /** MODIFIES: phantom_machine_state */
774 void int_a1(void);
775 /** MODIFIES: phantom_machine_state */
776 void int_a2(void);
777 /** MODIFIES: phantom_machine_state */
778 void int_a3(void);
779 /** MODIFIES: phantom_machine_state */
780 void int_a4(void);
781 /** MODIFIES: phantom_machine_state */
782 void int_a5(void);
783 /** MODIFIES: phantom_machine_state */
784 void int_a6(void);
785 /** MODIFIES: phantom_machine_state */
786 void int_a7(void);
787 /** MODIFIES: phantom_machine_state */
788 void int_a8(void);
789 /** MODIFIES: phantom_machine_state */
790 void int_a9(void);
791 /** MODIFIES: phantom_machine_state */
792 void int_aa(void);
793 /** MODIFIES: phantom_machine_state */
794 void int_ab(void);
795 /** MODIFIES: phantom_machine_state */
796 void int_ac(void);
797 /** MODIFIES: phantom_machine_state */
798 void int_ad(void);
799 /** MODIFIES: phantom_machine_state */
800 void int_ae(void);
801 /** MODIFIES: phantom_machine_state */
802 void int_af(void);
803 
804 /** MODIFIES: phantom_machine_state */
805 void int_b0(void);
806 /** MODIFIES: phantom_machine_state */
807 void int_b1(void);
808 /** MODIFIES: phantom_machine_state */
809 void int_b2(void);
810 /** MODIFIES: phantom_machine_state */
811 void int_b3(void);
812 /** MODIFIES: phantom_machine_state */
813 void int_b4(void);
814 /** MODIFIES: phantom_machine_state */
815 void int_b5(void);
816 /** MODIFIES: phantom_machine_state */
817 void int_b6(void);
818 /** MODIFIES: phantom_machine_state */
819 void int_b7(void);
820 /** MODIFIES: phantom_machine_state */
821 void int_b8(void);
822 /** MODIFIES: phantom_machine_state */
823 void int_b9(void);
824 /** MODIFIES: phantom_machine_state */
825 void int_ba(void);
826 /** MODIFIES: phantom_machine_state */
827 void int_bb(void);
828 /** MODIFIES: phantom_machine_state */
829 void int_bc(void);
830 /** MODIFIES: phantom_machine_state */
831 void int_bd(void);
832 /** MODIFIES: phantom_machine_state */
833 void int_be(void);
834 /** MODIFIES: phantom_machine_state */
835 void int_bf(void);
836 
837 /** MODIFIES: phantom_machine_state */
838 void int_c0(void);
839 /** MODIFIES: phantom_machine_state */
840 void int_c1(void);
841 /** MODIFIES: phantom_machine_state */
842 void int_c2(void);
843 /** MODIFIES: phantom_machine_state */
844 void int_c3(void);
845 /** MODIFIES: phantom_machine_state */
846 void int_c4(void);
847 /** MODIFIES: phantom_machine_state */
848 void int_c5(void);
849 /** MODIFIES: phantom_machine_state */
850 void int_c6(void);
851 /** MODIFIES: phantom_machine_state */
852 void int_c7(void);
853 /** MODIFIES: phantom_machine_state */
854 void int_c8(void);
855 /** MODIFIES: phantom_machine_state */
856 void int_c9(void);
857 /** MODIFIES: phantom_machine_state */
858 void int_ca(void);
859 /** MODIFIES: phantom_machine_state */
860 void int_cb(void);
861 /** MODIFIES: phantom_machine_state */
862 void int_cc(void);
863 /** MODIFIES: phantom_machine_state */
864 void int_cd(void);
865 /** MODIFIES: phantom_machine_state */
866 void int_ce(void);
867 /** MODIFIES: phantom_machine_state */
868 void int_cf(void);
869 
870 /** MODIFIES: phantom_machine_state */
871 void int_d0(void);
872 /** MODIFIES: phantom_machine_state */
873 void int_d1(void);
874 /** MODIFIES: phantom_machine_state */
875 void int_d2(void);
876 /** MODIFIES: phantom_machine_state */
877 void int_d3(void);
878 /** MODIFIES: phantom_machine_state */
879 void int_d4(void);
880 /** MODIFIES: phantom_machine_state */
881 void int_d5(void);
882 /** MODIFIES: phantom_machine_state */
883 void int_d6(void);
884 /** MODIFIES: phantom_machine_state */
885 void int_d7(void);
886 /** MODIFIES: phantom_machine_state */
887 void int_d8(void);
888 /** MODIFIES: phantom_machine_state */
889 void int_d9(void);
890 /** MODIFIES: phantom_machine_state */
891 void int_da(void);
892 /** MODIFIES: phantom_machine_state */
893 void int_db(void);
894 /** MODIFIES: phantom_machine_state */
895 void int_dc(void);
896 /** MODIFIES: phantom_machine_state */
897 void int_dd(void);
898 /** MODIFIES: phantom_machine_state */
899 void int_de(void);
900 /** MODIFIES: phantom_machine_state */
901 void int_df(void);
902 
903 /** MODIFIES: phantom_machine_state */
904 void int_e0(void);
905 /** MODIFIES: phantom_machine_state */
906 void int_e1(void);
907 /** MODIFIES: phantom_machine_state */
908 void int_e2(void);
909 /** MODIFIES: phantom_machine_state */
910 void int_e3(void);
911 /** MODIFIES: phantom_machine_state */
912 void int_e4(void);
913 /** MODIFIES: phantom_machine_state */
914 void int_e5(void);
915 /** MODIFIES: phantom_machine_state */
916 void int_e6(void);
917 /** MODIFIES: phantom_machine_state */
918 void int_e7(void);
919 /** MODIFIES: phantom_machine_state */
920 void int_e8(void);
921 /** MODIFIES: phantom_machine_state */
922 void int_e9(void);
923 /** MODIFIES: phantom_machine_state */
924 void int_ea(void);
925 /** MODIFIES: phantom_machine_state */
926 void int_eb(void);
927 /** MODIFIES: phantom_machine_state */
928 void int_ec(void);
929 /** MODIFIES: phantom_machine_state */
930 void int_ed(void);
931 /** MODIFIES: phantom_machine_state */
932 void int_ee(void);
933 /** MODIFIES: phantom_machine_state */
934 void int_ef(void);
935 
936 /** MODIFIES: phantom_machine_state */
937 void int_f0(void);
938 /** MODIFIES: phantom_machine_state */
939 void int_f1(void);
940 /** MODIFIES: phantom_machine_state */
941 void int_f2(void);
942 /** MODIFIES: phantom_machine_state */
943 void int_f3(void);
944 /** MODIFIES: phantom_machine_state */
945 void int_f4(void);
946 /** MODIFIES: phantom_machine_state */
947 void int_f5(void);
948 /** MODIFIES: phantom_machine_state */
949 void int_f6(void);
950 /** MODIFIES: phantom_machine_state */
951 void int_f7(void);
952 /** MODIFIES: phantom_machine_state */
953 void int_f8(void);
954 /** MODIFIES: phantom_machine_state */
955 void int_f9(void);
956 /** MODIFIES: phantom_machine_state */
957 void int_fa(void);
958 /** MODIFIES: phantom_machine_state */
959 void int_fb(void);
960 /** MODIFIES: phantom_machine_state */
961 void int_fc(void);
962 /** MODIFIES: phantom_machine_state */
963 void int_fd(void);
964 /** MODIFIES: phantom_machine_state */
965 void int_fe(void);
966 /** MODIFIES: phantom_machine_state */
967 void int_ff(void);
968 
969 #ifdef CONFIG_VTX
970 void handle_vmexit(void);
971 #endif
972 
973