1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
3 
4 #ifndef _ICE_TXRX_H_
5 #define _ICE_TXRX_H_
6 
7 #include "ice_type.h"
8 
9 #define ICE_DFLT_IRQ_WORK	256
10 #define ICE_RXBUF_3072		3072
11 #define ICE_RXBUF_2048		2048
12 #define ICE_RXBUF_1664		1664
13 #define ICE_RXBUF_1536		1536
14 #define ICE_MAX_CHAINED_RX_BUFS	5
15 #define ICE_MAX_BUF_TXD		8
16 #define ICE_MIN_TX_LEN		17
17 #define ICE_MAX_FRAME_LEGACY_RX 8320
18 
19 /* The size limit for a transmit buffer in a descriptor is (16K - 1).
20  * In order to align with the read requests we will align the value to
21  * the nearest 4K which represents our maximum read request size.
22  */
23 #define ICE_MAX_READ_REQ_SIZE	4096
24 #define ICE_MAX_DATA_PER_TXD	(16 * 1024 - 1)
25 #define ICE_MAX_DATA_PER_TXD_ALIGNED \
26 	(~(ICE_MAX_READ_REQ_SIZE - 1) & ICE_MAX_DATA_PER_TXD)
27 
28 #define ICE_MAX_TXQ_PER_TXQG	128
29 
30 /* Attempt to maximize the headroom available for incoming frames. We use a 2K
31  * buffer for MTUs <= 1500 and need 1536/1534 to store the data for the frame.
32  * This leaves us with 512 bytes of room.  From that we need to deduct the
33  * space needed for the shared info and the padding needed to IP align the
34  * frame.
35  *
36  * Note: For cache line sizes 256 or larger this value is going to end
37  *	 up negative.  In these cases we should fall back to the legacy
38  *	 receive path.
39  */
40 #if (PAGE_SIZE < 8192)
41 #define ICE_2K_TOO_SMALL_WITH_PADDING \
42 	((unsigned int)(NET_SKB_PAD + ICE_RXBUF_1536) > \
43 			SKB_WITH_OVERHEAD(ICE_RXBUF_2048))
44 
45 /**
46  * ice_compute_pad - compute the padding
47  * @rx_buf_len: buffer length
48  *
49  * Figure out the size of half page based on given buffer length and
50  * then subtract the skb_shared_info followed by subtraction of the
51  * actual buffer length; this in turn results in the actual space that
52  * is left for padding usage
53  */
ice_compute_pad(int rx_buf_len)54 static inline int ice_compute_pad(int rx_buf_len)
55 {
56 	int half_page_size;
57 
58 	half_page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2);
59 	return SKB_WITH_OVERHEAD(half_page_size) - rx_buf_len;
60 }
61 
62 /**
63  * ice_skb_pad - determine the padding that we can supply
64  *
65  * Figure out the right Rx buffer size and based on that calculate the
66  * padding
67  */
ice_skb_pad(void)68 static inline int ice_skb_pad(void)
69 {
70 	int rx_buf_len;
71 
72 	/* If a 2K buffer cannot handle a standard Ethernet frame then
73 	 * optimize padding for a 3K buffer instead of a 1.5K buffer.
74 	 *
75 	 * For a 3K buffer we need to add enough padding to allow for
76 	 * tailroom due to NET_IP_ALIGN possibly shifting us out of
77 	 * cache-line alignment.
78 	 */
79 	if (ICE_2K_TOO_SMALL_WITH_PADDING)
80 		rx_buf_len = ICE_RXBUF_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN);
81 	else
82 		rx_buf_len = ICE_RXBUF_1536;
83 
84 	/* if needed make room for NET_IP_ALIGN */
85 	rx_buf_len -= NET_IP_ALIGN;
86 
87 	return ice_compute_pad(rx_buf_len);
88 }
89 
90 #define ICE_SKB_PAD ice_skb_pad()
91 #else
92 #define ICE_2K_TOO_SMALL_WITH_PADDING false
93 #define ICE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
94 #endif
95 
96 /* We are assuming that the cache line is always 64 Bytes here for ice.
97  * In order to make sure that is a correct assumption there is a check in probe
98  * to print a warning if the read from GLPCI_CNF2 tells us that the cache line
99  * size is 128 bytes. We do it this way because we do not want to read the
100  * GLPCI_CNF2 register or a variable containing the value on every pass through
101  * the Tx path.
102  */
103 #define ICE_CACHE_LINE_BYTES		64
104 #define ICE_DESCS_PER_CACHE_LINE	(ICE_CACHE_LINE_BYTES / \
105 					 sizeof(struct ice_tx_desc))
106 #define ICE_DESCS_FOR_CTX_DESC		1
107 #define ICE_DESCS_FOR_SKB_DATA_PTR	1
108 /* Tx descriptors needed, worst case */
109 #define DESC_NEEDED (MAX_SKB_FRAGS + ICE_DESCS_FOR_CTX_DESC + \
110 		     ICE_DESCS_PER_CACHE_LINE + ICE_DESCS_FOR_SKB_DATA_PTR)
111 #define ICE_DESC_UNUSED(R)	\
112 	(u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
113 	      (R)->next_to_clean - (R)->next_to_use - 1)
114 
115 #define ICE_RX_DESC_UNUSED(R)	\
116 	((((R)->first_desc > (R)->next_to_use) ? 0 : (R)->count) + \
117 	      (R)->first_desc - (R)->next_to_use - 1)
118 
119 #define ICE_RING_QUARTER(R) ((R)->count >> 2)
120 
121 #define ICE_TX_FLAGS_TSO	BIT(0)
122 #define ICE_TX_FLAGS_HW_VLAN	BIT(1)
123 #define ICE_TX_FLAGS_SW_VLAN	BIT(2)
124 /* Free, was ICE_TX_FLAGS_DUMMY_PKT */
125 #define ICE_TX_FLAGS_TSYN	BIT(4)
126 #define ICE_TX_FLAGS_IPV4	BIT(5)
127 #define ICE_TX_FLAGS_IPV6	BIT(6)
128 #define ICE_TX_FLAGS_TUNNEL	BIT(7)
129 #define ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN	BIT(8)
130 #define ICE_TX_FLAGS_VLAN_M	0xffff0000
131 #define ICE_TX_FLAGS_VLAN_PR_M	0xe0000000
132 #define ICE_TX_FLAGS_VLAN_PR_S	29
133 #define ICE_TX_FLAGS_VLAN_S	16
134 
135 #define ICE_XDP_PASS		0
136 #define ICE_XDP_CONSUMED	BIT(0)
137 #define ICE_XDP_TX		BIT(1)
138 #define ICE_XDP_REDIR		BIT(2)
139 #define ICE_XDP_EXIT		BIT(3)
140 #define ICE_SKB_CONSUMED	ICE_XDP_CONSUMED
141 
142 #define ICE_RX_DMA_ATTR \
143 	(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
144 
145 #define ICE_ETH_PKT_HDR_PAD	(ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))
146 
147 #define ICE_TXD_LAST_DESC_CMD (ICE_TX_DESC_CMD_EOP | ICE_TX_DESC_CMD_RS)
148 
149 /**
150  * enum ice_tx_buf_type - type of &ice_tx_buf to act on Tx completion
151  * @ICE_TX_BUF_EMPTY: unused OR XSk frame, no action required
152  * @ICE_TX_BUF_DUMMY: dummy Flow Director packet, unmap and kfree()
153  * @ICE_TX_BUF_FRAG: mapped skb OR &xdp_buff frag, only unmap DMA
154  * @ICE_TX_BUF_SKB: &sk_buff, unmap and consume_skb(), update stats
155  * @ICE_TX_BUF_XDP_TX: &xdp_buff, unmap and page_frag_free(), stats
156  * @ICE_TX_BUF_XDP_XMIT: &xdp_frame, unmap and xdp_return_frame(), stats
157  * @ICE_TX_BUF_XSK_TX: &xdp_buff on XSk queue, xsk_buff_free(), stats
158  */
159 enum ice_tx_buf_type {
160 	ICE_TX_BUF_EMPTY	= 0U,
161 	ICE_TX_BUF_DUMMY,
162 	ICE_TX_BUF_FRAG,
163 	ICE_TX_BUF_SKB,
164 	ICE_TX_BUF_XDP_TX,
165 	ICE_TX_BUF_XDP_XMIT,
166 	ICE_TX_BUF_XSK_TX,
167 };
168 
169 struct ice_tx_buf {
170 	union {
171 		struct ice_tx_desc *next_to_watch;
172 		u32 rs_idx;
173 	};
174 	union {
175 		void *raw_buf;		/* used for XDP_TX and FDir rules */
176 		struct sk_buff *skb;	/* used for .ndo_start_xmit() */
177 		struct xdp_frame *xdpf;	/* used for .ndo_xdp_xmit() */
178 		struct xdp_buff *xdp;	/* used for XDP_TX ZC */
179 	};
180 	unsigned int bytecount;
181 	union {
182 		unsigned int gso_segs;
183 		unsigned int nr_frags;	/* used for mbuf XDP */
184 	};
185 	u32 type:16;			/* &ice_tx_buf_type */
186 	u32 tx_flags:16;
187 	DEFINE_DMA_UNMAP_LEN(len);
188 	DEFINE_DMA_UNMAP_ADDR(dma);
189 };
190 
191 struct ice_tx_offload_params {
192 	u64 cd_qw1;
193 	struct ice_tx_ring *tx_ring;
194 	u32 td_cmd;
195 	u32 td_offset;
196 	u32 td_l2tag1;
197 	u32 cd_tunnel_params;
198 	u16 cd_l2tag2;
199 	u8 header_len;
200 };
201 
202 struct ice_rx_buf {
203 	dma_addr_t dma;
204 	struct page *page;
205 	unsigned int page_offset;
206 	unsigned int pgcnt;
207 	unsigned int act;
208 	unsigned int pagecnt_bias;
209 };
210 
211 struct ice_q_stats {
212 	u64 pkts;
213 	u64 bytes;
214 };
215 
216 struct ice_txq_stats {
217 	u64 restart_q;
218 	u64 tx_busy;
219 	u64 tx_linearize;
220 	int prev_pkt; /* negative if no pending Tx descriptors */
221 };
222 
223 struct ice_rxq_stats {
224 	u64 non_eop_descs;
225 	u64 alloc_page_failed;
226 	u64 alloc_buf_failed;
227 };
228 
229 struct ice_ring_stats {
230 	struct rcu_head rcu;	/* to avoid race on free */
231 	struct ice_q_stats stats;
232 	struct u64_stats_sync syncp;
233 	union {
234 		struct ice_txq_stats tx_stats;
235 		struct ice_rxq_stats rx_stats;
236 	};
237 };
238 
239 enum ice_ring_state_t {
240 	ICE_TX_XPS_INIT_DONE,
241 	ICE_TX_NBITS,
242 };
243 
244 /* this enum matches hardware bits and is meant to be used by DYN_CTLN
245  * registers and QINT registers or more generally anywhere in the manual
246  * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
247  * register but instead is a special value meaning "don't update" ITR0/1/2.
248  */
249 enum ice_dyn_idx_t {
250 	ICE_IDX_ITR0 = 0,
251 	ICE_IDX_ITR1 = 1,
252 	ICE_IDX_ITR2 = 2,
253 	ICE_ITR_NONE = 3	/* ITR_NONE must not be used as an index */
254 };
255 
256 /* Header split modes defined by DTYPE field of Rx RLAN context */
257 enum ice_rx_dtype {
258 	ICE_RX_DTYPE_NO_SPLIT		= 0,
259 	ICE_RX_DTYPE_HEADER_SPLIT	= 1,
260 	ICE_RX_DTYPE_SPLIT_ALWAYS	= 2,
261 };
262 
263 /* indices into GLINT_ITR registers */
264 #define ICE_RX_ITR	ICE_IDX_ITR0
265 #define ICE_TX_ITR	ICE_IDX_ITR1
266 #define ICE_ITR_8K	124
267 #define ICE_ITR_20K	50
268 #define ICE_ITR_MAX	8160 /* 0x1FE0 */
269 #define ICE_DFLT_TX_ITR	ICE_ITR_20K
270 #define ICE_DFLT_RX_ITR	ICE_ITR_20K
271 enum ice_dynamic_itr {
272 	ITR_STATIC = 0,
273 	ITR_DYNAMIC = 1
274 };
275 
276 #define ITR_IS_DYNAMIC(rc) ((rc)->itr_mode == ITR_DYNAMIC)
277 #define ICE_ITR_GRAN_S		1	/* ITR granularity is always 2us */
278 #define ICE_ITR_GRAN_US		BIT(ICE_ITR_GRAN_S)
279 #define ICE_ITR_MASK		0x1FFE	/* ITR register value alignment mask */
280 #define ITR_REG_ALIGN(setting)	((setting) & ICE_ITR_MASK)
281 
282 #define ICE_DFLT_INTRL	0
283 #define ICE_MAX_INTRL	236
284 
285 #define ICE_IN_WB_ON_ITR_MODE	255
286 /* Sets WB_ON_ITR and assumes INTENA bit is already cleared, which allows
287  * setting the MSK_M bit to tell hardware to ignore the INTENA_M bit. Also,
288  * set the write-back latency to the usecs passed in.
289  */
290 #define ICE_GLINT_DYN_CTL_WB_ON_ITR(usecs, itr_idx)	\
291 	((((usecs) << (GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S)) & \
292 	  GLINT_DYN_CTL_INTERVAL_M) | \
293 	 (((itr_idx) << GLINT_DYN_CTL_ITR_INDX_S) & \
294 	  GLINT_DYN_CTL_ITR_INDX_M) | GLINT_DYN_CTL_INTENA_MSK_M | \
295 	 GLINT_DYN_CTL_WB_ON_ITR_M)
296 
297 /* Legacy or Advanced Mode Queue */
298 #define ICE_TX_ADVANCED	0
299 #define ICE_TX_LEGACY	1
300 
301 /* descriptor ring, associated with a VSI */
302 struct ice_rx_ring {
303 	/* CL1 - 1st cacheline starts here */
304 	struct ice_rx_ring *next;	/* pointer to next ring in q_vector */
305 	void *desc;			/* Descriptor ring memory */
306 	struct device *dev;		/* Used for DMA mapping */
307 	struct net_device *netdev;	/* netdev ring maps to */
308 	struct ice_vsi *vsi;		/* Backreference to associated VSI */
309 	struct ice_q_vector *q_vector;	/* Backreference to associated vector */
310 	u8 __iomem *tail;
311 	u16 q_index;			/* Queue number of ring */
312 
313 	u16 count;			/* Number of descriptors */
314 	u16 reg_idx;			/* HW register index of the ring */
315 	u16 next_to_alloc;
316 	/* CL2 - 2nd cacheline starts here */
317 	union {
318 		struct ice_rx_buf *rx_buf;
319 		struct xdp_buff **xdp_buf;
320 	};
321 	struct xdp_buff xdp;
322 	/* CL3 - 3rd cacheline starts here */
323 	struct bpf_prog *xdp_prog;
324 	u16 rx_offset;
325 
326 	/* used in interrupt processing */
327 	u16 next_to_use;
328 	u16 next_to_clean;
329 	u16 first_desc;
330 
331 	/* stats structs */
332 	struct ice_ring_stats *ring_stats;
333 
334 	struct rcu_head rcu;		/* to avoid race on free */
335 	/* CL4 - 4th cacheline starts here */
336 	struct ice_channel *ch;
337 	struct ice_tx_ring *xdp_ring;
338 	struct xsk_buff_pool *xsk_pool;
339 	dma_addr_t dma;			/* physical address of ring */
340 	u64 cached_phctime;
341 	u16 rx_buf_len;
342 	u8 dcb_tc;			/* Traffic class of ring */
343 	u8 ptp_rx;
344 #define ICE_RX_FLAGS_RING_BUILD_SKB	BIT(1)
345 #define ICE_RX_FLAGS_CRC_STRIP_DIS	BIT(2)
346 	u8 flags;
347 	/* CL5 - 5th cacheline starts here */
348 	struct xdp_rxq_info xdp_rxq;
349 } ____cacheline_internodealigned_in_smp;
350 
351 struct ice_tx_ring {
352 	/* CL1 - 1st cacheline starts here */
353 	struct ice_tx_ring *next;	/* pointer to next ring in q_vector */
354 	void *desc;			/* Descriptor ring memory */
355 	struct device *dev;		/* Used for DMA mapping */
356 	u8 __iomem *tail;
357 	struct ice_tx_buf *tx_buf;
358 	struct ice_q_vector *q_vector;	/* Backreference to associated vector */
359 	struct net_device *netdev;	/* netdev ring maps to */
360 	struct ice_vsi *vsi;		/* Backreference to associated VSI */
361 	/* CL2 - 2nd cacheline starts here */
362 	dma_addr_t dma;			/* physical address of ring */
363 	struct xsk_buff_pool *xsk_pool;
364 	u16 next_to_use;
365 	u16 next_to_clean;
366 	u16 q_handle;			/* Queue handle per TC */
367 	u16 reg_idx;			/* HW register index of the ring */
368 	u16 count;			/* Number of descriptors */
369 	u16 q_index;			/* Queue number of ring */
370 	u16 xdp_tx_active;
371 	/* stats structs */
372 	struct ice_ring_stats *ring_stats;
373 	/* CL3 - 3rd cacheline starts here */
374 	struct rcu_head rcu;		/* to avoid race on free */
375 	DECLARE_BITMAP(xps_state, ICE_TX_NBITS);	/* XPS Config State */
376 	struct ice_channel *ch;
377 	struct ice_ptp_tx *tx_tstamps;
378 	spinlock_t tx_lock;
379 	u32 txq_teid;			/* Added Tx queue TEID */
380 	/* CL4 - 4th cacheline starts here */
381 #define ICE_TX_FLAGS_RING_XDP		BIT(0)
382 #define ICE_TX_FLAGS_RING_VLAN_L2TAG1	BIT(1)
383 #define ICE_TX_FLAGS_RING_VLAN_L2TAG2	BIT(2)
384 	u8 flags;
385 	u8 dcb_tc;			/* Traffic class of ring */
386 	u8 ptp_tx;
387 } ____cacheline_internodealigned_in_smp;
388 
ice_ring_uses_build_skb(struct ice_rx_ring * ring)389 static inline bool ice_ring_uses_build_skb(struct ice_rx_ring *ring)
390 {
391 	return !!(ring->flags & ICE_RX_FLAGS_RING_BUILD_SKB);
392 }
393 
ice_set_ring_build_skb_ena(struct ice_rx_ring * ring)394 static inline void ice_set_ring_build_skb_ena(struct ice_rx_ring *ring)
395 {
396 	ring->flags |= ICE_RX_FLAGS_RING_BUILD_SKB;
397 }
398 
ice_clear_ring_build_skb_ena(struct ice_rx_ring * ring)399 static inline void ice_clear_ring_build_skb_ena(struct ice_rx_ring *ring)
400 {
401 	ring->flags &= ~ICE_RX_FLAGS_RING_BUILD_SKB;
402 }
403 
ice_ring_ch_enabled(struct ice_tx_ring * ring)404 static inline bool ice_ring_ch_enabled(struct ice_tx_ring *ring)
405 {
406 	return !!ring->ch;
407 }
408 
ice_ring_is_xdp(struct ice_tx_ring * ring)409 static inline bool ice_ring_is_xdp(struct ice_tx_ring *ring)
410 {
411 	return !!(ring->flags & ICE_TX_FLAGS_RING_XDP);
412 }
413 
414 enum ice_container_type {
415 	ICE_RX_CONTAINER,
416 	ICE_TX_CONTAINER,
417 };
418 
419 struct ice_ring_container {
420 	/* head of linked-list of rings */
421 	union {
422 		struct ice_rx_ring *rx_ring;
423 		struct ice_tx_ring *tx_ring;
424 	};
425 	struct dim dim;		/* data for net_dim algorithm */
426 	u16 itr_idx;		/* index in the interrupt vector */
427 	/* this matches the maximum number of ITR bits, but in usec
428 	 * values, so it is shifted left one bit (bit zero is ignored)
429 	 */
430 	union {
431 		struct {
432 			u16 itr_setting:13;
433 			u16 itr_reserved:2;
434 			u16 itr_mode:1;
435 		};
436 		u16 itr_settings;
437 	};
438 	enum ice_container_type type;
439 };
440 
441 struct ice_coalesce_stored {
442 	u16 itr_tx;
443 	u16 itr_rx;
444 	u8 intrl;
445 	u8 tx_valid;
446 	u8 rx_valid;
447 };
448 
449 /* iterator for handling rings in ring container */
450 #define ice_for_each_rx_ring(pos, head) \
451 	for (pos = (head).rx_ring; pos; pos = pos->next)
452 
453 #define ice_for_each_tx_ring(pos, head) \
454 	for (pos = (head).tx_ring; pos; pos = pos->next)
455 
ice_rx_pg_order(struct ice_rx_ring * ring)456 static inline unsigned int ice_rx_pg_order(struct ice_rx_ring *ring)
457 {
458 #if (PAGE_SIZE < 8192)
459 	if (ring->rx_buf_len > (PAGE_SIZE / 2))
460 		return 1;
461 #endif
462 	return 0;
463 }
464 
465 #define ice_rx_pg_size(_ring) (PAGE_SIZE << ice_rx_pg_order(_ring))
466 
467 union ice_32b_rx_flex_desc;
468 
469 bool ice_alloc_rx_bufs(struct ice_rx_ring *rxr, unsigned int cleaned_count);
470 netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev);
471 u16
472 ice_select_queue(struct net_device *dev, struct sk_buff *skb,
473 		 struct net_device *sb_dev);
474 void ice_clean_tx_ring(struct ice_tx_ring *tx_ring);
475 void ice_clean_rx_ring(struct ice_rx_ring *rx_ring);
476 int ice_setup_tx_ring(struct ice_tx_ring *tx_ring);
477 int ice_setup_rx_ring(struct ice_rx_ring *rx_ring);
478 void ice_free_tx_ring(struct ice_tx_ring *tx_ring);
479 void ice_free_rx_ring(struct ice_rx_ring *rx_ring);
480 int ice_napi_poll(struct napi_struct *napi, int budget);
481 int
482 ice_prgm_fdir_fltr(struct ice_vsi *vsi, struct ice_fltr_desc *fdir_desc,
483 		   u8 *raw_packet);
484 int ice_clean_rx_irq(struct ice_rx_ring *rx_ring, int budget);
485 void ice_clean_ctrl_tx_irq(struct ice_tx_ring *tx_ring);
486 #endif /* _ICE_TXRX_H_ */
487