1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __MACH_IMX_CLK_H
3 #define __MACH_IMX_CLK_H
4
5 #include <linux/bits.h>
6 #include <linux/spinlock.h>
7 #include <linux/clk-provider.h>
8
9 extern spinlock_t imx_ccm_lock;
10 extern bool mcore_booted;
11
12 void imx_check_clocks(struct clk *clks[], unsigned int count);
13 void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
14 #ifndef MODULE
15 void imx_register_uart_clocks(void);
16 #else
imx_register_uart_clocks(void)17 static inline void imx_register_uart_clocks(void)
18 {
19 }
20 #endif
21 void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);
22 void imx_unregister_clocks(struct clk *clks[], unsigned int count);
23 void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count);
24
25 extern void imx_cscmr1_fixup(u32 *val);
26
27 enum imx_pllv1_type {
28 IMX_PLLV1_IMX1,
29 IMX_PLLV1_IMX21,
30 IMX_PLLV1_IMX25,
31 IMX_PLLV1_IMX27,
32 IMX_PLLV1_IMX31,
33 IMX_PLLV1_IMX35,
34 };
35
36 enum imx_sscg_pll_type {
37 SCCG_PLL1,
38 SCCG_PLL2,
39 };
40
41 enum imx_pll14xx_type {
42 PLL_1416X,
43 PLL_1443X,
44 };
45
46 enum imx_pllv4_type {
47 IMX_PLLV4_IMX7ULP,
48 IMX_PLLV4_IMX8ULP,
49 };
50
51 enum imx_pfdv2_type {
52 IMX_PFDV2_IMX7ULP,
53 IMX_PFDV2_IMX8ULP,
54 };
55
56 /* NOTE: Rate table should be kept sorted in descending order. */
57 struct imx_pll14xx_rate_table {
58 unsigned int rate;
59 unsigned int pdiv;
60 unsigned int mdiv;
61 unsigned int sdiv;
62 unsigned int kdiv;
63 };
64
65 struct imx_pll14xx_clk {
66 enum imx_pll14xx_type type;
67 const struct imx_pll14xx_rate_table *rate_table;
68 int rate_count;
69 int flags;
70 };
71
72 extern struct imx_pll14xx_clk imx_1416x_pll;
73 extern struct imx_pll14xx_clk imx_1443x_pll;
74 extern struct imx_pll14xx_clk imx_1443x_dram_pll;
75
76 /* NOTE: Rate table should be kept sorted in descending order. */
77 struct imx_fracn_gppll_rate_table {
78 unsigned int rate;
79 unsigned int mfi;
80 unsigned int mfn;
81 unsigned int mfd;
82 unsigned int rdiv;
83 unsigned int odiv;
84 };
85
86 struct imx_fracn_gppll_clk {
87 const struct imx_fracn_gppll_rate_table *rate_table;
88 int rate_count;
89 int flags;
90 };
91
92 struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base,
93 const struct imx_fracn_gppll_clk *pll_clk);
94
95 extern struct imx_fracn_gppll_clk imx_fracn_gppll;
96
97 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
98 to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
99
100 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
101 cgr_val, cgr_mask, clk_gate_flags, lock, share_count) \
102 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
103 cgr_val, cgr_mask, clk_gate_flags, lock, share_count))
104
105 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \
106 to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
107
108 #define imx_clk_pfd(name, parent_name, reg, idx) \
109 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
110
111 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
112 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
113
114 #define imx_clk_fixed(name, rate) \
115 to_clk(imx_clk_hw_fixed(name, rate))
116
117 #define imx_clk_fixed_factor(name, parent, mult, div) \
118 to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
119
120 #define imx_clk_divider(name, parent, reg, shift, width) \
121 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
122
123 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \
124 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
125
126 #define imx_clk_gate(name, parent, reg, shift) \
127 to_clk(imx_clk_hw_gate(name, parent, reg, shift))
128
129 #define imx_clk_gate_dis(name, parent, reg, shift) \
130 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
131
132 #define imx_clk_gate2(name, parent, reg, shift) \
133 to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
134
135 #define imx_clk_gate2_cgr(name, parent, reg, shift, cgr_val) \
136 to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL))
137
138 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
139 to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
140
141 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \
142 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
143
144 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \
145 to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
146
147 #define imx_clk_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \
148 to_clk(imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags))
149
150 #define imx_clk_pllv1(type, name, parent, base) \
151 to_clk(imx_clk_hw_pllv1(type, name, parent, base))
152
153 #define imx_clk_pllv2(name, parent, base) \
154 to_clk(imx_clk_hw_pllv2(name, parent, base))
155
156 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \
157 to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
158
159 #define imx_clk_hw_gate(name, parent, reg, shift) \
160 imx_clk_hw_gate_flags(name, parent, reg, shift, 0)
161
162 #define imx_clk_hw_gate2(name, parent, reg, shift) \
163 imx_clk_hw_gate2_flags(name, parent, reg, shift, 0)
164
165 #define imx_clk_hw_gate_dis(name, parent, reg, shift) \
166 imx_clk_hw_gate_dis_flags(name, parent, reg, shift, 0)
167
168 #define imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags) \
169 __imx_clk_hw_gate(name, parent, reg, shift, flags, CLK_GATE_SET_TO_DISABLE)
170
171 #define imx_clk_hw_gate_flags(name, parent, reg, shift, flags) \
172 __imx_clk_hw_gate(name, parent, reg, shift, flags, 0)
173
174 #define imx_clk_hw_gate2_flags(name, parent, reg, shift, flags) \
175 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, flags, NULL)
176
177 #define imx_clk_hw_gate2_shared(name, parent, reg, shift, shared_count) \
178 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, 0, shared_count)
179
180 #define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) \
181 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE, shared_count)
182
183 #define imx_clk_hw_gate3(name, parent, reg, shift) \
184 imx_clk_hw_gate3_flags(name, parent, reg, shift, 0)
185
186 #define imx_clk_hw_gate3_flags(name, parent, reg, shift, flags) \
187 __imx_clk_hw_gate(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE, 0)
188
189 #define imx_clk_hw_gate4(name, parent, reg, shift) \
190 imx_clk_hw_gate4_flags(name, parent, reg, shift, 0)
191
192 #define imx_clk_hw_gate4_flags(name, parent, reg, shift, flags) \
193 imx_clk_hw_gate2_flags(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE)
194
195 #define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \
196 imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, 0)
197
198 #define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \
199 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, 0, 0)
200
201 #define imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags) \
202 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags, 0)
203
204 #define imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents) \
205 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT, CLK_MUX_READ_ONLY)
206
207 #define imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \
208 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags | CLK_OPS_PARENT_ENABLE, 0)
209
210 #define imx_clk_hw_divider(name, parent, reg, shift, width) \
211 __imx_clk_hw_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT)
212
213 #define imx_clk_hw_divider2(name, parent, reg, shift, width) \
214 __imx_clk_hw_divider(name, parent, reg, shift, width, \
215 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE)
216
217 #define imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags) \
218 __imx_clk_hw_divider(name, parent, reg, shift, width, flags)
219
220 #define imx_clk_hw_pll14xx(name, parent_name, base, pll_clk) \
221 imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk)
222
223 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
224 const char *parent_name, void __iomem *base,
225 const struct imx_pll14xx_clk *pll_clk);
226
227 struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,
228 const char *parent, void __iomem *base);
229
230 struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
231 void __iomem *base);
232
233 struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
234 void __iomem *base);
235
236 struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
237 const char * const *parent_names,
238 u8 num_parents,
239 u8 parent, u8 bypass1, u8 bypass2,
240 void __iomem *base,
241 unsigned long flags);
242
243 enum imx_pllv3_type {
244 IMX_PLLV3_GENERIC,
245 IMX_PLLV3_SYS,
246 IMX_PLLV3_USB,
247 IMX_PLLV3_USB_VF610,
248 IMX_PLLV3_AV,
249 IMX_PLLV3_ENET,
250 IMX_PLLV3_ENET_IMX7,
251 IMX_PLLV3_SYS_VF610,
252 IMX_PLLV3_DDR_IMX7,
253 IMX_PLLV3_AV_IMX7,
254 };
255
256 struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
257 const char *parent_name, void __iomem *base, u32 div_mask);
258
259 #define PLL_1416X_RATE(_rate, _m, _p, _s) \
260 { \
261 .rate = (_rate), \
262 .mdiv = (_m), \
263 .pdiv = (_p), \
264 .sdiv = (_s), \
265 }
266
267 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
268 { \
269 .rate = (_rate), \
270 .mdiv = (_m), \
271 .pdiv = (_p), \
272 .sdiv = (_s), \
273 .kdiv = (_k), \
274 }
275
276 struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name,
277 const char *parent_name, void __iomem *base);
278
279 struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
280 const char *parent_name, unsigned long flags,
281 void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask,
282 u8 clk_gate_flags, spinlock_t *lock,
283 unsigned int *share_count);
284
285 struct clk * imx_obtain_fixed_clock(
286 const char *name, unsigned long rate);
287
288 struct clk_hw *imx_obtain_fixed_clock_hw(
289 const char *name, unsigned long rate);
290
291 struct clk_hw *imx_obtain_fixed_of_clock(struct device_node *np,
292 const char *name, unsigned long rate);
293
294 struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name);
295
296 struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
297 void __iomem *reg, u8 shift, u32 exclusive_mask);
298
299 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
300 void __iomem *reg, u8 idx);
301
302 struct clk_hw *imx_clk_hw_pfdv2(enum imx_pfdv2_type type, const char *name,
303 const char *parent_name, void __iomem *reg, u8 idx);
304
305 struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
306 void __iomem *reg, u8 shift, u8 width,
307 void __iomem *busy_reg, u8 busy_shift);
308
309 struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift,
310 u8 width, void __iomem *busy_reg, u8 busy_shift,
311 const char * const *parent_names, int num_parents);
312
313 struct clk_hw *imx7ulp_clk_hw_composite(const char *name,
314 const char * const *parent_names,
315 int num_parents, bool mux_present,
316 bool rate_present, bool gate_present,
317 void __iomem *reg);
318
319 struct clk_hw *imx8ulp_clk_hw_composite(const char *name,
320 const char * const *parent_names,
321 int num_parents, bool mux_present,
322 bool rate_present, bool gate_present,
323 void __iomem *reg, bool has_swrst);
324
325 struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent,
326 void __iomem *reg, u8 shift, u8 width,
327 void (*fixup)(u32 *val));
328
329 struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,
330 u8 shift, u8 width, const char * const *parents,
331 int num_parents, void (*fixup)(u32 *val));
332
to_clk(struct clk_hw * hw)333 static inline struct clk *to_clk(struct clk_hw *hw)
334 {
335 if (IS_ERR_OR_NULL(hw))
336 return ERR_CAST(hw);
337 return hw->clk;
338 }
339
imx_clk_hw_fixed(const char * name,int rate)340 static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)
341 {
342 return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
343 }
344
imx_clk_hw_fixed_factor(const char * name,const char * parent,unsigned int mult,unsigned int div)345 static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name,
346 const char *parent, unsigned int mult, unsigned int div)
347 {
348 return clk_hw_register_fixed_factor(NULL, name, parent,
349 CLK_SET_RATE_PARENT, mult, div);
350 }
351
__imx_clk_hw_divider(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 width,unsigned long flags)352 static inline struct clk_hw *__imx_clk_hw_divider(const char *name,
353 const char *parent,
354 void __iomem *reg, u8 shift,
355 u8 width, unsigned long flags)
356 {
357 return clk_hw_register_divider(NULL, name, parent, flags,
358 reg, shift, width, 0, &imx_ccm_lock);
359 }
360
__imx_clk_hw_gate(const char * name,const char * parent,void __iomem * reg,u8 shift,unsigned long flags,unsigned long clk_gate_flags)361 static inline struct clk_hw *__imx_clk_hw_gate(const char *name, const char *parent,
362 void __iomem *reg, u8 shift,
363 unsigned long flags,
364 unsigned long clk_gate_flags)
365 {
366 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
367 shift, clk_gate_flags, &imx_ccm_lock);
368 }
369
__imx_clk_hw_gate2(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 cgr_val,unsigned long flags,unsigned int * share_count)370 static inline struct clk_hw *__imx_clk_hw_gate2(const char *name, const char *parent,
371 void __iomem *reg, u8 shift, u8 cgr_val,
372 unsigned long flags,
373 unsigned int *share_count)
374 {
375 return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
376 shift, cgr_val, 0x3, 0, &imx_ccm_lock, share_count);
377 }
378
__imx_clk_hw_mux(const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents,unsigned long flags,unsigned long clk_mux_flags)379 static inline struct clk_hw *__imx_clk_hw_mux(const char *name, void __iomem *reg,
380 u8 shift, u8 width, const char * const *parents,
381 int num_parents, unsigned long flags, unsigned long clk_mux_flags)
382 {
383 return clk_hw_register_mux(NULL, name, parents, num_parents,
384 flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
385 width, clk_mux_flags, &imx_ccm_lock);
386 }
387
388 struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
389 struct clk *div, struct clk *mux, struct clk *pll,
390 struct clk *step);
391
392 #define IMX_COMPOSITE_CORE BIT(0)
393 #define IMX_COMPOSITE_BUS BIT(1)
394 #define IMX_COMPOSITE_FW_MANAGED BIT(2)
395
396 #define IMX_COMPOSITE_CLK_FLAGS_DEFAULT \
397 (CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
398 #define IMX_COMPOSITE_CLK_FLAGS_CRITICAL \
399 (IMX_COMPOSITE_CLK_FLAGS_DEFAULT | CLK_IS_CRITICAL)
400 #define IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE \
401 (IMX_COMPOSITE_CLK_FLAGS_DEFAULT | CLK_GET_RATE_NOCACHE)
402 #define IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE \
403 (IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE | CLK_IS_CRITICAL)
404
405 struct clk_hw *__imx8m_clk_hw_composite(const char *name,
406 const char * const *parent_names,
407 int num_parents,
408 void __iomem *reg,
409 u32 composite_flags,
410 unsigned long flags);
411
412 #define _imx8m_clk_hw_composite(name, parent_names, reg, composite_flags, flags) \
413 __imx8m_clk_hw_composite(name, parent_names, \
414 ARRAY_SIZE(parent_names), reg, composite_flags, flags)
415
416 #define imx8m_clk_hw_composite(name, parent_names, reg) \
417 _imx8m_clk_hw_composite(name, parent_names, reg, \
418 0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
419
420 #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \
421 _imx8m_clk_hw_composite(name, parent_names, reg, \
422 0, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
423
424 #define imx8m_clk_hw_composite_bus(name, parent_names, reg) \
425 _imx8m_clk_hw_composite(name, parent_names, reg, \
426 IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
427
428 #define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg) \
429 _imx8m_clk_hw_composite(name, parent_names, reg, \
430 IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
431
432 #define imx8m_clk_hw_composite_core(name, parent_names, reg) \
433 _imx8m_clk_hw_composite(name, parent_names, reg, \
434 IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
435
436 #define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \
437 _imx8m_clk_hw_composite(name, parent_names, reg, \
438 IMX_COMPOSITE_FW_MANAGED, \
439 IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE)
440
441 #define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) \
442 _imx8m_clk_hw_composite(name, parent_names, reg, \
443 IMX_COMPOSITE_FW_MANAGED, \
444 IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE)
445
446 struct clk_hw *imx93_clk_composite_flags(const char *name,
447 const char * const *parent_names,
448 int num_parents,
449 void __iomem *reg,
450 u32 domain_id,
451 unsigned long flags);
452 #define imx93_clk_composite(name, parent_names, num_parents, reg, domain_id) \
453 imx93_clk_composite_flags(name, parent_names, num_parents, reg, domain_id \
454 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
455
456 struct clk_hw *imx93_clk_gate(struct device *dev, const char *name, const char *parent_name,
457 unsigned long flags, void __iomem *reg, u32 bit_idx, u32 val,
458 u32 mask, u32 domain_id, unsigned int *share_count);
459
460 struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,
461 unsigned long flags, void __iomem *reg, u8 shift, u8 width,
462 u8 clk_divider_flags, const struct clk_div_table *table,
463 spinlock_t *lock);
464
465 struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible,
466 u32 reg, const char **parent_names,
467 u8 num_parents, const u32 *mux_table, u32 mask);
468
469 #endif
470