1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_GT_TYPES__ 7 #define __INTEL_GT_TYPES__ 8 9 #include <linux/ktime.h> 10 #include <linux/list.h> 11 #include <linux/llist.h> 12 #include <linux/mutex.h> 13 #include <linux/notifier.h> 14 #include <linux/seqlock.h> 15 #include <linux/spinlock.h> 16 #include <linux/types.h> 17 #include <linux/workqueue.h> 18 19 #include "uc/intel_uc.h" 20 #include "intel_gsc.h" 21 22 #include "i915_vma.h" 23 #include "i915_perf_types.h" 24 #include "intel_engine_types.h" 25 #include "intel_gt_buffer_pool_types.h" 26 #include "intel_hwconfig.h" 27 #include "intel_llc_types.h" 28 #include "intel_reset_types.h" 29 #include "intel_rc6_types.h" 30 #include "intel_rps_types.h" 31 #include "intel_migrate_types.h" 32 #include "intel_wakeref.h" 33 #include "intel_wopcm.h" 34 35 struct drm_i915_private; 36 struct i915_ggtt; 37 struct intel_engine_cs; 38 struct intel_uncore; 39 40 struct intel_mmio_range { 41 u32 start; 42 u32 end; 43 }; 44 45 /* 46 * The hardware has multiple kinds of multicast register ranges that need 47 * special register steering (and future platforms are expected to add 48 * additional types). 49 * 50 * During driver startup, we initialize the steering control register to 51 * direct reads to a slice/subslice that are valid for the 'subslice' class 52 * of multicast registers. If another type of steering does not have any 53 * overlap in valid steering targets with 'subslice' style registers, we will 54 * need to explicitly re-steer reads of registers of the other type. 55 * 56 * Only the replication types that may need additional non-default steering 57 * are listed here. 58 */ 59 enum intel_steering_type { 60 L3BANK, 61 MSLICE, 62 LNCF, 63 GAM, 64 DSS, 65 OADDRM, 66 67 /* 68 * On some platforms there are multiple types of MCR registers that 69 * will always return a non-terminated value at instance (0, 0). We'll 70 * lump those all into a single category to keep things simple. 71 */ 72 INSTANCE0, 73 74 NUM_STEERING_TYPES 75 }; 76 77 enum intel_submission_method { 78 INTEL_SUBMISSION_RING, 79 INTEL_SUBMISSION_ELSP, 80 INTEL_SUBMISSION_GUC, 81 }; 82 83 struct gt_defaults { 84 u32 min_freq; 85 u32 max_freq; 86 }; 87 88 enum intel_gt_type { 89 GT_PRIMARY, 90 GT_TILE, 91 GT_MEDIA, 92 }; 93 94 struct intel_gt { 95 struct drm_i915_private *i915; 96 const char *name; 97 enum intel_gt_type type; 98 99 struct intel_uncore *uncore; 100 struct i915_ggtt *ggtt; 101 102 struct intel_uc uc; 103 struct intel_gsc gsc; 104 struct intel_wopcm wopcm; 105 106 struct { 107 /* Serialize global tlb invalidations */ 108 struct mutex invalidate_lock; 109 110 /* 111 * Batch TLB invalidations 112 * 113 * After unbinding the PTE, we need to ensure the TLB 114 * are invalidated prior to releasing the physical pages. 115 * But we only need one such invalidation for all unbinds, 116 * so we track how many TLB invalidations have been 117 * performed since unbind the PTE and only emit an extra 118 * invalidate if no full barrier has been passed. 119 */ 120 seqcount_mutex_t seqno; 121 } tlb; 122 123 struct i915_wa_list wa_list; 124 125 struct intel_gt_timelines { 126 spinlock_t lock; /* protects active_list */ 127 struct list_head active_list; 128 } timelines; 129 130 struct intel_gt_requests { 131 /** 132 * We leave the user IRQ off as much as possible, 133 * but this means that requests will finish and never 134 * be retired once the system goes idle. Set a timer to 135 * fire periodically while the ring is running. When it 136 * fires, go retire requests. 137 */ 138 struct delayed_work retire_work; 139 } requests; 140 141 struct { 142 struct llist_head list; 143 struct work_struct work; 144 } watchdog; 145 146 struct intel_wakeref wakeref; 147 atomic_t user_wakeref; 148 149 struct list_head closed_vma; 150 spinlock_t closed_lock; /* guards the list of closed_vma */ 151 152 ktime_t last_init_time; 153 struct intel_reset reset; 154 155 /** 156 * Is the GPU currently considered idle, or busy executing 157 * userspace requests? Whilst idle, we allow runtime power 158 * management to power down the hardware and display clocks. 159 * In order to reduce the effect on performance, there 160 * is a slight delay before we do so. 161 */ 162 intel_wakeref_t awake; 163 164 u32 clock_frequency; 165 u32 clock_period_ns; 166 167 struct intel_llc llc; 168 struct intel_rc6 rc6; 169 struct intel_rps rps; 170 171 spinlock_t *irq_lock; 172 u32 gt_imr; 173 u32 pm_ier; 174 u32 pm_imr; 175 176 u32 pm_guc_events; 177 178 struct { 179 bool active; 180 181 /** 182 * @lock: Lock protecting the below fields. 183 */ 184 seqcount_mutex_t lock; 185 186 /** 187 * @total: Total time this engine was busy. 188 * 189 * Accumulated time not counting the most recent block in cases 190 * where engine is currently busy (active > 0). 191 */ 192 ktime_t total; 193 194 /** 195 * @start: Timestamp of the last idle to active transition. 196 * 197 * Idle is defined as active == 0, active is active > 0. 198 */ 199 ktime_t start; 200 } stats; 201 202 struct intel_engine_cs *engine[I915_NUM_ENGINES]; 203 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1] 204 [MAX_ENGINE_INSTANCE + 1]; 205 enum intel_submission_method submission_method; 206 207 /* 208 * Default address space (either GGTT or ppGTT depending on arch). 209 * 210 * Reserved for exclusive use by the kernel. 211 */ 212 struct i915_address_space *vm; 213 214 /* 215 * A pool of objects to use as shadow copies of client batch buffers 216 * when the command parser is enabled. Prevents the client from 217 * modifying the batch contents after software parsing. 218 * 219 * Buffers older than 1s are periodically reaped from the pool, 220 * or may be reclaimed by the shrinker before then. 221 */ 222 struct intel_gt_buffer_pool buffer_pool; 223 224 struct i915_vma *scratch; 225 226 struct intel_migrate migrate; 227 228 const struct intel_mmio_range *steering_table[NUM_STEERING_TYPES]; 229 230 struct { 231 u8 groupid; 232 u8 instanceid; 233 } default_steering; 234 235 /** 236 * @mcr_lock: Protects the MCR steering register 237 * 238 * Protects the MCR steering register (e.g., GEN8_MCR_SELECTOR). 239 * Should be taken before uncore->lock in cases where both are desired. 240 */ 241 spinlock_t mcr_lock; 242 243 /* 244 * Base of per-tile GTTMMADR where we can derive the MMIO and the GGTT. 245 */ 246 phys_addr_t phys_addr; 247 248 struct intel_gt_info { 249 unsigned int id; 250 251 intel_engine_mask_t engine_mask; 252 253 u32 l3bank_mask; 254 255 u8 num_engines; 256 257 /* General presence of SFC units */ 258 u8 sfc_mask; 259 260 /* Media engine access to SFC per instance */ 261 u8 vdbox_sfc_access; 262 263 /* Slice/subslice/EU info */ 264 struct sseu_dev_info sseu; 265 266 unsigned long mslice_mask; 267 268 /** @hwconfig: hardware configuration data */ 269 struct intel_hwconfig hwconfig; 270 } info; 271 272 struct { 273 u8 uc_index; 274 u8 wb_index; /* Only used on HAS_L3_CCS_READ() platforms */ 275 } mocs; 276 277 /* gt/gtN sysfs */ 278 struct kobject sysfs_gt; 279 280 /* sysfs defaults per gt */ 281 struct gt_defaults defaults; 282 struct kobject *sysfs_defaults; 283 284 struct i915_perf_gt perf; 285 286 /** link: &ggtt.gt_list */ 287 struct list_head ggtt_link; 288 }; 289 290 struct intel_gt_definition { 291 enum intel_gt_type type; 292 char *name; 293 u32 mapping_base; 294 u32 gsi_offset; 295 intel_engine_mask_t engine_mask; 296 }; 297 298 enum intel_gt_scratch_field { 299 /* 8 bytes */ 300 INTEL_GT_SCRATCH_FIELD_DEFAULT = 0, 301 302 /* 8 bytes */ 303 INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH = 128, 304 305 /* 8 bytes */ 306 INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256, 307 }; 308 309 #endif /* __INTEL_GT_TYPES_H__ */ 310