1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef __IP30_COMMON_H
4 #define __IP30_COMMON_H
5 
6 /*
7  * Power Switch is wired via BaseIO BRIDGE slot #6.
8  *
9  * ACFail is wired via BaseIO BRIDGE slot #7.
10  */
11 #define IP30_POWER_IRQ		HEART_L2_INT_POWER_BTN
12 
13 #define IP30_HEART_L0_IRQ	(MIPS_CPU_IRQ_BASE + 2)
14 #define IP30_HEART_L1_IRQ	(MIPS_CPU_IRQ_BASE + 3)
15 #define IP30_HEART_L2_IRQ	(MIPS_CPU_IRQ_BASE + 4)
16 #define IP30_HEART_TIMER_IRQ	(MIPS_CPU_IRQ_BASE + 5)
17 #define IP30_HEART_ERR_IRQ	(MIPS_CPU_IRQ_BASE + 6)
18 
19 extern void __init ip30_install_ipi(void);
20 extern struct plat_smp_ops ip30_smp_ops;
21 extern void __init ip30_per_cpu_init(void);
22 
23 #endif /* __IP30_COMMON_H */
24