1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #ifdef pr_fmt
32 #undef pr_fmt
33 #endif
34
35 #define pr_fmt(fmt) "amdgpu: " fmt
36
37 #ifdef dev_fmt
38 #undef dev_fmt
39 #endif
40
41 #define dev_fmt(fmt) "amdgpu: " fmt
42
43 #include "amdgpu_ctx.h"
44
45 #include <linux/atomic.h>
46 #include <linux/wait.h>
47 #include <linux/list.h>
48 #include <linux/kref.h>
49 #include <linux/rbtree.h>
50 #include <linux/hashtable.h>
51 #include <linux/dma-fence.h>
52 #include <linux/pci.h>
53 #include <linux/aer.h>
54
55 #include <drm/ttm/ttm_bo.h>
56 #include <drm/ttm/ttm_placement.h>
57 #include <drm/ttm/ttm_execbuf_util.h>
58
59 #include <drm/amdgpu_drm.h>
60 #include <drm/drm_gem.h>
61 #include <drm/drm_ioctl.h>
62
63 #include <kgd_kfd_interface.h>
64 #include "dm_pp_interface.h"
65 #include "kgd_pp_interface.h"
66
67 #include "amd_shared.h"
68 #include "amdgpu_mode.h"
69 #include "amdgpu_ih.h"
70 #include "amdgpu_irq.h"
71 #include "amdgpu_ucode.h"
72 #include "amdgpu_ttm.h"
73 #include "amdgpu_psp.h"
74 #include "amdgpu_gds.h"
75 #include "amdgpu_sync.h"
76 #include "amdgpu_ring.h"
77 #include "amdgpu_vm.h"
78 #include "amdgpu_dpm.h"
79 #include "amdgpu_acp.h"
80 #include "amdgpu_uvd.h"
81 #include "amdgpu_vce.h"
82 #include "amdgpu_vcn.h"
83 #include "amdgpu_jpeg.h"
84 #include "amdgpu_gmc.h"
85 #include "amdgpu_gfx.h"
86 #include "amdgpu_sdma.h"
87 #include "amdgpu_lsdma.h"
88 #include "amdgpu_nbio.h"
89 #include "amdgpu_hdp.h"
90 #include "amdgpu_dm.h"
91 #include "amdgpu_virt.h"
92 #include "amdgpu_csa.h"
93 #include "amdgpu_mes_ctx.h"
94 #include "amdgpu_gart.h"
95 #include "amdgpu_debugfs.h"
96 #include "amdgpu_job.h"
97 #include "amdgpu_bo_list.h"
98 #include "amdgpu_gem.h"
99 #include "amdgpu_doorbell.h"
100 #include "amdgpu_amdkfd.h"
101 #include "amdgpu_discovery.h"
102 #include "amdgpu_mes.h"
103 #include "amdgpu_umc.h"
104 #include "amdgpu_mmhub.h"
105 #include "amdgpu_gfxhub.h"
106 #include "amdgpu_df.h"
107 #include "amdgpu_smuio.h"
108 #include "amdgpu_fdinfo.h"
109 #include "amdgpu_mca.h"
110 #include "amdgpu_ras.h"
111
112 #define MAX_GPU_INSTANCE 16
113
114 struct amdgpu_gpu_instance
115 {
116 struct amdgpu_device *adev;
117 int mgpu_fan_enabled;
118 };
119
120 struct amdgpu_mgpu_info
121 {
122 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
123 struct mutex mutex;
124 uint32_t num_gpu;
125 uint32_t num_dgpu;
126 uint32_t num_apu;
127
128 /* delayed reset_func for XGMI configuration if necessary */
129 struct delayed_work delayed_reset_work;
130 bool pending_reset;
131 };
132
133 enum amdgpu_ss {
134 AMDGPU_SS_DRV_LOAD,
135 AMDGPU_SS_DEV_D0,
136 AMDGPU_SS_DEV_D3,
137 AMDGPU_SS_DRV_UNLOAD
138 };
139
140 struct amdgpu_watchdog_timer
141 {
142 bool timeout_fatal_disable;
143 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
144 };
145
146 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
147
148 /*
149 * Modules parameters.
150 */
151 extern int amdgpu_modeset;
152 extern unsigned int amdgpu_vram_limit;
153 extern int amdgpu_vis_vram_limit;
154 extern int amdgpu_gart_size;
155 extern int amdgpu_gtt_size;
156 extern int amdgpu_moverate;
157 extern int amdgpu_audio;
158 extern int amdgpu_disp_priority;
159 extern int amdgpu_hw_i2c;
160 extern int amdgpu_pcie_gen2;
161 extern int amdgpu_msi;
162 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
163 extern int amdgpu_dpm;
164 extern int amdgpu_fw_load_type;
165 extern int amdgpu_aspm;
166 extern int amdgpu_runtime_pm;
167 extern uint amdgpu_ip_block_mask;
168 extern int amdgpu_bapm;
169 extern int amdgpu_deep_color;
170 extern int amdgpu_vm_size;
171 extern int amdgpu_vm_block_size;
172 extern int amdgpu_vm_fragment_size;
173 extern int amdgpu_vm_fault_stop;
174 extern int amdgpu_vm_debug;
175 extern int amdgpu_vm_update_mode;
176 extern int amdgpu_exp_hw_support;
177 extern int amdgpu_dc;
178 extern int amdgpu_sched_jobs;
179 extern int amdgpu_sched_hw_submission;
180 extern uint amdgpu_pcie_gen_cap;
181 extern uint amdgpu_pcie_lane_cap;
182 extern u64 amdgpu_cg_mask;
183 extern uint amdgpu_pg_mask;
184 extern uint amdgpu_sdma_phase_quantum;
185 extern char *amdgpu_disable_cu;
186 extern char *amdgpu_virtual_display;
187 extern uint amdgpu_pp_feature_mask;
188 extern uint amdgpu_force_long_training;
189 extern int amdgpu_job_hang_limit;
190 extern int amdgpu_lbpw;
191 extern int amdgpu_compute_multipipe;
192 extern int amdgpu_gpu_recovery;
193 extern int amdgpu_emu_mode;
194 extern uint amdgpu_smu_memory_pool_size;
195 extern int amdgpu_smu_pptable_id;
196 extern uint amdgpu_dc_feature_mask;
197 extern uint amdgpu_freesync_vid_mode;
198 extern uint amdgpu_dc_debug_mask;
199 extern uint amdgpu_dc_visual_confirm;
200 extern uint amdgpu_dm_abm_level;
201 extern int amdgpu_backlight;
202 extern struct amdgpu_mgpu_info mgpu_info;
203 extern int amdgpu_ras_enable;
204 extern uint amdgpu_ras_mask;
205 extern int amdgpu_bad_page_threshold;
206 extern bool amdgpu_ignore_bad_page_threshold;
207 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
208 extern int amdgpu_async_gfx_ring;
209 extern int amdgpu_mcbp;
210 extern int amdgpu_discovery;
211 extern int amdgpu_mes;
212 extern int amdgpu_mes_kiq;
213 extern int amdgpu_noretry;
214 extern int amdgpu_force_asic_type;
215 extern int amdgpu_smartshift_bias;
216 extern int amdgpu_use_xgmi_p2p;
217 #ifdef CONFIG_HSA_AMD
218 extern int sched_policy;
219 extern bool debug_evictions;
220 extern bool no_system_mem_limit;
221 extern int halt_if_hws_hang;
222 #else
223 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
224 static const bool __maybe_unused debug_evictions; /* = false */
225 static const bool __maybe_unused no_system_mem_limit;
226 static const int __maybe_unused halt_if_hws_hang;
227 #endif
228 #ifdef CONFIG_HSA_AMD_P2P
229 extern bool pcie_p2p;
230 #endif
231
232 extern int amdgpu_tmz;
233 extern int amdgpu_reset_method;
234
235 #ifdef CONFIG_DRM_AMDGPU_SI
236 extern int amdgpu_si_support;
237 #endif
238 #ifdef CONFIG_DRM_AMDGPU_CIK
239 extern int amdgpu_cik_support;
240 #endif
241 extern int amdgpu_num_kcq;
242
243 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
244 extern int amdgpu_vcnfw_log;
245 extern int amdgpu_sg_display;
246
247 #define AMDGPU_VM_MAX_NUM_CTX 4096
248 #define AMDGPU_SG_THRESHOLD (256*1024*1024)
249 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
250 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
251 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
252 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
253 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
254 #define AMDGPUFB_CONN_LIMIT 4
255 #define AMDGPU_BIOS_NUM_SCRATCH 16
256
257 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
258
259 /* hard reset data */
260 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
261
262 /* reset flags */
263 #define AMDGPU_RESET_GFX (1 << 0)
264 #define AMDGPU_RESET_COMPUTE (1 << 1)
265 #define AMDGPU_RESET_DMA (1 << 2)
266 #define AMDGPU_RESET_CP (1 << 3)
267 #define AMDGPU_RESET_GRBM (1 << 4)
268 #define AMDGPU_RESET_DMA1 (1 << 5)
269 #define AMDGPU_RESET_RLC (1 << 6)
270 #define AMDGPU_RESET_SEM (1 << 7)
271 #define AMDGPU_RESET_IH (1 << 8)
272 #define AMDGPU_RESET_VMC (1 << 9)
273 #define AMDGPU_RESET_MC (1 << 10)
274 #define AMDGPU_RESET_DISPLAY (1 << 11)
275 #define AMDGPU_RESET_UVD (1 << 12)
276 #define AMDGPU_RESET_VCE (1 << 13)
277 #define AMDGPU_RESET_VCE1 (1 << 14)
278
279 /* max cursor sizes (in pixels) */
280 #define CIK_CURSOR_WIDTH 128
281 #define CIK_CURSOR_HEIGHT 128
282
283 /* smart shift bias level limits */
284 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
285 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
286
287 struct amdgpu_device;
288 struct amdgpu_irq_src;
289 struct amdgpu_fpriv;
290 struct amdgpu_bo_va_mapping;
291 struct kfd_vm_fault_info;
292 struct amdgpu_hive_info;
293 struct amdgpu_reset_context;
294 struct amdgpu_reset_control;
295
296 enum amdgpu_cp_irq {
297 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
298 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
299 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
300 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
301 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
302 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
303 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
304 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
305 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
306 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
307
308 AMDGPU_CP_IRQ_LAST
309 };
310
311 enum amdgpu_thermal_irq {
312 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
313 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
314
315 AMDGPU_THERMAL_IRQ_LAST
316 };
317
318 enum amdgpu_kiq_irq {
319 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
320 AMDGPU_CP_KIQ_IRQ_LAST
321 };
322 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */
323 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
324 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
325 #define MAX_KIQ_REG_TRY 1000
326
327 int amdgpu_device_ip_set_clockgating_state(void *dev,
328 enum amd_ip_block_type block_type,
329 enum amd_clockgating_state state);
330 int amdgpu_device_ip_set_powergating_state(void *dev,
331 enum amd_ip_block_type block_type,
332 enum amd_powergating_state state);
333 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
334 u64 *flags);
335 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
336 enum amd_ip_block_type block_type);
337 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
338 enum amd_ip_block_type block_type);
339
340 #define AMDGPU_MAX_IP_NUM 16
341
342 struct amdgpu_ip_block_status {
343 bool valid;
344 bool sw;
345 bool hw;
346 bool late_initialized;
347 bool hang;
348 };
349
350 struct amdgpu_ip_block_version {
351 const enum amd_ip_block_type type;
352 const u32 major;
353 const u32 minor;
354 const u32 rev;
355 const struct amd_ip_funcs *funcs;
356 };
357
358 #define HW_REV(_Major, _Minor, _Rev) \
359 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
360
361 struct amdgpu_ip_block {
362 struct amdgpu_ip_block_status status;
363 const struct amdgpu_ip_block_version *version;
364 };
365
366 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
367 enum amd_ip_block_type type,
368 u32 major, u32 minor);
369
370 struct amdgpu_ip_block *
371 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
372 enum amd_ip_block_type type);
373
374 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
375 const struct amdgpu_ip_block_version *ip_block_version);
376
377 /*
378 * BIOS.
379 */
380 bool amdgpu_get_bios(struct amdgpu_device *adev);
381 bool amdgpu_read_bios(struct amdgpu_device *adev);
382 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
383 u8 *bios, u32 length_bytes);
384 /*
385 * Clocks
386 */
387
388 #define AMDGPU_MAX_PPLL 3
389
390 struct amdgpu_clock {
391 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
392 struct amdgpu_pll spll;
393 struct amdgpu_pll mpll;
394 /* 10 Khz units */
395 uint32_t default_mclk;
396 uint32_t default_sclk;
397 uint32_t default_dispclk;
398 uint32_t current_dispclk;
399 uint32_t dp_extclk;
400 uint32_t max_pixel_clock;
401 };
402
403 /* sub-allocation manager, it has to be protected by another lock.
404 * By conception this is an helper for other part of the driver
405 * like the indirect buffer or semaphore, which both have their
406 * locking.
407 *
408 * Principe is simple, we keep a list of sub allocation in offset
409 * order (first entry has offset == 0, last entry has the highest
410 * offset).
411 *
412 * When allocating new object we first check if there is room at
413 * the end total_size - (last_object_offset + last_object_size) >=
414 * alloc_size. If so we allocate new object there.
415 *
416 * When there is not enough room at the end, we start waiting for
417 * each sub object until we reach object_offset+object_size >=
418 * alloc_size, this object then become the sub object we return.
419 *
420 * Alignment can't be bigger than page size.
421 *
422 * Hole are not considered for allocation to keep things simple.
423 * Assumption is that there won't be hole (all object on same
424 * alignment).
425 */
426
427 #define AMDGPU_SA_NUM_FENCE_LISTS 32
428
429 struct amdgpu_sa_manager {
430 wait_queue_head_t wq;
431 struct amdgpu_bo *bo;
432 struct list_head *hole;
433 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
434 struct list_head olist;
435 unsigned size;
436 uint64_t gpu_addr;
437 void *cpu_ptr;
438 uint32_t domain;
439 uint32_t align;
440 };
441
442 /* sub-allocation buffer */
443 struct amdgpu_sa_bo {
444 struct list_head olist;
445 struct list_head flist;
446 struct amdgpu_sa_manager *manager;
447 unsigned soffset;
448 unsigned eoffset;
449 struct dma_fence *fence;
450 };
451
452 int amdgpu_fence_slab_init(void);
453 void amdgpu_fence_slab_fini(void);
454
455 /*
456 * IRQS.
457 */
458
459 struct amdgpu_flip_work {
460 struct delayed_work flip_work;
461 struct work_struct unpin_work;
462 struct amdgpu_device *adev;
463 int crtc_id;
464 u32 target_vblank;
465 uint64_t base;
466 struct drm_pending_vblank_event *event;
467 struct amdgpu_bo *old_abo;
468 unsigned shared_count;
469 struct dma_fence **shared;
470 struct dma_fence_cb cb;
471 bool async;
472 };
473
474
475 /*
476 * file private structure
477 */
478
479 struct amdgpu_fpriv {
480 struct amdgpu_vm vm;
481 struct amdgpu_bo_va *prt_va;
482 struct amdgpu_bo_va *csa_va;
483 struct mutex bo_list_lock;
484 struct idr bo_list_handles;
485 struct amdgpu_ctx_mgr ctx_mgr;
486 };
487
488 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
489
490 /*
491 * Writeback
492 */
493 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */
494
495 struct amdgpu_wb {
496 struct amdgpu_bo *wb_obj;
497 volatile uint32_t *wb;
498 uint64_t gpu_addr;
499 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
500 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
501 };
502
503 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
504 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
505
506 /*
507 * Benchmarking
508 */
509 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
510
511 /*
512 * ASIC specific register table accessible by UMD
513 */
514 struct amdgpu_allowed_register_entry {
515 uint32_t reg_offset;
516 bool grbm_indexed;
517 };
518
519 enum amd_reset_method {
520 AMD_RESET_METHOD_NONE = -1,
521 AMD_RESET_METHOD_LEGACY = 0,
522 AMD_RESET_METHOD_MODE0,
523 AMD_RESET_METHOD_MODE1,
524 AMD_RESET_METHOD_MODE2,
525 AMD_RESET_METHOD_BACO,
526 AMD_RESET_METHOD_PCI,
527 };
528
529 struct amdgpu_video_codec_info {
530 u32 codec_type;
531 u32 max_width;
532 u32 max_height;
533 u32 max_pixels_per_frame;
534 u32 max_level;
535 };
536
537 #define codec_info_build(type, width, height, level) \
538 .codec_type = type,\
539 .max_width = width,\
540 .max_height = height,\
541 .max_pixels_per_frame = height * width,\
542 .max_level = level,
543
544 struct amdgpu_video_codecs {
545 const u32 codec_count;
546 const struct amdgpu_video_codec_info *codec_array;
547 };
548
549 /*
550 * ASIC specific functions.
551 */
552 struct amdgpu_asic_funcs {
553 bool (*read_disabled_bios)(struct amdgpu_device *adev);
554 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
555 u8 *bios, u32 length_bytes);
556 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
557 u32 sh_num, u32 reg_offset, u32 *value);
558 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
559 int (*reset)(struct amdgpu_device *adev);
560 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
561 /* get the reference clock */
562 u32 (*get_xclk)(struct amdgpu_device *adev);
563 /* MM block clocks */
564 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
565 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
566 /* static power management */
567 int (*get_pcie_lanes)(struct amdgpu_device *adev);
568 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
569 /* get config memsize register */
570 u32 (*get_config_memsize)(struct amdgpu_device *adev);
571 /* flush hdp write queue */
572 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
573 /* invalidate hdp read cache */
574 void (*invalidate_hdp)(struct amdgpu_device *adev,
575 struct amdgpu_ring *ring);
576 /* check if the asic needs a full reset of if soft reset will work */
577 bool (*need_full_reset)(struct amdgpu_device *adev);
578 /* initialize doorbell layout for specific asic*/
579 void (*init_doorbell_index)(struct amdgpu_device *adev);
580 /* PCIe bandwidth usage */
581 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
582 uint64_t *count1);
583 /* do we need to reset the asic at init time (e.g., kexec) */
584 bool (*need_reset_on_init)(struct amdgpu_device *adev);
585 /* PCIe replay counter */
586 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
587 /* device supports BACO */
588 bool (*supports_baco)(struct amdgpu_device *adev);
589 /* pre asic_init quirks */
590 void (*pre_asic_init)(struct amdgpu_device *adev);
591 /* enter/exit umd stable pstate */
592 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
593 /* query video codecs */
594 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
595 const struct amdgpu_video_codecs **codecs);
596 };
597
598 /*
599 * IOCTL.
600 */
601 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
602 struct drm_file *filp);
603
604 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
605 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
606 struct drm_file *filp);
607 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
608 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
609 struct drm_file *filp);
610
611 /* VRAM scratch page for HDP bug, default vram page */
612 struct amdgpu_mem_scratch {
613 struct amdgpu_bo *robj;
614 volatile uint32_t *ptr;
615 u64 gpu_addr;
616 };
617
618 /*
619 * CGS
620 */
621 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
622 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
623
624 /*
625 * Core structure, functions and helpers.
626 */
627 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
628 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
629
630 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
631 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
632
633 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
634 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
635
636 struct amdgpu_mmio_remap {
637 u32 reg_offset;
638 resource_size_t bus_addr;
639 };
640
641 /* Define the HW IP blocks will be used in driver , add more if necessary */
642 enum amd_hw_ip_block_type {
643 GC_HWIP = 1,
644 HDP_HWIP,
645 SDMA0_HWIP,
646 SDMA1_HWIP,
647 SDMA2_HWIP,
648 SDMA3_HWIP,
649 SDMA4_HWIP,
650 SDMA5_HWIP,
651 SDMA6_HWIP,
652 SDMA7_HWIP,
653 LSDMA_HWIP,
654 MMHUB_HWIP,
655 ATHUB_HWIP,
656 NBIO_HWIP,
657 MP0_HWIP,
658 MP1_HWIP,
659 UVD_HWIP,
660 VCN_HWIP = UVD_HWIP,
661 JPEG_HWIP = VCN_HWIP,
662 VCN1_HWIP,
663 VCE_HWIP,
664 DF_HWIP,
665 DCE_HWIP,
666 OSSSYS_HWIP,
667 SMUIO_HWIP,
668 PWR_HWIP,
669 NBIF_HWIP,
670 THM_HWIP,
671 CLK_HWIP,
672 UMC_HWIP,
673 RSMU_HWIP,
674 XGMI_HWIP,
675 DCI_HWIP,
676 PCIE_HWIP,
677 MAX_HWIP
678 };
679
680 #define HWIP_MAX_INSTANCE 28
681
682 #define HW_ID_MAX 300
683 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv))
684 #define IP_VERSION_MAJ(ver) ((ver) >> 16)
685 #define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF)
686 #define IP_VERSION_REV(ver) ((ver) & 0xFF)
687
688 struct amd_powerplay {
689 void *pp_handle;
690 const struct amd_pm_funcs *pp_funcs;
691 };
692
693 struct ip_discovery_top;
694
695 /* polaris10 kickers */
696 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
697 ((rid == 0xE3) || \
698 (rid == 0xE4) || \
699 (rid == 0xE5) || \
700 (rid == 0xE7) || \
701 (rid == 0xEF))) || \
702 ((did == 0x6FDF) && \
703 ((rid == 0xE7) || \
704 (rid == 0xEF) || \
705 (rid == 0xFF))))
706
707 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
708 ((rid == 0xE1) || \
709 (rid == 0xF7)))
710
711 /* polaris11 kickers */
712 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
713 ((rid == 0xE0) || \
714 (rid == 0xE5))) || \
715 ((did == 0x67FF) && \
716 ((rid == 0xCF) || \
717 (rid == 0xEF) || \
718 (rid == 0xFF))))
719
720 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
721 ((rid == 0xE2)))
722
723 /* polaris12 kickers */
724 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
725 ((rid == 0xC0) || \
726 (rid == 0xC1) || \
727 (rid == 0xC3) || \
728 (rid == 0xC7))) || \
729 ((did == 0x6981) && \
730 ((rid == 0x00) || \
731 (rid == 0x01) || \
732 (rid == 0x10))))
733
734 struct amdgpu_mqd_prop {
735 uint64_t mqd_gpu_addr;
736 uint64_t hqd_base_gpu_addr;
737 uint64_t rptr_gpu_addr;
738 uint64_t wptr_gpu_addr;
739 uint32_t queue_size;
740 bool use_doorbell;
741 uint32_t doorbell_index;
742 uint64_t eop_gpu_addr;
743 uint32_t hqd_pipe_priority;
744 uint32_t hqd_queue_priority;
745 bool hqd_active;
746 };
747
748 struct amdgpu_mqd {
749 unsigned mqd_size;
750 int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
751 struct amdgpu_mqd_prop *p);
752 };
753
754 #define AMDGPU_RESET_MAGIC_NUM 64
755 #define AMDGPU_MAX_DF_PERFMONS 4
756 #define AMDGPU_PRODUCT_NAME_LEN 64
757 struct amdgpu_reset_domain;
758
759 /*
760 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise.
761 */
762 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size)
763
764 struct amdgpu_device {
765 struct device *dev;
766 struct pci_dev *pdev;
767 struct drm_device ddev;
768
769 #ifdef CONFIG_DRM_AMD_ACP
770 struct amdgpu_acp acp;
771 #endif
772 struct amdgpu_hive_info *hive;
773 /* ASIC */
774 enum amd_asic_type asic_type;
775 uint32_t family;
776 uint32_t rev_id;
777 uint32_t external_rev_id;
778 unsigned long flags;
779 unsigned long apu_flags;
780 int usec_timeout;
781 const struct amdgpu_asic_funcs *asic_funcs;
782 bool shutdown;
783 bool need_swiotlb;
784 bool accel_working;
785 struct notifier_block acpi_nb;
786 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
787 struct debugfs_blob_wrapper debugfs_vbios_blob;
788 struct debugfs_blob_wrapper debugfs_discovery_blob;
789 struct mutex srbm_mutex;
790 /* GRBM index mutex. Protects concurrent access to GRBM index */
791 struct mutex grbm_idx_mutex;
792 struct dev_pm_domain vga_pm_domain;
793 bool have_disp_power_ref;
794 bool have_atomics_support;
795
796 /* BIOS */
797 bool is_atom_fw;
798 uint8_t *bios;
799 uint32_t bios_size;
800 uint32_t bios_scratch_reg_offset;
801 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
802
803 /* Register/doorbell mmio */
804 resource_size_t rmmio_base;
805 resource_size_t rmmio_size;
806 void __iomem *rmmio;
807 /* protects concurrent MM_INDEX/DATA based register access */
808 spinlock_t mmio_idx_lock;
809 struct amdgpu_mmio_remap rmmio_remap;
810 /* protects concurrent SMC based register access */
811 spinlock_t smc_idx_lock;
812 amdgpu_rreg_t smc_rreg;
813 amdgpu_wreg_t smc_wreg;
814 /* protects concurrent PCIE register access */
815 spinlock_t pcie_idx_lock;
816 amdgpu_rreg_t pcie_rreg;
817 amdgpu_wreg_t pcie_wreg;
818 amdgpu_rreg_t pciep_rreg;
819 amdgpu_wreg_t pciep_wreg;
820 amdgpu_rreg64_t pcie_rreg64;
821 amdgpu_wreg64_t pcie_wreg64;
822 /* protects concurrent UVD register access */
823 spinlock_t uvd_ctx_idx_lock;
824 amdgpu_rreg_t uvd_ctx_rreg;
825 amdgpu_wreg_t uvd_ctx_wreg;
826 /* protects concurrent DIDT register access */
827 spinlock_t didt_idx_lock;
828 amdgpu_rreg_t didt_rreg;
829 amdgpu_wreg_t didt_wreg;
830 /* protects concurrent gc_cac register access */
831 spinlock_t gc_cac_idx_lock;
832 amdgpu_rreg_t gc_cac_rreg;
833 amdgpu_wreg_t gc_cac_wreg;
834 /* protects concurrent se_cac register access */
835 spinlock_t se_cac_idx_lock;
836 amdgpu_rreg_t se_cac_rreg;
837 amdgpu_wreg_t se_cac_wreg;
838 /* protects concurrent ENDPOINT (audio) register access */
839 spinlock_t audio_endpt_idx_lock;
840 amdgpu_block_rreg_t audio_endpt_rreg;
841 amdgpu_block_wreg_t audio_endpt_wreg;
842 struct amdgpu_doorbell doorbell;
843
844 /* clock/pll info */
845 struct amdgpu_clock clock;
846
847 /* MC */
848 struct amdgpu_gmc gmc;
849 struct amdgpu_gart gart;
850 dma_addr_t dummy_page_addr;
851 struct amdgpu_vm_manager vm_manager;
852 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
853 unsigned num_vmhubs;
854
855 /* memory management */
856 struct amdgpu_mman mman;
857 struct amdgpu_mem_scratch mem_scratch;
858 struct amdgpu_wb wb;
859 atomic64_t num_bytes_moved;
860 atomic64_t num_evictions;
861 atomic64_t num_vram_cpu_page_faults;
862 atomic_t gpu_reset_counter;
863 atomic_t vram_lost_counter;
864
865 /* data for buffer migration throttling */
866 struct {
867 spinlock_t lock;
868 s64 last_update_us;
869 s64 accum_us; /* accumulated microseconds */
870 s64 accum_us_vis; /* for visible VRAM */
871 u32 log2_max_MBps;
872 } mm_stats;
873
874 /* display */
875 bool enable_virtual_display;
876 struct amdgpu_vkms_output *amdgpu_vkms_output;
877 struct amdgpu_mode_info mode_info;
878 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
879 struct delayed_work hotplug_work;
880 struct amdgpu_irq_src crtc_irq;
881 struct amdgpu_irq_src vline0_irq;
882 struct amdgpu_irq_src vupdate_irq;
883 struct amdgpu_irq_src pageflip_irq;
884 struct amdgpu_irq_src hpd_irq;
885 struct amdgpu_irq_src dmub_trace_irq;
886 struct amdgpu_irq_src dmub_outbox_irq;
887
888 /* rings */
889 u64 fence_context;
890 unsigned num_rings;
891 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
892 struct dma_fence __rcu *gang_submit;
893 bool ib_pool_ready;
894 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
895 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
896
897 /* interrupts */
898 struct amdgpu_irq irq;
899
900 /* powerplay */
901 struct amd_powerplay powerplay;
902 struct amdgpu_pm pm;
903 u64 cg_flags;
904 u32 pg_flags;
905
906 /* nbio */
907 struct amdgpu_nbio nbio;
908
909 /* hdp */
910 struct amdgpu_hdp hdp;
911
912 /* smuio */
913 struct amdgpu_smuio smuio;
914
915 /* mmhub */
916 struct amdgpu_mmhub mmhub;
917
918 /* gfxhub */
919 struct amdgpu_gfxhub gfxhub;
920
921 /* gfx */
922 struct amdgpu_gfx gfx;
923
924 /* sdma */
925 struct amdgpu_sdma sdma;
926
927 /* lsdma */
928 struct amdgpu_lsdma lsdma;
929
930 /* uvd */
931 struct amdgpu_uvd uvd;
932
933 /* vce */
934 struct amdgpu_vce vce;
935
936 /* vcn */
937 struct amdgpu_vcn vcn;
938
939 /* jpeg */
940 struct amdgpu_jpeg jpeg;
941
942 /* firmwares */
943 struct amdgpu_firmware firmware;
944
945 /* PSP */
946 struct psp_context psp;
947
948 /* GDS */
949 struct amdgpu_gds gds;
950
951 /* KFD */
952 struct amdgpu_kfd_dev kfd;
953
954 /* UMC */
955 struct amdgpu_umc umc;
956
957 /* display related functionality */
958 struct amdgpu_display_manager dm;
959
960 /* mes */
961 bool enable_mes;
962 bool enable_mes_kiq;
963 struct amdgpu_mes mes;
964 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
965
966 /* df */
967 struct amdgpu_df df;
968
969 /* MCA */
970 struct amdgpu_mca mca;
971
972 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
973 uint32_t harvest_ip_mask;
974 int num_ip_blocks;
975 struct mutex mn_lock;
976 DECLARE_HASHTABLE(mn_hash, 7);
977
978 /* tracking pinned memory */
979 atomic64_t vram_pin_size;
980 atomic64_t visible_pin_size;
981 atomic64_t gart_pin_size;
982
983 /* soc15 register offset based on ip, instance and segment */
984 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
985
986 /* delayed work_func for deferring clockgating during resume */
987 struct delayed_work delayed_init_work;
988
989 struct amdgpu_virt virt;
990
991 /* link all shadow bo */
992 struct list_head shadow_list;
993 struct mutex shadow_list_lock;
994
995 /* record hw reset is performed */
996 bool has_hw_reset;
997 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
998
999 /* s3/s4 mask */
1000 bool in_suspend;
1001 bool in_s3;
1002 bool in_s4;
1003 bool in_s0ix;
1004
1005 enum pp_mp1_state mp1_state;
1006 struct amdgpu_doorbell_index doorbell_index;
1007
1008 struct mutex notifier_lock;
1009
1010 int asic_reset_res;
1011 struct work_struct xgmi_reset_work;
1012 struct list_head reset_list;
1013
1014 long gfx_timeout;
1015 long sdma_timeout;
1016 long video_timeout;
1017 long compute_timeout;
1018
1019 uint64_t unique_id;
1020 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1021
1022 /* enable runtime pm on the device */
1023 bool in_runpm;
1024 bool has_pr3;
1025
1026 bool pm_sysfs_en;
1027 bool ucode_sysfs_en;
1028 bool psp_sysfs_en;
1029
1030 /* Chip product information */
1031 char product_number[20];
1032 char product_name[AMDGPU_PRODUCT_NAME_LEN];
1033 char serial[20];
1034
1035 atomic_t throttling_logging_enabled;
1036 struct ratelimit_state throttling_logging_rs;
1037 uint32_t ras_hw_enabled;
1038 uint32_t ras_enabled;
1039
1040 bool no_hw_access;
1041 struct pci_saved_state *pci_state;
1042 pci_channel_state_t pci_channel_state;
1043
1044 struct amdgpu_reset_control *reset_cntl;
1045 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1046
1047 bool ram_is_direct_mapped;
1048
1049 struct list_head ras_list;
1050
1051 struct ip_discovery_top *ip_top;
1052
1053 struct amdgpu_reset_domain *reset_domain;
1054
1055 struct mutex benchmark_mutex;
1056
1057 /* reset dump register */
1058 uint32_t *reset_dump_reg_list;
1059 uint32_t *reset_dump_reg_value;
1060 int num_regs;
1061 #ifdef CONFIG_DEV_COREDUMP
1062 struct amdgpu_task_info reset_task_info;
1063 bool reset_vram_lost;
1064 struct timespec64 reset_time;
1065 #endif
1066
1067 bool scpm_enabled;
1068 uint32_t scpm_status;
1069
1070 struct work_struct reset_work;
1071
1072 bool job_hang;
1073 bool dc_enabled;
1074 };
1075
drm_to_adev(struct drm_device * ddev)1076 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1077 {
1078 return container_of(ddev, struct amdgpu_device, ddev);
1079 }
1080
adev_to_drm(struct amdgpu_device * adev)1081 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1082 {
1083 return &adev->ddev;
1084 }
1085
amdgpu_ttm_adev(struct ttm_device * bdev)1086 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1087 {
1088 return container_of(bdev, struct amdgpu_device, mman.bdev);
1089 }
1090
1091 int amdgpu_device_init(struct amdgpu_device *adev,
1092 uint32_t flags);
1093 void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1094 void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1095
1096 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1097
1098 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1099 void *buf, size_t size, bool write);
1100 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1101 void *buf, size_t size, bool write);
1102
1103 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1104 void *buf, size_t size, bool write);
1105 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1106 uint32_t reg, uint32_t acc_flags);
1107 void amdgpu_device_wreg(struct amdgpu_device *adev,
1108 uint32_t reg, uint32_t v,
1109 uint32_t acc_flags);
1110 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1111 uint32_t reg, uint32_t v);
1112 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1113 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1114
1115 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1116 u32 pcie_index, u32 pcie_data,
1117 u32 reg_addr);
1118 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1119 u32 pcie_index, u32 pcie_data,
1120 u32 reg_addr);
1121 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1122 u32 pcie_index, u32 pcie_data,
1123 u32 reg_addr, u32 reg_data);
1124 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1125 u32 pcie_index, u32 pcie_data,
1126 u32 reg_addr, u64 reg_data);
1127
1128 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1129 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1130
1131 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);
1132
1133 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1134 struct amdgpu_reset_context *reset_context);
1135
1136 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1137 struct amdgpu_reset_context *reset_context);
1138
1139 int emu_soc_asic_init(struct amdgpu_device *adev);
1140
1141 /*
1142 * Registers read & write functions.
1143 */
1144 #define AMDGPU_REGS_NO_KIQ (1<<1)
1145 #define AMDGPU_REGS_RLC (1<<2)
1146
1147 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1148 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1149
1150 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1151 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1152
1153 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1154 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1155
1156 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1157 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1158 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1159 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1160 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1161 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1162 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1163 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1164 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1165 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1166 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1167 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1168 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1169 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1170 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1171 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1172 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1173 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1174 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1175 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1176 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1177 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1178 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1179 #define WREG32_P(reg, val, mask) \
1180 do { \
1181 uint32_t tmp_ = RREG32(reg); \
1182 tmp_ &= (mask); \
1183 tmp_ |= ((val) & ~(mask)); \
1184 WREG32(reg, tmp_); \
1185 } while (0)
1186 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1187 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1188 #define WREG32_PLL_P(reg, val, mask) \
1189 do { \
1190 uint32_t tmp_ = RREG32_PLL(reg); \
1191 tmp_ &= (mask); \
1192 tmp_ |= ((val) & ~(mask)); \
1193 WREG32_PLL(reg, tmp_); \
1194 } while (0)
1195
1196 #define WREG32_SMC_P(_Reg, _Val, _Mask) \
1197 do { \
1198 u32 tmp = RREG32_SMC(_Reg); \
1199 tmp &= (_Mask); \
1200 tmp |= ((_Val) & ~(_Mask)); \
1201 WREG32_SMC(_Reg, tmp); \
1202 } while (0)
1203
1204 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1205
1206 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1207 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1208
1209 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
1210 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1211 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1212
1213 #define REG_GET_FIELD(value, reg, field) \
1214 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1215
1216 #define WREG32_FIELD(reg, field, val) \
1217 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1218
1219 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1220 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1221
1222 /*
1223 * BIOS helpers.
1224 */
1225 #define RBIOS8(i) (adev->bios[i])
1226 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1227 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1228
1229 /*
1230 * ASICs macro.
1231 */
1232 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1233 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1234 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1235 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1236 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1237 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1238 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1239 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1240 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1241 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1242 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1243 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1244 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1245 #define amdgpu_asic_flush_hdp(adev, r) \
1246 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1247 #define amdgpu_asic_invalidate_hdp(adev, r) \
1248 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1249 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : 0))
1250 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1251 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1252 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1253 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1254 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1255 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1256 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1257 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1258 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1259 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1260
1261 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1262
1263 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
1264
1265 /* Common functions */
1266 bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1267 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1268 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1269 struct amdgpu_job *job,
1270 struct amdgpu_reset_context *reset_context);
1271 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1272 int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1273 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1274 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1275
1276 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1277 u64 num_vis_bytes);
1278 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1279 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1280 const u32 *registers,
1281 const u32 array_size);
1282
1283 int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1284 bool amdgpu_device_supports_atpx(struct drm_device *dev);
1285 bool amdgpu_device_supports_px(struct drm_device *dev);
1286 bool amdgpu_device_supports_boco(struct drm_device *dev);
1287 bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1288 bool amdgpu_device_supports_baco(struct drm_device *dev);
1289 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1290 struct amdgpu_device *peer_adev);
1291 int amdgpu_device_baco_enter(struct drm_device *dev);
1292 int amdgpu_device_baco_exit(struct drm_device *dev);
1293
1294 void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1295 struct amdgpu_ring *ring);
1296 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1297 struct amdgpu_ring *ring);
1298
1299 void amdgpu_device_halt(struct amdgpu_device *adev);
1300 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1301 u32 reg);
1302 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1303 u32 reg, u32 v);
1304 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
1305 struct dma_fence *gang);
1306 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
1307
1308 /* atpx handler */
1309 #if defined(CONFIG_VGA_SWITCHEROO)
1310 void amdgpu_register_atpx_handler(void);
1311 void amdgpu_unregister_atpx_handler(void);
1312 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1313 bool amdgpu_is_atpx_hybrid(void);
1314 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1315 bool amdgpu_has_atpx(void);
1316 #else
amdgpu_register_atpx_handler(void)1317 static inline void amdgpu_register_atpx_handler(void) {}
amdgpu_unregister_atpx_handler(void)1318 static inline void amdgpu_unregister_atpx_handler(void) {}
amdgpu_has_atpx_dgpu_power_cntl(void)1319 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
amdgpu_is_atpx_hybrid(void)1320 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
amdgpu_atpx_dgpu_req_power_for_displays(void)1321 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
amdgpu_has_atpx(void)1322 static inline bool amdgpu_has_atpx(void) { return false; }
1323 #endif
1324
1325 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1326 void *amdgpu_atpx_get_dhandle(void);
1327 #else
amdgpu_atpx_get_dhandle(void)1328 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1329 #endif
1330
1331 /*
1332 * KMS
1333 */
1334 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1335 extern const int amdgpu_max_kms_ioctl;
1336
1337 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1338 void amdgpu_driver_unload_kms(struct drm_device *dev);
1339 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1340 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1341 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1342 struct drm_file *file_priv);
1343 void amdgpu_driver_release_kms(struct drm_device *dev);
1344
1345 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1346 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1347 int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1348 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1349 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1350 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1351 int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1352 struct drm_file *filp);
1353
1354 /*
1355 * functions used by amdgpu_encoder.c
1356 */
1357 struct amdgpu_afmt_acr {
1358 u32 clock;
1359
1360 int n_32khz;
1361 int cts_32khz;
1362
1363 int n_44_1khz;
1364 int cts_44_1khz;
1365
1366 int n_48khz;
1367 int cts_48khz;
1368
1369 };
1370
1371 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1372
1373 /* amdgpu_acpi.c */
1374
1375 /* ATCS Device/Driver State */
1376 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
1377 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
1378 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
1379 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
1380
1381 #if defined(CONFIG_ACPI)
1382 int amdgpu_acpi_init(struct amdgpu_device *adev);
1383 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1384 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1385 bool amdgpu_acpi_is_power_shift_control_supported(void);
1386 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1387 u8 perf_req, bool advertise);
1388 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1389 u8 dev_state, bool drv_state);
1390 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1391 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1392
1393 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1394 void amdgpu_acpi_detect(void);
1395 #else
amdgpu_acpi_init(struct amdgpu_device * adev)1396 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
amdgpu_acpi_fini(struct amdgpu_device * adev)1397 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
amdgpu_acpi_detect(void)1398 static inline void amdgpu_acpi_detect(void) { }
amdgpu_acpi_is_power_shift_control_supported(void)1399 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
amdgpu_acpi_power_shift_control(struct amdgpu_device * adev,u8 dev_state,bool drv_state)1400 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1401 u8 dev_state, bool drv_state) { return 0; }
amdgpu_acpi_smart_shift_update(struct drm_device * dev,enum amdgpu_ss ss_state)1402 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
1403 enum amdgpu_ss ss_state) { return 0; }
1404 #endif
1405
1406 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1407 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1408 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1409 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1410 #else
amdgpu_acpi_is_s0ix_active(struct amdgpu_device * adev)1411 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
amdgpu_acpi_should_gpu_reset(struct amdgpu_device * adev)1412 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
amdgpu_acpi_is_s3_active(struct amdgpu_device * adev)1413 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1414 #endif
1415
1416 #if defined(CONFIG_DRM_AMD_DC)
1417 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1418 #else
amdgpu_dm_display_resume(struct amdgpu_device * adev)1419 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1420 #endif
1421
1422
1423 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1424 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1425
1426 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1427 pci_channel_state_t state);
1428 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1429 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1430 void amdgpu_pci_resume(struct pci_dev *pdev);
1431
1432 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1433 bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1434
1435 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1436
1437 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1438 enum amd_clockgating_state state);
1439 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1440 enum amd_powergating_state state);
1441
amdgpu_device_has_timeouts_enabled(struct amdgpu_device * adev)1442 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1443 {
1444 return amdgpu_gpu_recovery != 0 &&
1445 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1446 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1447 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1448 adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1449 }
1450
1451 #include "amdgpu_object.h"
1452
amdgpu_is_tmz(struct amdgpu_device * adev)1453 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1454 {
1455 return adev->gmc.tmz_enabled;
1456 }
1457
1458 int amdgpu_in_reset(struct amdgpu_device *adev);
1459
1460 #endif
1461