1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3  * Copyright (c) 2014, STMicroelectronics International N.V.
4  */
5 
6 #include <stdint.h>
7 
8 /*
9  *  General constants
10  */
11 
12 /*
13  * CP15 Multiprocessor Affinity register (MPIDR)
14  */
15 #define CP15_CONFIG_CPU_ID_MASK   U(0x00000003)
16 #define CPU_ID0    U(0x00000000)
17 #define CPU_ID1    U(0x00000001)
18 
19 /*
20  * CP15 Secure configuration register
21  */
22 #define CP15_CONFIG_NS_MASK   U(0x00000001)
23 #define CP15_CONFIG_IRQ_MASK  U(0x00000002)
24 #define CP15_CONFIG_FIQ_MASK  U(0x00000004)
25 #define CP15_CONFIG_EA_MASK   U(0x00000008)
26 #define CP15_CONFIG_FW_MASK   U(0x00000010)
27 #define CP15_CONFIG_AW_MASK   U(0x00000020)
28 #define CP15_CONFIG_nET_MASK  U(0x00000040)
29 
30 /*
31  * CP15 Control register
32  */
33 #define CP15_CONTROL_M_MASK          U(0x00000001)
34 #define CP15_CONTROL_C_MASK          U(0x00000004)
35 #define CP15_CONTROL_Z_MASK          U(0x00000800)
36 #define CP15_CONTROL_I_MASK          U(0x00001000)
37 #define CP15_CONTROL_V_MASK          U(0x00002000)
38 #define CP15_CONTROL_HA_MASK         U(0x00020000)
39 #define CP15_CONTROL_EE_MASK         U(0x02000000)
40 #define CP15_CONTROL_NMFI_MASK       U(0x08000000)
41 #define CP15_CONTROL_TRE_MASK        U(0x10000000)
42 #define CP15_CONTROL_AFE_MASK        U(0x20000000)
43 #define CP15_CONTROL_TE_MASK         U(0x40000000)
44 
45 /*
46  * CP15 Auxiliary Control register
47  */
48 #define CP15_CONTROL_SMP_MASK        U(0x00000040)
49 #define CP15_CONTROL_EXCL_MASK       U(0x00000080)
50 
51 /*
52  * CP15 Non secure access control register
53  */
54 #define CP15_NSAC_TL_MASK        U(0x10000)
55 #define CP15_NSAC_CL_MASK        U(0x20000)
56 #define CP15_NSAC_CPN_MASK       U(0x3FFF)
57 
58 /*
59  * CP15 Cache register
60  */
61 #define CP15_CACHE_ADDR_R_BIT    U(12)
62 #define CP15_CACHE_ADDR_L_BIT    (U(32) - CP15_CACHE_ADDR_R_BIT)
63 #define CP15_CACHE_RESULT_MASK   U(0x00000001)
64 
65 /*
66  * CP15 TCM register
67  *
68  * ITCM configuration (4kbytes, @0x20100000, enabled)
69  * DTCM configuration (4kbytes, @0x20101000, enabled)
70  */
71 #define CP15_TCM_ENABLE_MASK     U(0x00000001)
72 #define CP15_TCM_INSTR_TCM       U(0x2010000C)
73 #define CP15_TCM_DATA_TCM        U(0x2010100C)
74 
75 /*
76  * CP15 cache lockdown register
77  *
78  * ITCM configuration (4kbytes, @0x20100000, enabled)
79  * DTCM configuration (4kbytes, @0x20101000, enabled)
80  */
81 #define CP15_CACHE_LOCK_ALLWAYS_MASK     U(0x0000000F)
82 
83 /*
84  * CP15 cache cleaning constant definition
85  */
86 /* start of line number field offset in way/index format */
87 #define LINE_FIELD_OFFSET        U(5)
88 /* Warning: this assumes a 256 lines/way cache (32kB cache) */
89 #define LINE_FIELD_OVERFLOW      U(13)
90 /* start of way number field offset in way/index format */
91 #define WAY_FIELD_OFFSET         U(30)
92