1 /*
2 * @brief LPC15xx I2C driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2014
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __I2C_COMMON_15XX_H_
33 #define __I2C_COMMON_15XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /** @defgroup I2C_15XX CHIP: LPC15xx I2C driver
40 * @ingroup CHIP_15XX_Drivers
41 * @{
42 */
43
44 /**
45 * @brief I2C register block structure
46 */
47 typedef struct { /* I2C0 Structure */
48 __IO uint32_t CFG; /*!< I2C Configuration Register common for Master, Slave and Monitor */
49 __IO uint32_t STAT; /*!< I2C Status Register common for Master, Slave and Monitor */
50 __IO uint32_t INTENSET; /*!< I2C Interrupt Enable Set Register common for Master, Slave and Monitor */
51 __O uint32_t INTENCLR; /*!< I2C Interrupt Enable Clear Register common for Master, Slave and Monitor */
52 __IO uint32_t TIMEOUT; /*!< I2C Timeout value Register */
53 __IO uint32_t CLKDIV; /*!< I2C Clock Divider Register */
54 __I uint32_t INTSTAT; /*!< I2C Interrupt Status Register */
55 __I uint32_t RESERVED0;
56 __IO uint32_t MSTCTL; /*!< I2C Master Control Register */
57 __IO uint32_t MSTTIME; /*!< I2C Master Time Register for SCL */
58 __IO uint32_t MSTDAT; /*!< I2C Master Data Register */
59 __I uint32_t RESERVED1[5];
60 __IO uint32_t SLVCTL; /*!< I2C Slave Control Register */
61 __IO uint32_t SLVDAT; /*!< I2C Slave Data Register */
62 __IO uint32_t SLVADR[4]; /*!< I2C Slave Address Registers */
63 __IO uint32_t SLVQUAL0; /*!< I2C Slave Address Qualifier 0 Register */
64 __I uint32_t RESERVED2[9];
65 __I uint32_t MONRXDAT; /*!< I2C Monitor Data Register */
66 } LPC_I2C_T;
67
68 /*
69 * @brief I2C Configuration register Bit definition
70 */
71 #define I2C_CFG_MSTEN (1 << 0) /*!< Master Enable/Disable Bit */
72 #define I2C_CFG_SLVEN (1 << 1) /*!< Slave Enable/Disable Bit */
73 #define I2C_CFG_MONEN (1 << 2) /*!< Monitor Enable/Disable Bit */
74 #define I2C_CFG_TIMEOUTEN (1 << 3) /*!< Timeout Enable/Disable Bit */
75 #define I2C_CFG_MONCLKSTR (1 << 4) /*!< Monitor Clock Stretching Bit */
76 #define I2C_CFG_MASK ((uint32_t) 0x1F) /*!< Configuration register Mask */
77
78 /*
79 * @brief I2C Status register Bit definition
80 */
81 #define I2C_STAT_MSTPENDING (1 << 0) /*!< Master Pending Status Bit */
82 #define I2C_STAT_MSTSTATE (0x7 << 1) /*!< Master State Code */
83 #define I2C_STAT_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Bit */
84 #define I2C_STAT_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Bit */
85 #define I2C_STAT_SLVPENDING (1 << 8) /*!< Slave Pending Status Bit */
86 #define I2C_STAT_SLVSTATE (0x3 << 9) /*!< Slave State Code */
87 #define I2C_STAT_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Bit */
88 #define I2C_STAT_SLVIDX (0x3 << 12) /*!< Slave Address Index */
89 #define I2C_STAT_SLVSEL (1 << 14) /*!< Slave Selected Bit */
90 #define I2C_STAT_SLVDESEL (1 << 15) /*!< Slave Deselect Bit */
91 #define I2C_STAT_MONRDY (1 << 16) /*!< Monitor Ready Bit */
92 #define I2C_STAT_MONOV (1 << 17) /*!< Monitor Overflow Flag */
93 #define I2C_STAT_MONACTIVE (1 << 18) /*!< Monitor Active Flag */
94 #define I2C_STAT_MONIDLE (1 << 19) /*!< Monitor Idle Flag */
95 #define I2C_STAT_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Flag */
96 #define I2C_STAT_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Flag */
97
98 #define I2C_STAT_MSTCODE_IDLE (0) /*!< Master Idle State Code */
99 #define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */
100 #define I2C_STAT_MSTCODE_TXREADY (2) /*!< Master Transmit Ready State Code */
101 #define I2C_STAT_MSTCODE_NACKADR (3) /*!< Master NACK by slave on address State Code */
102 #define I2C_STAT_MSTCODE_NACKDAT (4) /*!< Master NACK by slave on data State Code */
103
104 #define I2C_STAT_SLVCODE_ADDR (0) /*!< Master Idle State Code */
105 #define I2C_STAT_SLVCODE_RX (1) /*!< Received data is available Code */
106 #define I2C_STAT_SLVCODE_TX (2) /*!< Data can be transmitted Code */
107
108 /*
109 * @brief I2C Interrupt Enable Set register Bit definition
110 */
111 #define I2C_INTENSET_MSTPENDING (1 << 0) /*!< Master Pending Interrupt Enable Bit */
112 #define I2C_INTENSET_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Interrupt Enable Bit */
113 #define I2C_INTENSET_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Interrupt Enable Bit */
114 #define I2C_INTENSET_SLVPENDING (1 << 8) /*!< Slave Pending Interrupt Enable Bit */
115 #define I2C_INTENSET_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Interrupt Enable Bit */
116 #define I2C_INTENSET_SLVDESEL (1 << 15) /*!< Slave Deselect Interrupt Enable Bit */
117 #define I2C_INTENSET_MONRDY (1 << 16) /*!< Monitor Ready Interrupt Enable Bit */
118 #define I2C_INTENSET_MONOV (1 << 17) /*!< Monitor Overflow Interrupt Enable Bit */
119 #define I2C_INTENSET_MONIDLE (1 << 19) /*!< Monitor Idle Interrupt Enable Bit */
120 #define I2C_INTENSET_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Enable Bit */
121 #define I2C_INTENSET_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Enable Bit */
122
123 /*
124 * @brief I2C Interrupt Enable Clear register Bit definition
125 */
126 #define I2C_INTENCLR_MSTPENDING (1 << 0) /*!< Master Pending Interrupt Clear Bit */
127 #define I2C_INTENCLR_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Interrupt Clear Bit */
128 #define I2C_INTENCLR_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Interrupt Clear Bit */
129 #define I2C_INTENCLR_SLVPENDING (1 << 8) /*!< Slave Pending Interrupt Clear Bit */
130 #define I2C_INTENCLR_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Interrupt Clear Bit */
131 #define I2C_INTENCLR_SLVDESEL (1 << 15) /*!< Slave Deselect Interrupt Clear Bit */
132 #define I2C_INTENCLR_MONRDY (1 << 16) /*!< Monitor Ready Interrupt Clear Bit */
133 #define I2C_INTENCLR_MONOV (1 << 17) /*!< Monitor Overflow Interrupt Clear Bit */
134 #define I2C_INTENCLR_MONIDLE (1 << 19) /*!< Monitor Idle Interrupt Clear Bit */
135 #define I2C_INTENCLR_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Clear Bit */
136 #define I2C_INTENCLR_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Clear Bit */
137
138 /*
139 * @brief I2C TimeOut Value Macro
140 */
141 #define I2C_TIMEOUT_VAL(n) (((uint32_t) ((n) - 1) & 0xFFF0) | 0x000F) /*!< Macro for Timeout value register */
142
143 /*
144 * @brief I2C Interrupt Status register Bit definition
145 */
146 #define I2C_INTSTAT_MSTPENDING (1 << 0) /*!< Master Pending Interrupt Status Bit */
147 #define I2C_INTSTAT_MSTRARBLOSS (1 << 4) /*!< Master Arbitration Loss Interrupt Status Bit */
148 #define I2C_INTSTAT_MSTSTSTPERR (1 << 6) /*!< Master Start Stop Error Interrupt Status Bit */
149 #define I2C_INTSTAT_SLVPENDING (1 << 8) /*!< Slave Pending Interrupt Status Bit */
150 #define I2C_INTSTAT_SLVNOTSTR (1 << 11) /*!< Slave not stretching Clock Interrupt Status Bit */
151 #define I2C_INTSTAT_SLVDESEL (1 << 15) /*!< Slave Deselect Interrupt Status Bit */
152 #define I2C_INTSTAT_MONRDY (1 << 16) /*!< Monitor Ready Interrupt Status Bit */
153 #define I2C_INTSTAT_MONOV (1 << 17) /*!< Monitor Overflow Interrupt Status Bit */
154 #define I2C_INTSTAT_MONIDLE (1 << 19) /*!< Monitor Idle Interrupt Status Bit */
155 #define I2C_INTSTAT_EVENTTIMEOUT (1 << 24) /*!< Event Timeout Interrupt Status Bit */
156 #define I2C_INTSTAT_SCLTIMEOUT (1 << 25) /*!< SCL Timeout Interrupt Status Bit */
157
158 /*
159 * @brief I2C Master Control register Bit definition
160 */
161 #define I2C_MSTCTL_MSTCONTINUE (1 << 0) /*!< Master Continue Bit */
162 #define I2C_MSTCTL_MSTSTART (1 << 1) /*!< Master Start Control Bit */
163 #define I2C_MSTCTL_MSTSTOP (1 << 2) /*!< Master Stop Control Bit */
164 #define I2C_MSTCTL_MSTDMA (1 << 3) /*!< Master DMA Enable Bit */
165
166 /*
167 * @brief I2C Master Time Register Field definition
168 */
169 #define I2C_MSTTIME_MSTSCLLOW (0x07 << 0) /*!< Master SCL Low Time field */
170 #define I2C_MSTTIME_MSTSCLHIGH (0x07 << 4) /*!< Master SCL High Time field */
171
172 /*
173 * @brief I2C Master Data Mask
174 */
175 #define I2C_MSTDAT_DATAMASK ((uint32_t) 0x00FF << 0) /*!< Master data mask */
176
177 /*
178 * @brief I2C Slave Control register Bit definition
179 */
180 #define I2C_SLVCTL_SLVCONTINUE (1 << 0) /*!< Slave Continue Bit */
181 #define I2C_SLVCTL_SLVNACK (1 << 1) /*!< Slave NACK Bit */
182 #define I2C_SLVCTL_SLVDMA (1 << 3) /*!< Slave DMA Enable Bit */
183
184 /*
185 * @brief I2C Slave Data Mask
186 */
187 #define I2C_SLVDAT_DATAMASK ((uint32_t) 0x00FF << 0) /*!< Slave data mask */
188
189 /*
190 * @brief I2C Slave Address register Bit definition
191 */
192 #define I2C_SLVADR_SADISABLE (1 << 0) /*!< Slave Address n Disable Bit */
193 #define I2C_SLVADR_SLVADR (0x7F << 1) /*!< Slave Address field */
194 #define I2C_SLVADR_MASK ((uint32_t) 0x00FF) /*!< Slave Address Mask */
195
196 /*
197 * @brief I2C Slave Address Qualifier 0 Register Bit definition
198 */
199 #define I2C_SLVQUAL_QUALMODE0 (1 << 0) /*!< Slave Qualifier Mode Enable Bit */
200 #define I2C_SLVQUAL_SLVQUAL0 (0x7F << 1) /*!< Slave Qualifier Address for Address 0 */
201
202 /*
203 * @brief I2C Monitor Data Register Bit definition
204 */
205 #define I2C_MONRXDAT_DATA (0xFF << 0) /*!< Monitor Function Receive Data Field */
206 #define I2C_MONRXDAT_MONSTART (1 << 8) /*!< Monitor Received Start Bit */
207 #define I2C_MONRXDAT_MONRESTART (1 << 9) /*!< Monitor Received Repeated Start Bit */
208 #define I2C_MONRXDAT_MONNACK (1 << 10) /*!< Monitor Received Nack Bit */
209
210 /**
211 * @brief Initialize I2C Interface
212 * @param pI2C : Pointer to selected I2C peripheral
213 * @return Nothing
214 * @note This function enables the I2C clock for both the master and
215 * slave interfaces if the I2C channel.
216
217 */
218 void Chip_I2C_Init(LPC_I2C_T *pI2C);
219
220 /**
221 * @brief Shutdown I2C Interface
222 * @param pI2C : Pointer to selected I2C peripheral
223 * @return Nothing
224 * @note This function disables the I2C clock for both the master and
225 * slave interfaces if the I2C channel.
226 */
227 void Chip_I2C_DeInit(LPC_I2C_T *pI2C);
228
229 /**
230 * @brief Sets I2C Clock Divider registers
231 * @param pI2C : Pointer to selected I2C peripheral
232 * @param clkdiv : Clock Divider value for I2C, value is between (1 - 65536)
233 * @return Nothing
234 * @note The clock to I2C block is determined by the following formula (I2C_PCLK
235 * is the frequency of the system clock): <br>
236 * I2C Clock Frequency = (I2C_PCLK)/clkdiv;
237 */
Chip_I2C_SetClockDiv(LPC_I2C_T * pI2C,uint32_t clkdiv)238 static INLINE void Chip_I2C_SetClockDiv(LPC_I2C_T *pI2C, uint32_t clkdiv)
239 {
240 if ((clkdiv >= 1) && (clkdiv <= 65536)) {
241 pI2C->CLKDIV = clkdiv - 1;
242 }
243 else {
244 pI2C->CLKDIV = 0;
245 }
246 }
247
248 /**
249 * @brief Get I2C Clock Divider registers
250 * @param pI2C : Pointer to selected I2C peripheral
251 * @return Clock Divider value
252 * @note Return the divider value for the I2C block
253 * It is the CLKDIV register value + 1
254 */
Chip_I2C_GetClockDiv(LPC_I2C_T * pI2C)255 static INLINE uint32_t Chip_I2C_GetClockDiv(LPC_I2C_T *pI2C)
256 {
257 return (pI2C->CLKDIV & 0xFFFF) + 1;
258 }
259
260 /**
261 * @brief Enable I2C Interrupts
262 * @param pI2C : Pointer to selected I2C peripheral
263 * @param intEn : ORed Value of I2C_INTENSET_* values to enable
264 * @return Nothing
265 */
Chip_I2C_EnableInt(LPC_I2C_T * pI2C,uint32_t intEn)266 static INLINE void Chip_I2C_EnableInt(LPC_I2C_T *pI2C, uint32_t intEn)
267 {
268 pI2C->INTENSET = intEn;
269 }
270
271 /**
272 * @brief Disable I2C Interrupts
273 * @param pI2C : Pointer to selected I2C peripheral
274 * @param intClr : ORed Value of I2C_INTENSET_* values to disable
275 * @return Nothing
276 */
Chip_I2C_DisableInt(LPC_I2C_T * pI2C,uint32_t intClr)277 static INLINE void Chip_I2C_DisableInt(LPC_I2C_T *pI2C, uint32_t intClr)
278 {
279 pI2C->INTENCLR = intClr;
280 }
281
282 /**
283 * @brief Disable I2C Interrupts
284 * @param pI2C : Pointer to selected I2C peripheral
285 * @param intClr : ORed Value of I2C_INTENSET_* values to disable
286 * @return Nothing
287 * @note It is recommended to use the Chip_I2C_DisableInt() function
288 * instead of this function.
289 */
Chip_I2C_ClearInt(LPC_I2C_T * pI2C,uint32_t intClr)290 static INLINE void Chip_I2C_ClearInt(LPC_I2C_T *pI2C, uint32_t intClr)
291 {
292 Chip_I2C_DisableInt(pI2C, intClr);
293 }
294
295 /**
296 * @brief Returns pending I2C Interrupts
297 * @param pI2C : Pointer to selected I2C peripheral
298 * @return All pending interrupts, mask with I2C_INTENSET_* to determine specific interrupts
299 */
Chip_I2C_GetPendingInt(LPC_I2C_T * pI2C)300 static INLINE uint32_t Chip_I2C_GetPendingInt(LPC_I2C_T *pI2C)
301 {
302 return pI2C->INTSTAT;
303 }
304
305 /**
306 * @}
307 */
308
309 #ifdef __cplusplus
310 }
311 #endif
312
313 #endif /* __I2C_COMMON_15XX_H_ */
314