1 /*
2 * @brief LPC15xx Input Mux Registers and Driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2013
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __INMUX_15XX_H_
33 #define __INMUX_15XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /** @defgroup INMUX_15XX CHIP: LPC15xx Input Mux Registers and Driver
40 * @ingroup CHIP_15XX_Drivers
41 * @{
42 */
43
44 /**
45 * @brief LPC15xx Input Mux Register Block Structure
46 */
47 typedef struct { /*!< INMUX Structure */
48 __IO uint32_t SCT0_INMUX[7]; /*!< Input mux registers for SCT0 inputs */
49 __I uint32_t RESERVED1[1];
50 __IO uint32_t SCT1_INMUX[7]; /*!< Input mux registers for SCT1 inputs */
51 __I uint32_t RESERVED2[1];
52 __IO uint32_t SCT2_INMUX[3]; /*!< Input mux registers for SCT2 inputs */
53 __I uint32_t RESERVED3[5];
54 __IO uint32_t SCT3_INMUX[3]; /*!< Input mux registers for SCT3 inputs */
55 __I uint32_t RESERVED4[5];
56 __I uint32_t RESERVED4A[16];
57 __IO uint32_t PINTSEL[8]; /*!< Pin interrupt select registers */
58 __IO uint32_t DMA_ITRIG_INMUX[18]; /*!< Input mux register for DMA trigger inputs */
59 __I uint32_t RESERVED5[6];
60 __IO uint32_t DMA_INMUX[4]; /*!< Input mux register for DMA trigger inputs */
61 __I uint32_t RESERVED6[4];
62 __IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement ref clock */
63 __IO uint32_t FREQMEAS_TARGET; /*!< Clock selection for frequency measurement target clock */
64 } LPC_INMUX_T;
65
66 /* SCT input mux mapping selections for SCT0 inputs 0-6 */
67 typedef enum {
68 SCT0_INMUX_PIO0_2 = 0,
69 SCT0_INMUX_PIO0_3,
70 SCT0_INMUX_PIO0_17,
71 SCT0_INMUX_PIO0_30,
72 SCT0_INMUX_PIO1_6,
73 SCT0_INMUX_PIO1_7,
74 SCT0_INMUX_PIO1_12,
75 SCT0_INMUX_PIO1_13,
76 SCT0_INMUX_SCT1_OUT4,
77 SCT0_INMUX_SCT2_OUT4,
78 SCT0_INMUX_SCT2_OUT5,
79 SCT0_INMUX_ADC0_THCMP_IRQ,
80 SCT0_INMUX_ADC1_THCMP_IRQ,
81 SCT0_INMUX_ACMP0_OUT,
82 SCT0_INMUX_ACMP1_OUT,
83 SCT0_INMUX_ACMP2_OUT,
84 SCT0_INMUX_ACMP3_OUT,
85 SCT0_INMUX_SCTIPU_ABORT,
86 SCT0_INMUX_SCTIPU_SAMPLE0,
87 SCT0_INMUX_SCTIPU_SAMPLE1,
88 SCT0_INMUX_SCTIPU_SAMPLE2,
89 SCT0_INMUX_SCTIPU_SAMPLE3,
90 SCT0_INMUX_DEBUG_HALTED
91 } SCT0_INMUX_T;
92
93 /**
94 * @brief Selects an input source for SCT0 input 0 to 6
95 * @param input : SCT0 input to use, 0 - 6
96 * @param src : Source to map to the SCT input
97 * @return Nothing
98 */
Chip_INMUX_SelectSCT0Src(uint8_t input,SCT0_INMUX_T src)99 STATIC INLINE void Chip_INMUX_SelectSCT0Src(uint8_t input, SCT0_INMUX_T src)
100 {
101 LPC_INMUX->SCT0_INMUX[input] = (uint32_t) src;
102 }
103
104 /* SCT input mux mapping selections for SCT1 inputs 0-6 */
105 typedef enum {
106 SCT1_INMUX_PIO0_15 = 0,
107 SCT1_INMUX_PIO0_16,
108 SCT1_INMUX_PIO0_21,
109 SCT1_INMUX_PIO0_31,
110 SCT1_INMUX_PIO1_4,
111 SCT1_INMUX_PIO1_5,
112 SCT1_INMUX_PIO1_15,
113 SCT1_INMUX_PIO1_16,
114 SCT1_INMUX_SCT0_OUT4,
115 SCT1_INMUX_SCT3_OUT4,
116 SCT1_INMUX_SCT3_OUT5,
117 SCT1_INMUX_ADC0_THCMP_IRQ,
118 SCT1_INMUX_ADC1_THCMP_IRQ,
119 SCT1_INMUX_ACMP0_OUT,
120 SCT1_INMUX_ACMP1_OUT,
121 SCT1_INMUX_ACMP2_OUT,
122 SCT1_INMUX_ACMP3_OUT,
123 SCT1_INMUX_SCTIPU_ABORT,
124 SCT1_INMUX_SCTIPU_SAMPLE0,
125 SCT1_INMUX_SCTIPU_SAMPLE1,
126 SCT1_INMUX_SCTIPU_SAMPLE2,
127 SCT1_INMUX_SCTIPU_SAMPLE3,
128 SCT1_INMUX_DEBUG_HALTED
129 } SCT1_INMUX_T;
130
131 /**
132 * @brief Selects an input source for SCT1 input 0 to 6
133 * @param input : SCT1 input to use, 0 - 6
134 * @param src : Source to map to the SCT input
135 * @return Nothing
136 */
Chip_INMUX_SelectSCT1Src(uint8_t input,SCT1_INMUX_T src)137 STATIC INLINE void Chip_INMUX_SelectSCT1Src(uint8_t input, SCT1_INMUX_T src)
138 {
139 LPC_INMUX->SCT1_INMUX[input] = (uint32_t) src;
140 }
141
142 /* SCT input mux mapping selections for SCT2 inputs 0-2 */
143 typedef enum {
144 SCT2_INMUX_PIO0_4 = 0,
145 SCT2_INMUX_PIO0_27,
146 SCT2_INMUX_PIO1_18,
147 SCT2_INMUX_PIO1_19,
148 SCT2_INMUX_SCT0_OUT4,
149 SCT2_INMUX_SCT0_OUT5,
150 SCT2_INMUX_SCT0_OUT7,
151 SCT2_INMUX_SCT0_OUT8,
152 SCT2_INMUX_ADC0_THCMP_IRQ,
153 SCT2_INMUX_ADC1_THCMP_IRQ,
154 SCT2_INMUX_ACMP0_OUT,
155 SCT2_INMUX_ACMP1_OUT,
156 SCT2_INMUX_ACMP2_OUT,
157 SCT2_INMUX_ACMP3_OUT,
158 SCT2_INMUX_SCTIPU_ABORT,
159 SCT2_INMUX_SCTIPU_SAMPLE0,
160 SCT2_INMUX_SCTIPU_SAMPLE1,
161 SCT2_INMUX_SCTIPU_SAMPLE2,
162 SCT2_INMUX_SCTIPU_SAMPLE3,
163 SCT2_INMUX_USB_FRAME_TOGGLE,
164 SCT2_INMUX_DEBUG_HALTED
165 } SCT2_INMUX_T;
166
167 /**
168 * @brief Selects an input source for SCT2 input 0 to 2
169 * @param input : SCT2 input to use, 0 - 2
170 * @param src : Source to map to the SCT input
171 * @return Nothing
172 */
Chip_INMUX_SelectSCT2Src(uint8_t input,SCT2_INMUX_T src)173 STATIC INLINE void Chip_INMUX_SelectSCT2Src(uint8_t input, SCT2_INMUX_T src)
174 {
175 LPC_INMUX->SCT2_INMUX[input] = (uint32_t) src;
176 }
177
178 /* SCT input mux mapping selections for SCT3 inputs 0-2 */
179 typedef enum {
180 SCT3_INMUX_PIO0_7 = 0,
181 SCT3_INMUX_PIO1_11,
182 SCT3_INMUX_PIO1_21,
183 SCT3_INMUX_PIO1_22,
184 SCT3_INMUX_SCT1_OUT4,
185 SCT3_INMUX_SCT1_OUT5,
186 SCT3_INMUX_SCT1_OUT7,
187 SCT3_INMUX_SCT1_OUT8,
188 SCT3_INMUX_ADC0_THCMP_IRQ,
189 SCT3_INMUX_ADC1_THCMP_IRQ,
190 SCT3_INMUX_ACMP0_OUT,
191 SCT3_INMUX_ACMP1_OUT,
192 SCT3_INMUX_ACMP2_OUT,
193 SCT3_INMUX_ACMP3_OUT,
194 SCT3_INMUX_SCTIPU_ABORT3,
195 SCT3_INMUX_SCTIPU_SAMPLE0,
196 SCT3_INMUX_SCTIPU_SAMPLE1,
197 SCT3_INMUX_SCTIPU_SAMPLE2,
198 SCT3_INMUX_SCTIPU_SAMPLE3,
199 SCT3_INMUX_USB_FRAME_TOGGLE,
200 SCT3_INMUX_DEBUG_HALTED
201 } SCT3_INMUX_T;
202
203 /**
204 * @brief Selects an input source for SCT3 input 0 to 2
205 * @param input : SCT3 input to use, 0 - 2
206 * @param src : Source to map to the SCT input
207 * @return Nothing
208 */
Chip_INMUX_SelectSCT3Src(uint8_t input,SCT3_INMUX_T src)209 STATIC INLINE void Chip_INMUX_SelectSCT3Src(uint8_t input, SCT3_INMUX_T src)
210 {
211 LPC_INMUX->SCT3_INMUX[input] = (uint32_t) src;
212 }
213
214 /**
215 * @brief GPIO Pin Interrupt Pin Select (sets PINTSEL register)
216 * @param pintSel : GPIO PINTSEL interrupt, should be: 0 to 7
217 * @param portNum : GPIO port number interrupt, should be: 0 to 1
218 * @param pinNum : GPIO pin number Interrupt, should be: 0 to 31
219 * @return Nothing
220 */
Chip_INMUX_PinIntSel(uint8_t pintSel,uint8_t portNum,uint8_t pinNum)221 STATIC INLINE void Chip_INMUX_PinIntSel(uint8_t pintSel, uint8_t portNum, uint8_t pinNum)
222 {
223 LPC_INMUX->PINTSEL[pintSel] = (portNum * 32) + pinNum;
224 }
225
226 /* DMA triggers that can mapped to DMA channels */
227 typedef enum {
228 DMATRIG_ADC0_SEQA_IRQ = 0, /*!< ADC0 sequencer A interrupt as trigger */
229 DMATRIG_ADC0_SEQB_IRQ, /*!< ADC0 sequencer B interrupt as trigger */
230 DMATRIG_ADC1_SEQA_IRQ, /*!< ADC1 sequencer A interrupt as trigger */
231 DMATRIG_ADC1_SEQB_IRQ, /*!< ADC1 sequencer B interrupt as trigger */
232 DMATRIG_SCT0_DMA0, /*!< SCT 0, DMA 0 as trigger */
233 DMATRIG_SCT0_DMA1, /*!< SCT 1, DMA 1 as trigger */
234 DMATRIG_SCT1_DMA0, /*!< SCT 0, DMA 0 as trigger */
235 DMATRIG_SCT1_DMA1, /*!< SCT 1, DMA 1 as trigger */
236 DMATRIG_SCT2_DMA0, /*!< SCT 2, DMA 0 as trigger */
237 DMATRIG_SCT2_DMA1, /*!< SCT 2, DMA 1 as trigger */
238 DMATRIG_SCT3_DMA0, /*!< SCT 3, DMA 0 as trigger */
239 DMATRIG_SCT3_DMA1, /*!< SCT 3, DMA 1 as trigger */
240 DMATRIG_ACMP0_OUT, /*!< Analog comparator 0 output as trigger */
241 DMATRIG_ACMP1_OUT, /*!< Analog comparator 1 output as trigger */
242 DMATRIG_ACMP2_OUT, /*!< Analog comparator 2 output as trigger */
243 DMATRIG_ACMP3_OUT, /*!< Analog comparator 3 output as trigger */
244 DMATRIG_OUTMUX0, /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */
245 DMATRIG_OUTMUX1, /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */
246 DMATRIG_OUTMUX2, /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */
247 DMATRIG_OUTMUX3 /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */
248 } DMA_TRIGSRC_T;
249
250 /**
251 * @brief Select a trigger source for a DMA channel
252 * @param ch : DMA channel number
253 * @param trig : Trigger source for the DMA channel
254 * @return Nothing
255 */
Chip_INMUX_SetDMATrigger(uint8_t ch,DMA_TRIGSRC_T trig)256 STATIC INLINE void Chip_INMUX_SetDMATrigger(uint8_t ch, DMA_TRIGSRC_T trig)
257 {
258 LPC_INMUX->DMA_ITRIG_INMUX[ch] = (uint32_t) trig;
259 }
260
261 /**
262 * @brief Selects a DMA trigger source for the DMATRIG_OUTMUXn IDs
263 * @param index : Select 0 to 3 to sets the source for DMATRIG_OUTMUX0 to DMATRIG_OUTMUX3
264 * @param dmaCh : DMA channel to select for DMATRIG_OUTMUXn source
265 * @return Nothing
266 * @note This function sets the DMA trigger (out) source used with the DMATRIG_OUTMUXn
267 * trigger source.
268 */
Chip_INMUX_SetDMAOutMux(uint8_t index,uint8_t dmaCh)269 STATIC INLINE void Chip_INMUX_SetDMAOutMux(uint8_t index, uint8_t dmaCh)
270 {
271 LPC_INMUX->DMA_INMUX[index] = (uint32_t) dmaCh;
272 }
273
274 /* Freqeuency mearure reference and target clock sources */
275 typedef enum {
276 FREQMSR_MAIN_OSC = 0, /*!< System oscillator */
277 FREQMSR_IRC, /*!< Internal RC (IRC) oscillator */
278 FREQMSR_WDOSC, /*!< Watchdog oscillator */
279 FREQMSR_32KHZOSC, /*!< 32KHz (RTC) oscillator rate */
280 FREQMSR_USB_FTOGGLE, /*!< USB FTOGGLE rate */
281 FREQMSR_PIO0_5, /*!< External pin PIO0_5 as input rate */
282 FREQMSR_PIO0_19, /*!< External pin PIO0_19 as input rate */
283 FREQMSR_PIO0_30, /*!< External pin PIO0_30 as input rate */
284 FREQMSR_PIO1_27 /*!< External pin PIO1_27 as input rate */
285 } FREQMSR_SRC_T;
286
287 /**
288 * @brief Selects a reference clock used with the frequency measure function
289 * @param ref : Frequency measure function reference clock
290 * @return Nothing
291 */
Chip_INMUX_SetFreqMeasRefClock(FREQMSR_SRC_T ref)292 STATIC INLINE void Chip_INMUX_SetFreqMeasRefClock(FREQMSR_SRC_T ref)
293 {
294 LPC_INMUX->FREQMEAS_REF = (uint32_t) ref;
295 }
296
297 /**
298 * @brief Selects a target clock used with the frequency measure function
299 * @param targ : Frequency measure function reference clock
300 * @return Nothing
301 */
Chip_INMUX_SetFreqMeasTargClock(FREQMSR_SRC_T targ)302 STATIC INLINE void Chip_INMUX_SetFreqMeasTargClock(FREQMSR_SRC_T targ)
303 {
304 LPC_INMUX->FREQMEAS_TARGET = (uint32_t) targ;
305 }
306
307 /**
308 * @}
309 */
310
311 #ifdef __cplusplus
312 }
313 #endif
314
315 #endif /* __INMUX_15XX_H_ */
316