1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2022, HiSilicon Limited 4 */ 5 6 #ifndef LPC_UART_H 7 #define LPC_UART_H 8 9 #include <types_ext.h> 10 #include <drivers/serial.h> 11 12 #define UART_SEND_LOOP_MAX 1000000 13 #define UART_THR 0x00 14 #define UART_LSR 0x05 15 16 #define UART_USR_BUS 0x01 17 18 #define LPC_BASE 0x201190000 19 #define LPC_SIZE 0x1000000 20 21 #define LPC_START_REG_OFFSET (0x00) 22 #define LPC_OP_STATUS_REG_OFFSET (0x04) 23 #define LPC_IRQ_ST_REG_OFFSET (0x08) 24 #define LPC_OP_LEN_REG_OFFSET (0x10) 25 #define LPC_CMD_REG_OFFSET (0x14) 26 #define LPC_FWH_ID_MSIZE_REG_OFFSET (0x18) 27 #define LPC_ADDR_REG_OFFSET (0x20) 28 #define LPC_WDATA_REG_OFFSET (0x24) 29 #define LPC_RDATA_REG_OFFSET (0x28) 30 #define LPC_LONG_CNT_REG_OFFSET (0x30) 31 #define LPC_TX_FIFO_ST_REG_OFFSET (0x50) 32 #define LPC_RX_FIFO_ST_REG_OFFSET (0x54) 33 #define LPC_TIME_OUT_REG_OFFSET (0x58) 34 #define LPC_SIRQ_CTRL0_REG_OFFSET (0x80) 35 #define LPC_SIRQ_CTRL1_REG_OFFSET (0x84) 36 #define LPC_SIRQ_INT_REG_OFFSET (0x90) 37 #define LPC_SIRQ_INT_MASK_REG_OFFSET (0x94) 38 #define LPC_SIRQ_STAT_REG_OFFSET (0xa0) 39 40 #define LPC_SINGLE_READ (0x8) 41 #define LPC_SINGLE_WRITE (0x9) 42 #define LPC_IRQ_ST_ON (0x2) 43 #define LPC_RADTA_LEN (0x40) 44 45 struct lpc_uart_data { 46 struct io_pa_va base; 47 struct serial_chip chip; 48 }; 49 50 void lpc_uart_init(struct lpc_uart_data *pd, paddr_t base, 51 uint32_t uart_clk, uint32_t baud_rate); 52 53 #endif /* LPC_UART_H */ 54