1 /*
2 * @brief LPC15xx Pin Interrupt and Pattern Match Registers and driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2013
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __PININT_15XX_H_
33 #define __PININT_15XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /** @defgroup PININT_15XX CHIP: LPC15xx Pin Interrupt driver
40 * @ingroup CHIP_15XX_Drivers
41 * @{
42 */
43
44 /**
45 * @brief LPC15xx Pin Interrupt and Pattern Match register block structure
46 */
47 typedef struct { /*!< PIN_INT Structure */
48 __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
49 __IO uint32_t IENR; /*!< Pin Interrupt Enable (Rising) register */
50 __IO uint32_t SIENR; /*!< Set Pin Interrupt Enable (Rising) register */
51 __IO uint32_t CIENR; /*!< Clear Pin Interrupt Enable (Rising) register */
52 __IO uint32_t IENF; /*!< Pin Interrupt Enable Falling Edge / Active Level register */
53 __IO uint32_t SIENF; /*!< Set Pin Interrupt Enable Falling Edge / Active Level register */
54 __IO uint32_t CIENF; /*!< Clear Pin Interrupt Enable Falling Edge / Active Level address */
55 __IO uint32_t RISE; /*!< Pin Interrupt Rising Edge register */
56 __IO uint32_t FALL; /*!< Pin Interrupt Falling Edge register */
57 __IO uint32_t IST; /*!< Pin Interrupt Status register */
58 } LPC_PIN_INT_T;
59
60 /**
61 * LPC15xx Pin Interrupt channel values
62 */
63 #define PININTCH0 (1 << 0)
64 #define PININTCH1 (1 << 1)
65 #define PININTCH2 (1 << 2)
66 #define PININTCH3 (1 << 3)
67 #define PININTCH4 (1 << 4)
68 #define PININTCH5 (1 << 5)
69 #define PININTCH6 (1 << 6)
70 #define PININTCH7 (1 << 7)
71 #define PININTCH(ch) (1 << (ch))
72
73 /**
74 * @brief Initialize Pin interrupt block
75 * @param pPININT : The base address of Pin interrupt block
76 * @return Nothing
77 * @note This function should be used after the Chip_GPIO_Init() function.
78 */
Chip_PININT_Init(LPC_PIN_INT_T * pPININT)79 STATIC INLINE void Chip_PININT_Init(LPC_PIN_INT_T *pPININT)
80 {
81 Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_PININT);
82 Chip_SYSCTL_PeriphReset(RESET_PININT);
83 }
84
85 /**
86 * @brief De-Initialize Pin interrupt block
87 * @param pPININT : The base address of Pin interrupt block
88 * @return Nothing
89 */
Chip_PININT_DeInit(LPC_PIN_INT_T * pPININT)90 STATIC INLINE void Chip_PININT_DeInit(LPC_PIN_INT_T *pPININT)
91 {
92 Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_PININT);
93 }
94
95 /**
96 * @brief Configure the pins as edge sensitive in Pin interrupt block
97 * @param pPININT : The base address of Pin interrupt block
98 * @param pins : Pins (ORed value of PININTCH*)
99 * @return Nothing
100 */
Chip_PININT_SetPinModeEdge(LPC_PIN_INT_T * pPININT,uint32_t pins)101 STATIC INLINE void Chip_PININT_SetPinModeEdge(LPC_PIN_INT_T *pPININT, uint32_t pins)
102 {
103 pPININT->ISEL &= ~pins;
104 }
105
106 /**
107 * @brief Configure the pins as level sensitive in Pin interrupt block
108 * @param pPININT : The base address of Pin interrupt block
109 * @param pins : Pins (ORed value of PININTCH*)
110 * @return Nothing
111 */
Chip_PININT_SetPinModeLevel(LPC_PIN_INT_T * pPININT,uint32_t pins)112 STATIC INLINE void Chip_PININT_SetPinModeLevel(LPC_PIN_INT_T *pPININT, uint32_t pins)
113 {
114 pPININT->ISEL |= pins;
115 }
116
117 /**
118 * @brief Return current PININT rising edge or high level interrupt enable state
119 * @param pPININT : The base address of Pin interrupt block
120 * @return A bifield containing the high edge/level interrupt enables for each
121 * interrupt. Bit 0 = PININT0, 1 = PININT1, etc.
122 * For each bit, a 0 means the high edge/level interrupt is disabled, while a 1
123 * means it's enabled.
124 */
Chip_PININT_GetHighEnabled(LPC_PIN_INT_T * pPININT)125 STATIC INLINE uint32_t Chip_PININT_GetHighEnabled(LPC_PIN_INT_T *pPININT)
126 {
127 return pPININT->IENR;
128 }
129
130 /**
131 * @brief Enable high edge/level PININT interrupts for pins
132 * @param pPININT : The base address of Pin interrupt block
133 * @param pins : Pins to enable (ORed value of PININTCH*)
134 * @return Nothing
135 */
Chip_PININT_EnableIntHigh(LPC_PIN_INT_T * pPININT,uint32_t pins)136 STATIC INLINE void Chip_PININT_EnableIntHigh(LPC_PIN_INT_T *pPININT, uint32_t pins)
137 {
138 pPININT->SIENR = pins;
139 }
140
141 /**
142 * @brief Disable high edge/level PININT interrupts for pins
143 * @param pPININT : The base address of Pin interrupt block
144 * @param pins : Pins to disable (ORed value of PININTCH*)
145 * @return Nothing
146 */
Chip_PININT_DisableIntHigh(LPC_PIN_INT_T * pPININT,uint32_t pins)147 STATIC INLINE void Chip_PININT_DisableIntHigh(LPC_PIN_INT_T *pPININT, uint32_t pins)
148 {
149 pPININT->CIENR = pins;
150 }
151
152 /**
153 * @brief Return current PININT falling edge or low level interrupt enable state
154 * @param pPININT : The base address of Pin interrupt block
155 * @return A bifield containing the low edge/level interrupt enables for each
156 * interrupt. Bit 0 = PININT0, 1 = PININT1, etc.
157 * For each bit, a 0 means the low edge/level interrupt is disabled, while a 1
158 * means it's enabled.
159 */
Chip_PININT_GetLowEnabled(LPC_PIN_INT_T * pPININT)160 STATIC INLINE uint32_t Chip_PININT_GetLowEnabled(LPC_PIN_INT_T *pPININT)
161 {
162 return pPININT->IENF;
163 }
164
165 /**
166 * @brief Enable low edge/level PININT interrupts for pins
167 * @param pPININT : The base address of Pin interrupt block
168 * @param pins : Pins to enable (ORed value of PININTCH*)
169 * @return Nothing
170 */
Chip_PININT_EnableIntLow(LPC_PIN_INT_T * pPININT,uint32_t pins)171 STATIC INLINE void Chip_PININT_EnableIntLow(LPC_PIN_INT_T *pPININT, uint32_t pins)
172 {
173 pPININT->SIENF = pins;
174 }
175
176 /**
177 * @brief Disable low edge/level PININT interrupts for pins
178 * @param pPININT : The base address of Pin interrupt block
179 * @param pins : Pins to disable (ORed value of PININTCH*)
180 * @return Nothing
181 */
Chip_PININT_DisableIntLow(LPC_PIN_INT_T * pPININT,uint32_t pins)182 STATIC INLINE void Chip_PININT_DisableIntLow(LPC_PIN_INT_T *pPININT, uint32_t pins)
183 {
184 pPININT->CIENF = pins;
185 }
186
187 /**
188 * @brief Return pin states that have a detected latched high edge (RISE) state
189 * @param pPININT : The base address of Pin interrupt block
190 * @return PININT states (bit n = high) with a latched rise state detected
191 */
Chip_PININT_GetRiseStates(LPC_PIN_INT_T * pPININT)192 STATIC INLINE uint32_t Chip_PININT_GetRiseStates(LPC_PIN_INT_T *pPININT)
193 {
194 return pPININT->RISE;
195 }
196
197 /**
198 * @brief Clears pin states that had a latched high edge (RISE) state
199 * @param pPININT : The base address of Pin interrupt block
200 * @param pins : Pins with latched states to clear
201 * @return Nothing
202 */
Chip_PININT_ClearRiseStates(LPC_PIN_INT_T * pPININT,uint32_t pins)203 STATIC INLINE void Chip_PININT_ClearRiseStates(LPC_PIN_INT_T *pPININT, uint32_t pins)
204 {
205 pPININT->RISE = pins;
206 }
207
208 /**
209 * @brief Return pin states that have a detected latched falling edge (FALL) state
210 * @param pPININT : The base address of Pin interrupt block
211 * @return PININT states (bit n = high) with a latched rise state detected
212 */
Chip_PININT_GetFallStates(LPC_PIN_INT_T * pPININT)213 STATIC INLINE uint32_t Chip_PININT_GetFallStates(LPC_PIN_INT_T *pPININT)
214 {
215 return pPININT->FALL;
216 }
217
218 /**
219 * @brief Clears pin states that had a latched falling edge (FALL) state
220 * @param pPININT : The base address of Pin interrupt block
221 * @param pins : Pins with latched states to clear
222 * @return Nothing
223 */
Chip_PININT_ClearFallStates(LPC_PIN_INT_T * pPININT,uint32_t pins)224 STATIC INLINE void Chip_PININT_ClearFallStates(LPC_PIN_INT_T *pPININT, uint32_t pins)
225 {
226 pPININT->FALL = pins;
227 }
228
229 /**
230 * @brief Get interrupt status from Pin interrupt block
231 * @param pPININT : The base address of Pin interrupt block
232 * @return Interrupt status (bit n for PININTn = high means interrupt ie pending)
233 */
Chip_PININT_GetIntStatus(LPC_PIN_INT_T * pPININT)234 STATIC INLINE uint32_t Chip_PININT_GetIntStatus(LPC_PIN_INT_T *pPININT)
235 {
236 return pPININT->IST;
237 }
238
239 /**
240 * @brief Clear interrupt status in Pin interrupt block
241 * @param pPININT : The base address of Pin interrupt block
242 * @param pins : Pin interrupts to clear (ORed value of PININTCH*)
243 * @return Nothing
244 */
Chip_PININT_ClearIntStatus(LPC_PIN_INT_T * pPININT,uint32_t pins)245 STATIC INLINE void Chip_PININT_ClearIntStatus(LPC_PIN_INT_T *pPININT, uint32_t pins)
246 {
247 pPININT->IST = pins;
248 }
249
250 /**
251 * @}
252 */
253
254 #ifdef __cplusplus
255 }
256 #endif
257
258 #endif /* __PININT_15XX_H_ */
259