1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_CATALOG_H 8 #define _DPU_HW_CATALOG_H 9 10 #include <linux/kernel.h> 11 #include <linux/bug.h> 12 #include <linux/bitmap.h> 13 #include <linux/err.h> 14 15 /** 16 * Max hardware block count: For ex: max 12 SSPP pipes or 17 * 5 ctl paths. In all cases, it can have max 12 hardware blocks 18 * based on current design 19 */ 20 #define MAX_BLOCKS 12 21 22 #define DPU_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28) |\ 23 ((MINOR & 0xFFF) << 16) |\ 24 (STEP & 0xFFFF)) 25 26 #define DPU_HW_MAJOR(rev) ((rev) >> 28) 27 #define DPU_HW_MINOR(rev) (((rev) >> 16) & 0xFFF) 28 #define DPU_HW_STEP(rev) ((rev) & 0xFFFF) 29 #define DPU_HW_MAJOR_MINOR(rev) ((rev) >> 16) 30 31 #define IS_DPU_MAJOR_MINOR_SAME(rev1, rev2) \ 32 (DPU_HW_MAJOR_MINOR((rev1)) == DPU_HW_MAJOR_MINOR((rev2))) 33 34 #define DPU_HW_VER_170 DPU_HW_VER(1, 7, 0) /* 8996 v1.0 */ 35 #define DPU_HW_VER_171 DPU_HW_VER(1, 7, 1) /* 8996 v2.0 */ 36 #define DPU_HW_VER_172 DPU_HW_VER(1, 7, 2) /* 8996 v3.0 */ 37 #define DPU_HW_VER_300 DPU_HW_VER(3, 0, 0) /* 8998 v1.0 */ 38 #define DPU_HW_VER_301 DPU_HW_VER(3, 0, 1) /* 8998 v1.1 */ 39 #define DPU_HW_VER_400 DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */ 40 #define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */ 41 #define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */ 42 #define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sm8150 v1.0 */ 43 #define DPU_HW_VER_501 DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */ 44 #define DPU_HW_VER_510 DPU_HW_VER(5, 1, 1) /* sc8180 */ 45 #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */ 46 #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ 47 #define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0) /* sm6115|sm4250 */ 48 #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ 49 #define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */ 50 #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ 51 #define DPU_HW_VER_800 DPU_HW_VER(8, 0, 0) /* sc8280xp */ 52 #define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */ 53 #define DPU_HW_VER_900 DPU_HW_VER(9, 0, 0) /* sm8550 */ 54 55 #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) 56 #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) 57 #define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400) 58 #define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410) 59 #define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500) 60 #define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620) 61 #define IS_SC7280_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_720) 62 63 #define DPU_HW_BLK_NAME_LEN 16 64 65 #define MAX_IMG_WIDTH 0x3fff 66 #define MAX_IMG_HEIGHT 0x3fff 67 68 #define CRTC_DUAL_MIXERS 2 69 70 #define MAX_XIN_COUNT 16 71 72 /** 73 * Supported UBWC feature versions 74 */ 75 enum { 76 DPU_HW_UBWC_VER_10 = 0x100, 77 DPU_HW_UBWC_VER_20 = 0x200, 78 DPU_HW_UBWC_VER_30 = 0x300, 79 DPU_HW_UBWC_VER_40 = 0x400, 80 }; 81 82 /** 83 * MDP TOP BLOCK features 84 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe 85 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats 86 * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression. 87 * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth 88 * compression initial revision 89 * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 90 * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results 91 * in a failure 92 * @DPU_MDP_MAX Maximum value 93 94 */ 95 enum { 96 DPU_MDP_PANIC_PER_PIPE = 0x1, 97 DPU_MDP_10BIT_SUPPORT, 98 DPU_MDP_BWC, 99 DPU_MDP_UBWC_1_0, 100 DPU_MDP_UBWC_1_5, 101 DPU_MDP_AUDIO_SELECT, 102 DPU_MDP_PERIPH_0_REMOVED, 103 DPU_MDP_MAX 104 }; 105 106 /** 107 * SSPP sub-blocks/features 108 * @DPU_SSPP_SRC Src and fetch part of the pipes, 109 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support 110 * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support 111 * @DPU_SSPP_SCALER_QSEED3LITE, QSEED3 Lite alogorithm support 112 * @DPU_SSPP_SCALER_QSEED4, QSEED4 algorithm support 113 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes 114 * @DPU_SSPP_CSC, Support of Color space converion 115 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion 116 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer 117 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq 118 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control 119 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect 120 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support 121 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support 122 * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper 123 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec 124 * @DPU_SSPP_CDP Supports client driven prefetch 125 * @DPU_SSPP_INLINE_ROTATION Support inline rotation 126 * @DPU_SSPP_MAX maximum value 127 */ 128 enum { 129 DPU_SSPP_SRC = 0x1, 130 DPU_SSPP_SCALER_QSEED2, 131 DPU_SSPP_SCALER_QSEED3, 132 DPU_SSPP_SCALER_QSEED3LITE, 133 DPU_SSPP_SCALER_QSEED4, 134 DPU_SSPP_SCALER_RGB, 135 DPU_SSPP_CSC, 136 DPU_SSPP_CSC_10BIT, 137 DPU_SSPP_CURSOR, 138 DPU_SSPP_QOS, 139 DPU_SSPP_QOS_8LVL, 140 DPU_SSPP_EXCL_RECT, 141 DPU_SSPP_SMART_DMA_V1, 142 DPU_SSPP_SMART_DMA_V2, 143 DPU_SSPP_TS_PREFILL, 144 DPU_SSPP_TS_PREFILL_REC1, 145 DPU_SSPP_CDP, 146 DPU_SSPP_INLINE_ROTATION, 147 DPU_SSPP_MAX 148 }; 149 150 /* 151 * MIXER sub-blocks/features 152 * @DPU_MIXER_LAYER Layer mixer layer blend configuration, 153 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration 154 * @DPU_MIXER_GC Gamma correction block 155 * @DPU_DIM_LAYER Layer mixer supports dim layer 156 * @DPU_MIXER_COMBINED_ALPHA Layer mixer has combined alpha register 157 * @DPU_MIXER_MAX maximum value 158 */ 159 enum { 160 DPU_MIXER_LAYER = 0x1, 161 DPU_MIXER_SOURCESPLIT, 162 DPU_MIXER_GC, 163 DPU_DIM_LAYER, 164 DPU_MIXER_COMBINED_ALPHA, 165 DPU_MIXER_MAX 166 }; 167 168 /** 169 * DSPP sub-blocks 170 * @DPU_DSPP_PCC Panel color correction block 171 * @DPU_DSPP_GC Gamma correction block 172 */ 173 enum { 174 DPU_DSPP_PCC = 0x1, 175 DPU_DSPP_GC, 176 DPU_DSPP_MAX 177 }; 178 179 /** 180 * PINGPONG sub-blocks 181 * @DPU_PINGPONG_TE Tear check block 182 * @DPU_PINGPONG_TE2 Additional tear check block for split pipes 183 * @DPU_PINGPONG_SPLIT PP block supports split fifo 184 * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo 185 * @DPU_PINGPONG_DITHER, Dither blocks 186 * @DPU_PINGPONG_MAX 187 */ 188 enum { 189 DPU_PINGPONG_TE = 0x1, 190 DPU_PINGPONG_TE2, 191 DPU_PINGPONG_SPLIT, 192 DPU_PINGPONG_SLAVE, 193 DPU_PINGPONG_DITHER, 194 DPU_PINGPONG_MAX 195 }; 196 197 /** 198 * CTL sub-blocks 199 * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display 200 * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) 201 * @DPU_CTL_VM_CFG: CTL config to support multiple VMs 202 * @DPU_CTL_HAS_LAYER_EXT4: CTL has the CTL_LAYER_EXT4 register 203 * @DPU_CTL_MAX 204 */ 205 enum { 206 DPU_CTL_SPLIT_DISPLAY = 0x1, 207 DPU_CTL_ACTIVE_CFG, 208 DPU_CTL_FETCH_ACTIVE, 209 DPU_CTL_VM_CFG, 210 DPU_CTL_HAS_LAYER_EXT4, 211 DPU_CTL_MAX 212 }; 213 214 /** 215 * INTF sub-blocks 216 * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which 217 * pixel data arrives to this INTF 218 * @DPU_INTF_TE INTF block has TE configuration support 219 * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate 220 than video timing 221 * @DPU_INTF_MAX 222 */ 223 enum { 224 DPU_INTF_INPUT_CTRL = 0x1, 225 DPU_INTF_TE, 226 DPU_DATA_HCTL_EN, 227 DPU_INTF_MAX 228 }; 229 230 /** 231 * WB sub-blocks and features 232 * @DPU_WB_LINE_MODE Writeback module supports line/linear mode 233 * @DPU_WB_BLOCK_MODE Writeback module supports block mode read 234 * @DPU_WB_CHROMA_DOWN, Writeback chroma down block, 235 * @DPU_WB_DOWNSCALE, Writeback integer downscaler, 236 * @DPU_WB_DITHER, Dither block 237 * @DPU_WB_TRAFFIC_SHAPER, Writeback traffic shaper bloc 238 * @DPU_WB_UBWC, Writeback Universal bandwidth compression 239 * @DPU_WB_YUV_CONFIG Writeback supports output of YUV colorspace 240 * @DPU_WB_PIPE_ALPHA Writeback supports pipe alpha 241 * @DPU_WB_XY_ROI_OFFSET Writeback supports x/y-offset of out ROI in 242 * the destination image 243 * @DPU_WB_QOS, Writeback supports QoS control, danger/safe/creq 244 * @DPU_WB_QOS_8LVL, Writeback supports 8-level QoS control 245 * @DPU_WB_CDP Writeback supports client driven prefetch 246 * @DPU_WB_INPUT_CTRL Writeback supports from which pp block input pixel 247 * data arrives. 248 * @DPU_WB_CROP CWB supports cropping 249 * @DPU_WB_MAX maximum value 250 */ 251 enum { 252 DPU_WB_LINE_MODE = 0x1, 253 DPU_WB_BLOCK_MODE, 254 DPU_WB_UBWC, 255 DPU_WB_YUV_CONFIG, 256 DPU_WB_PIPE_ALPHA, 257 DPU_WB_XY_ROI_OFFSET, 258 DPU_WB_QOS, 259 DPU_WB_QOS_8LVL, 260 DPU_WB_CDP, 261 DPU_WB_INPUT_CTRL, 262 DPU_WB_CROP, 263 DPU_WB_MAX 264 }; 265 266 /** 267 * VBIF sub-blocks and features 268 * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit 269 * @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap 270 * @DPU_VBIF_MAX maximum value 271 */ 272 enum { 273 DPU_VBIF_QOS_OTLIM = 0x1, 274 DPU_VBIF_QOS_REMAP, 275 DPU_VBIF_MAX 276 }; 277 278 /** 279 * DSC features 280 * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets 281 * the pixel output from this DSC. 282 */ 283 enum { 284 DPU_DSC_OUTPUT_CTRL = 0x1, 285 }; 286 287 /** 288 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU 289 * @name: string name for debug purposes 290 * @id: enum identifying this block 291 * @base: register base offset to mdss 292 * @len: length of hardware block 293 * @features bit mask identifying sub-blocks/features 294 */ 295 #define DPU_HW_BLK_INFO \ 296 char name[DPU_HW_BLK_NAME_LEN]; \ 297 u32 id; \ 298 u32 base; \ 299 u32 len; \ 300 unsigned long features 301 302 /** 303 * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU 304 * @name: string name for debug purposes 305 * @id: enum identifying this sub-block 306 * @base: offset of this sub-block relative to the block 307 * offset 308 * @len register block length of this sub-block 309 */ 310 #define DPU_HW_SUBBLK_INFO \ 311 char name[DPU_HW_BLK_NAME_LEN]; \ 312 u32 id; \ 313 u32 base; \ 314 u32 len 315 316 /** 317 * struct dpu_src_blk: SSPP part of the source pipes 318 * @info: HW register and features supported by this sub-blk 319 */ 320 struct dpu_src_blk { 321 DPU_HW_SUBBLK_INFO; 322 }; 323 324 /** 325 * struct dpu_scaler_blk: Scaler information 326 * @info: HW register and features supported by this sub-blk 327 * @version: qseed block revision 328 */ 329 struct dpu_scaler_blk { 330 DPU_HW_SUBBLK_INFO; 331 u32 version; 332 }; 333 334 struct dpu_csc_blk { 335 DPU_HW_SUBBLK_INFO; 336 }; 337 338 /** 339 * struct dpu_pp_blk : Pixel processing sub-blk information 340 * @info: HW register and features supported by this sub-blk 341 * @version: HW Algorithm version 342 */ 343 struct dpu_pp_blk { 344 DPU_HW_SUBBLK_INFO; 345 u32 version; 346 }; 347 348 /** 349 * enum dpu_qos_lut_usage - define QoS LUT use cases 350 */ 351 enum dpu_qos_lut_usage { 352 DPU_QOS_LUT_USAGE_LINEAR, 353 DPU_QOS_LUT_USAGE_MACROTILE, 354 DPU_QOS_LUT_USAGE_NRT, 355 DPU_QOS_LUT_USAGE_MAX, 356 }; 357 358 /** 359 * struct dpu_qos_lut_entry - define QoS LUT table entry 360 * @fl: fill level, or zero on last entry to indicate default lut 361 * @lut: lut to use if equal to or less than fill level 362 */ 363 struct dpu_qos_lut_entry { 364 u32 fl; 365 u64 lut; 366 }; 367 368 /** 369 * struct dpu_qos_lut_tbl - define QoS LUT table 370 * @nentry: number of entry in this table 371 * @entries: Pointer to table entries 372 */ 373 struct dpu_qos_lut_tbl { 374 u32 nentry; 375 const struct dpu_qos_lut_entry *entries; 376 }; 377 378 /** 379 * struct dpu_rotation_cfg - define inline rotation config 380 * @rot_maxheight: max pre rotated height allowed for rotation 381 * @rot_num_formats: number of elements in @rot_format_list 382 * @rot_format_list: list of supported rotator formats 383 */ 384 struct dpu_rotation_cfg { 385 u32 rot_maxheight; 386 size_t rot_num_formats; 387 const u32 *rot_format_list; 388 }; 389 390 /** 391 * struct dpu_caps - define DPU capabilities 392 * @max_mixer_width max layer mixer line width support. 393 * @max_mixer_blendstages max layer mixer blend stages or 394 * supported z order 395 * @qseed_type qseed2 or qseed3 support. 396 * @smart_dma_rev Supported version of SmartDMA feature. 397 * @ubwc_version UBWC feature version (0x0 for not supported) 398 * @has_src_split source split feature status 399 * @has_dim_layer dim layer feature status 400 * @has_idle_pc indicate if idle power collapse feature is supported 401 * @has_3d_merge indicate if 3D merge is supported 402 * @max_linewidth max linewidth for sspp 403 * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes 404 * @max_hdeci_exp max horizontal decimation supported (max is 2^value) 405 * @max_vdeci_exp max vertical decimation supported (max is 2^value) 406 */ 407 struct dpu_caps { 408 u32 max_mixer_width; 409 u32 max_mixer_blendstages; 410 u32 qseed_type; 411 u32 smart_dma_rev; 412 u32 ubwc_version; 413 bool has_src_split; 414 bool has_dim_layer; 415 bool has_idle_pc; 416 bool has_3d_merge; 417 /* SSPP limits */ 418 u32 max_linewidth; 419 u32 pixel_ram_size; 420 u32 max_hdeci_exp; 421 u32 max_vdeci_exp; 422 }; 423 424 /** 425 * struct dpu_sspp_sub_blks : SSPP sub-blocks 426 * common: Pointer to common configurations shared by sub blocks 427 * @creq_vblank: creq priority during vertical blanking 428 * @danger_vblank: danger priority during vertical blanking 429 * @maxdwnscale: max downscale ratio supported(without DECIMATION) 430 * @maxupscale: maxupscale ratio supported 431 * @smart_dma_priority: hw priority of rect1 of multirect pipe 432 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps 433 * @qseed_ver: qseed version 434 * @src_blk: 435 * @scaler_blk: 436 * @csc_blk: 437 * @hsic: 438 * @memcolor: 439 * @pcc_blk: 440 * @igc_blk: 441 * @format_list: Pointer to list of supported formats 442 * @num_formats: Number of supported formats 443 * @virt_format_list: Pointer to list of supported formats for virtual planes 444 * @virt_num_formats: Number of supported formats for virtual planes 445 * @dpu_rotation_cfg: inline rotation configuration 446 */ 447 struct dpu_sspp_sub_blks { 448 u32 creq_vblank; 449 u32 danger_vblank; 450 u32 maxdwnscale; 451 u32 maxupscale; 452 u32 smart_dma_priority; 453 u32 max_per_pipe_bw; 454 u32 qseed_ver; 455 struct dpu_src_blk src_blk; 456 struct dpu_scaler_blk scaler_blk; 457 struct dpu_pp_blk csc_blk; 458 struct dpu_pp_blk hsic_blk; 459 struct dpu_pp_blk memcolor_blk; 460 struct dpu_pp_blk pcc_blk; 461 struct dpu_pp_blk igc_blk; 462 463 const u32 *format_list; 464 u32 num_formats; 465 const u32 *virt_format_list; 466 u32 virt_num_formats; 467 const struct dpu_rotation_cfg *rotation_cfg; 468 }; 469 470 /** 471 * struct dpu_lm_sub_blks: information of mixer block 472 * @maxwidth: Max pixel width supported by this mixer 473 * @maxblendstages: Max number of blend-stages supported 474 * @blendstage_base: Blend-stage register base offset 475 * @gc: gamma correction block 476 */ 477 struct dpu_lm_sub_blks { 478 u32 maxwidth; 479 u32 maxblendstages; 480 u32 blendstage_base[MAX_BLOCKS]; 481 struct dpu_pp_blk gc; 482 }; 483 484 /** 485 * struct dpu_dspp_sub_blks: Information of DSPP block 486 * @gc : gamma correction block 487 * @pcc: pixel color correction block 488 */ 489 struct dpu_dspp_sub_blks { 490 struct dpu_pp_blk gc; 491 struct dpu_pp_blk pcc; 492 }; 493 494 struct dpu_pingpong_sub_blks { 495 struct dpu_pp_blk te; 496 struct dpu_pp_blk te2; 497 struct dpu_pp_blk dither; 498 }; 499 500 /** 501 * dpu_clk_ctrl_type - Defines top level clock control signals 502 */ 503 enum dpu_clk_ctrl_type { 504 DPU_CLK_CTRL_NONE, 505 DPU_CLK_CTRL_VIG0, 506 DPU_CLK_CTRL_VIG1, 507 DPU_CLK_CTRL_VIG2, 508 DPU_CLK_CTRL_VIG3, 509 DPU_CLK_CTRL_VIG4, 510 DPU_CLK_CTRL_RGB0, 511 DPU_CLK_CTRL_RGB1, 512 DPU_CLK_CTRL_RGB2, 513 DPU_CLK_CTRL_RGB3, 514 DPU_CLK_CTRL_DMA0, 515 DPU_CLK_CTRL_DMA1, 516 DPU_CLK_CTRL_DMA2, 517 DPU_CLK_CTRL_DMA3, 518 DPU_CLK_CTRL_DMA4, 519 DPU_CLK_CTRL_DMA5, 520 DPU_CLK_CTRL_CURSOR0, 521 DPU_CLK_CTRL_CURSOR1, 522 DPU_CLK_CTRL_INLINE_ROT0_SSPP, 523 DPU_CLK_CTRL_REG_DMA, 524 DPU_CLK_CTRL_WB2, 525 DPU_CLK_CTRL_MAX, 526 }; 527 528 /* struct dpu_clk_ctrl_reg : Clock control register 529 * @reg_off: register offset 530 * @bit_off: bit offset 531 */ 532 struct dpu_clk_ctrl_reg { 533 u32 reg_off; 534 u32 bit_off; 535 }; 536 537 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info 538 * @id: index identifying this block 539 * @base: register base offset to mdss 540 * @features bit mask identifying sub-blocks/features 541 * @highest_bank_bit: UBWC parameter 542 * @ubwc_swizzle: ubwc default swizzle setting 543 * @clk_ctrls clock control register definition 544 */ 545 struct dpu_mdp_cfg { 546 DPU_HW_BLK_INFO; 547 u32 highest_bank_bit; 548 u32 ubwc_swizzle; 549 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; 550 }; 551 552 /* struct dpu_ctl_cfg : MDP CTL instance info 553 * @id: index identifying this block 554 * @base: register base offset to mdss 555 * @features bit mask identifying sub-blocks/features 556 * @intr_start: interrupt index for CTL_START 557 */ 558 struct dpu_ctl_cfg { 559 DPU_HW_BLK_INFO; 560 s32 intr_start; 561 }; 562 563 /** 564 * struct dpu_sspp_cfg - information of source pipes 565 * @id: index identifying this block 566 * @base register offset of this block 567 * @features bit mask identifying sub-blocks/features 568 * @sblk: SSPP sub-blocks information 569 * @xin_id: bus client identifier 570 * @clk_ctrl clock control identifier 571 * @type sspp type identifier 572 */ 573 struct dpu_sspp_cfg { 574 DPU_HW_BLK_INFO; 575 const struct dpu_sspp_sub_blks *sblk; 576 u32 xin_id; 577 enum dpu_clk_ctrl_type clk_ctrl; 578 u32 type; 579 }; 580 581 /** 582 * struct dpu_lm_cfg - information of layer mixer blocks 583 * @id: index identifying this block 584 * @base register offset of this block 585 * @features bit mask identifying sub-blocks/features 586 * @sblk: LM Sub-blocks information 587 * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported 588 * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL 589 */ 590 struct dpu_lm_cfg { 591 DPU_HW_BLK_INFO; 592 const struct dpu_lm_sub_blks *sblk; 593 u32 pingpong; 594 u32 dspp; 595 unsigned long lm_pair_mask; 596 }; 597 598 /** 599 * struct dpu_dspp_cfg - information of DSPP blocks 600 * @id enum identifying this block 601 * @base register offset of this block 602 * @features bit mask identifying sub-blocks/features 603 * supported by this block 604 * @sblk sub-blocks information 605 */ 606 struct dpu_dspp_cfg { 607 DPU_HW_BLK_INFO; 608 const struct dpu_dspp_sub_blks *sblk; 609 }; 610 611 /** 612 * struct dpu_pingpong_cfg - information of PING-PONG blocks 613 * @id enum identifying this block 614 * @base register offset of this block 615 * @features bit mask identifying sub-blocks/features 616 * @intr_done: index for PINGPONG done interrupt 617 * @intr_rdptr: index for PINGPONG readpointer done interrupt 618 * @sblk sub-blocks information 619 */ 620 struct dpu_pingpong_cfg { 621 DPU_HW_BLK_INFO; 622 u32 merge_3d; 623 s32 intr_done; 624 s32 intr_rdptr; 625 const struct dpu_pingpong_sub_blks *sblk; 626 }; 627 628 /** 629 * struct dpu_merge_3d_cfg - information of DSPP blocks 630 * @id enum identifying this block 631 * @base register offset of this block 632 * @features bit mask identifying sub-blocks/features 633 * supported by this block 634 * @sblk sub-blocks information 635 */ 636 struct dpu_merge_3d_cfg { 637 DPU_HW_BLK_INFO; 638 const struct dpu_merge_3d_sub_blks *sblk; 639 }; 640 641 /** 642 * struct dpu_dsc_cfg - information of DSC blocks 643 * @id enum identifying this block 644 * @base register offset of this block 645 * @features bit mask identifying sub-blocks/features 646 */ 647 struct dpu_dsc_cfg { 648 DPU_HW_BLK_INFO; 649 }; 650 651 /** 652 * struct dpu_intf_cfg - information of timing engine blocks 653 * @id enum identifying this block 654 * @base register offset of this block 655 * @features bit mask identifying sub-blocks/features 656 * @type: Interface type(DSI, DP, HDMI) 657 * @controller_id: Controller Instance ID in case of multiple of intf type 658 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch 659 * @intr_underrun: index for INTF underrun interrupt 660 * @intr_vsync: index for INTF VSYNC interrupt 661 */ 662 struct dpu_intf_cfg { 663 DPU_HW_BLK_INFO; 664 u32 type; /* interface type*/ 665 u32 controller_id; 666 u32 prog_fetch_lines_worst_case; 667 s32 intr_underrun; 668 s32 intr_vsync; 669 }; 670 671 /** 672 * struct dpu_wb_cfg - information of writeback blocks 673 * @DPU_HW_BLK_INFO: refer to the description above for DPU_HW_BLK_INFO 674 * @vbif_idx: vbif client index 675 * @maxlinewidth: max line width supported by writeback block 676 * @xin_id: bus client identifier 677 * @intr_wb_done: interrupt index for WB_DONE 678 * @format_list: list of formats supported by this writeback block 679 * @num_formats: number of formats supported by this writeback block 680 * @clk_ctrl: clock control identifier 681 */ 682 struct dpu_wb_cfg { 683 DPU_HW_BLK_INFO; 684 u8 vbif_idx; 685 u32 maxlinewidth; 686 u32 xin_id; 687 s32 intr_wb_done; 688 const u32 *format_list; 689 u32 num_formats; 690 enum dpu_clk_ctrl_type clk_ctrl; 691 }; 692 693 /** 694 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting 695 * @pps pixel per seconds 696 * @ot_limit OT limit to use up to specified pixel per second 697 */ 698 struct dpu_vbif_dynamic_ot_cfg { 699 u64 pps; 700 u32 ot_limit; 701 }; 702 703 /** 704 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table 705 * @count length of cfg 706 * @cfg pointer to array of configuration settings with 707 * ascending requirements 708 */ 709 struct dpu_vbif_dynamic_ot_tbl { 710 u32 count; 711 const struct dpu_vbif_dynamic_ot_cfg *cfg; 712 }; 713 714 /** 715 * struct dpu_vbif_qos_tbl - QoS priority table 716 * @npriority_lvl num of priority level 717 * @priority_lvl pointer to array of priority level in ascending order 718 */ 719 struct dpu_vbif_qos_tbl { 720 u32 npriority_lvl; 721 const u32 *priority_lvl; 722 }; 723 724 /** 725 * struct dpu_vbif_cfg - information of VBIF blocks 726 * @id enum identifying this block 727 * @base register offset of this block 728 * @features bit mask identifying sub-blocks/features 729 * @ot_rd_limit default OT read limit 730 * @ot_wr_limit default OT write limit 731 * @xin_halt_timeout maximum time (in usec) for xin to halt 732 * @qos_rp_remap_size size of VBIF_XINL_QOS_RP_REMAP register space 733 * @dynamic_ot_rd_tbl dynamic OT read configuration table 734 * @dynamic_ot_wr_tbl dynamic OT write configuration table 735 * @qos_rt_tbl real-time QoS priority table 736 * @qos_nrt_tbl non-real-time QoS priority table 737 * @memtype_count number of defined memtypes 738 * @memtype array of xin memtype definitions 739 */ 740 struct dpu_vbif_cfg { 741 DPU_HW_BLK_INFO; 742 u32 default_ot_rd_limit; 743 u32 default_ot_wr_limit; 744 u32 xin_halt_timeout; 745 u32 qos_rp_remap_size; 746 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl; 747 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl; 748 struct dpu_vbif_qos_tbl qos_rt_tbl; 749 struct dpu_vbif_qos_tbl qos_nrt_tbl; 750 u32 memtype_count; 751 u32 memtype[MAX_XIN_COUNT]; 752 }; 753 /** 754 * struct dpu_reg_dma_cfg - information of lut dma blocks 755 * @id enum identifying this block 756 * @base register offset of this block 757 * @features bit mask identifying sub-blocks/features 758 * @version version of lutdma hw block 759 * @trigger_sel_off offset to trigger select registers of lutdma 760 */ 761 struct dpu_reg_dma_cfg { 762 DPU_HW_BLK_INFO; 763 u32 version; 764 u32 trigger_sel_off; 765 u32 xin_id; 766 enum dpu_clk_ctrl_type clk_ctrl; 767 }; 768 769 /** 770 * Define CDP use cases 771 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases 772 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD 773 */ 774 enum { 775 DPU_PERF_CDP_USAGE_RT, 776 DPU_PERF_CDP_USAGE_NRT, 777 DPU_PERF_CDP_USAGE_MAX 778 }; 779 780 /** 781 * struct dpu_perf_cdp_cfg - define CDP use case configuration 782 * @rd_enable: true if read pipe CDP is enabled 783 * @wr_enable: true if write pipe CDP is enabled 784 */ 785 struct dpu_perf_cdp_cfg { 786 bool rd_enable; 787 bool wr_enable; 788 }; 789 790 /** 791 * struct dpu_perf_cfg - performance control settings 792 * @max_bw_low low threshold of maximum bandwidth (kbps) 793 * @max_bw_high high threshold of maximum bandwidth (kbps) 794 * @min_core_ib minimum bandwidth for core (kbps) 795 * @min_core_ib minimum mnoc ib vote in kbps 796 * @min_llcc_ib minimum llcc ib vote in kbps 797 * @min_dram_ib minimum dram ib vote in kbps 798 * @undersized_prefill_lines undersized prefill in lines 799 * @xtra_prefill_lines extra prefill latency in lines 800 * @dest_scale_prefill_lines destination scaler latency in lines 801 * @macrotile_perfill_lines macrotile latency in lines 802 * @yuv_nv12_prefill_lines yuv_nv12 latency in lines 803 * @linear_prefill_lines linear latency in lines 804 * @downscaling_prefill_lines downscaling latency in lines 805 * @amortizable_theshold minimum y position for traffic shaping prefill 806 * @min_prefill_lines minimum pipeline latency in lines 807 * @clk_inefficiency_factor DPU src clock inefficiency factor 808 * @bw_inefficiency_factor DPU axi bus bw inefficiency factor 809 * @safe_lut_tbl: LUT tables for safe signals 810 * @danger_lut_tbl: LUT tables for danger signals 811 * @qos_lut_tbl: LUT tables for QoS signals 812 * @cdp_cfg cdp use case configurations 813 */ 814 struct dpu_perf_cfg { 815 u32 max_bw_low; 816 u32 max_bw_high; 817 u32 min_core_ib; 818 u32 min_llcc_ib; 819 u32 min_dram_ib; 820 u32 undersized_prefill_lines; 821 u32 xtra_prefill_lines; 822 u32 dest_scale_prefill_lines; 823 u32 macrotile_prefill_lines; 824 u32 yuv_nv12_prefill_lines; 825 u32 linear_prefill_lines; 826 u32 downscaling_prefill_lines; 827 u32 amortizable_threshold; 828 u32 min_prefill_lines; 829 u32 clk_inefficiency_factor; 830 u32 bw_inefficiency_factor; 831 u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 832 u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 833 struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 834 struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX]; 835 }; 836 837 /** 838 * struct dpu_mdss_cfg - information of MDSS HW 839 * This is the main catalog data structure representing 840 * this HW version. Contains number of instances, 841 * register offsets, capabilities of the all MDSS HW sub-blocks. 842 * 843 * @dma_formats Supported formats for dma pipe 844 * @cursor_formats Supported formats for cursor pipe 845 * @vig_formats Supported formats for vig pipe 846 * @mdss_irqs: Bitmap with the irqs supported by the target 847 */ 848 struct dpu_mdss_cfg { 849 const struct dpu_caps *caps; 850 851 u32 mdp_count; 852 const struct dpu_mdp_cfg *mdp; 853 854 u32 ctl_count; 855 const struct dpu_ctl_cfg *ctl; 856 857 u32 sspp_count; 858 const struct dpu_sspp_cfg *sspp; 859 860 u32 mixer_count; 861 const struct dpu_lm_cfg *mixer; 862 863 u32 pingpong_count; 864 const struct dpu_pingpong_cfg *pingpong; 865 866 u32 merge_3d_count; 867 const struct dpu_merge_3d_cfg *merge_3d; 868 869 u32 dsc_count; 870 struct dpu_dsc_cfg *dsc; 871 872 u32 intf_count; 873 const struct dpu_intf_cfg *intf; 874 875 u32 vbif_count; 876 const struct dpu_vbif_cfg *vbif; 877 878 u32 wb_count; 879 const struct dpu_wb_cfg *wb; 880 881 u32 reg_dma_count; 882 const struct dpu_reg_dma_cfg *dma_cfg; 883 884 u32 ad_count; 885 886 u32 dspp_count; 887 const struct dpu_dspp_cfg *dspp; 888 889 /* Add additional block data structures here */ 890 891 const struct dpu_perf_cfg *perf; 892 const struct dpu_format_extended *dma_formats; 893 const struct dpu_format_extended *cursor_formats; 894 const struct dpu_format_extended *vig_formats; 895 896 unsigned long mdss_irqs; 897 }; 898 899 struct dpu_mdss_hw_cfg_handler { 900 u32 hw_rev; 901 const struct dpu_mdss_cfg *dpu_cfg; 902 }; 903 904 /** 905 * dpu_hw_catalog_init - dpu hardware catalog init API retrieves 906 * hardcoded target specific catalog information in config structure 907 * @hw_rev: caller needs provide the hardware revision. 908 * 909 * Return: dpu config structure 910 */ 911 const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev); 912 913 #endif /* _DPU_HW_CATALOG_H */ 914