1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * Register definitions for PCIe integration control module. 9 */ 10 11 #ifndef PCIE_INTEG_CTRL_REG 12 #define PCIE_INTEG_CTRL_REG 13 14 #include <mod_pcid.h> 15 16 #include <fwk_macros.h> 17 18 #include <stdint.h> 19 20 struct pcie_ctrl_reg_set { 21 FWK_RW uint32_t ECAM1_START_ADDR; 22 FWK_RW uint32_t ECAM1_END_ADDR; 23 FWK_RW uint32_t MMIOL_START_ADDR; 24 FWK_RW uint32_t MMIOL_END_ADDR; 25 FWK_RW uint32_t MMIOH_START_ADDR; 26 FWK_RW uint32_t MMIOH_END_ADDR; 27 FWK_RW uint32_t MMIOH2L_TR_START_ADDR; 28 FWK_RW uint32_t MMIOH2L_TR_END_ADDR; 29 FWK_RW uint32_t CFG_START_ADDR; 30 FWK_RW uint32_t CFG_END_ADDR; 31 FWK_RW uint32_t ECAM2_START_ADDR; 32 FWK_RW uint32_t ECAM2_END_ADDR; 33 FWK_RW uint32_t ECAM2_ADDR_CTRL; 34 }; 35 36 struct pcie_ctrl_reg { 37 struct pcie_ctrl_reg_set pcie_ctrl_x4_0; 38 uint8_t RESERVED0[0x100 - 0x34]; 39 struct pcie_ctrl_reg_set pcie_ctrl_x4_1; 40 uint8_t RESERVED1[0x200 - 0x134]; 41 struct pcie_ctrl_reg_set pcie_ctrl_x8; 42 uint8_t RESERVED2[0x300 - 0x234]; 43 struct pcie_ctrl_reg_set pcie_ctrl_x16; 44 uint8_t RESERVED3[0x400 - 0x334]; 45 uint32_t NCI_PMU_CONS_INT_STATUS; 46 uint8_t RESERVED4[0xFD0 - 0x404]; 47 struct mod_pcid_registers pcid; 48 }; 49 50 #define PCIE_INTEG_CTRL_REG_ADDR_POS 1 51 #define PCIE_INTEG_CTRL_REG_SEC_ACC_CTRL_DIS_POS 29 52 #define PCIE_INTEG_CTRL_REG_EN 1 53 54 #define PCIE_INTEG_CTRL_REG_START_ADDR(addr) \ 55 (((addr) >> 20) << PCIE_INTEG_CTRL_REG_ADDR_POS) 56 57 #define PCIE_INTEG_CTRL_REG_START_ADDR_EN(addr, non_secure_access) \ 58 (PCIE_INTEG_CTRL_REG_START_ADDR(addr) | PCIE_INTEG_CTRL_REG_EN | \ 59 ((non_secure_access) << PCIE_INTEG_CTRL_REG_SEC_ACC_CTRL_DIS_POS)) 60 61 #define PCIE_INTEG_CTRL_REG_END_ADDR(addr) ((addr) >> 20) 62 63 #endif /* PCIE_INTEG_CTRL_REG */ 64