1 #ifndef __ASM_MSR_INDEX_H 2 #define __ASM_MSR_INDEX_H 3 4 /* CPU model specific register (MSR) numbers */ 5 6 /* x86-64 specific MSRs */ 7 #define MSR_EFER 0xc0000080 /* extended feature register */ 8 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 9 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 10 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 11 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 12 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 13 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 14 #define MSR_SHADOW_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 15 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 16 17 /* EFER bits: */ 18 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 19 #define _EFER_LME 8 /* Long mode enable */ 20 #define _EFER_LMA 10 /* Long mode active (read-only) */ 21 #define _EFER_NX 11 /* No execute enable */ 22 #define _EFER_SVME 12 /* AMD: SVM enable */ 23 #define _EFER_LMSLE 13 /* AMD: Long-mode segment limit enable */ 24 #define _EFER_FFXSE 14 /* AMD: Fast FXSAVE/FXRSTOR enable */ 25 26 #define EFER_SCE (1<<_EFER_SCE) 27 #define EFER_LME (1<<_EFER_LME) 28 #define EFER_LMA (1<<_EFER_LMA) 29 #define EFER_NX (1<<_EFER_NX) 30 #define EFER_SVME (1<<_EFER_SVME) 31 #define EFER_LMSLE (1<<_EFER_LMSLE) 32 #define EFER_FFXSE (1<<_EFER_FFXSE) 33 34 /* Intel MSRs. Some also available on other CPUs */ 35 #define MSR_IA32_PERFCTR0 0x000000c1 36 #define MSR_IA32_A_PERFCTR0 0x000004c1 37 #define MSR_FSB_FREQ 0x000000cd 38 39 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 40 #define NHM_C3_AUTO_DEMOTE (1UL << 25) 41 #define NHM_C1_AUTO_DEMOTE (1UL << 26) 42 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 43 44 #define MSR_MTRRcap 0x000000fe 45 #define MSR_IA32_BBL_CR_CTL 0x00000119 46 47 #define MSR_IA32_SYSENTER_CS 0x00000174 48 #define MSR_IA32_SYSENTER_ESP 0x00000175 49 #define MSR_IA32_SYSENTER_EIP 0x00000176 50 51 #define MSR_IA32_MCG_CAP 0x00000179 52 #define MSR_IA32_MCG_STATUS 0x0000017a 53 #define MSR_IA32_MCG_CTL 0x0000017b 54 #define MSR_IA32_MCG_EXT_CTL 0x000004d0 55 56 #define MSR_IA32_PEBS_ENABLE 0x000003f1 57 #define MSR_IA32_DS_AREA 0x00000600 58 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 59 /* Lower 6 bits define the format of the address in the LBR stack */ 60 #define MSR_IA32_PERF_CAP_LBR_FORMAT 0x3f 61 62 #define MSR_IA32_BNDCFGS 0x00000d90 63 #define IA32_BNDCFGS_ENABLE 0x00000001 64 #define IA32_BNDCFGS_PRESERVE 0x00000002 65 #define IA32_BNDCFGS_RESERVED 0x00000ffc 66 67 #define MSR_IA32_XSS 0x00000da0 68 69 #define MSR_MTRRfix64K_00000 0x00000250 70 #define MSR_MTRRfix16K_80000 0x00000258 71 #define MSR_MTRRfix16K_A0000 0x00000259 72 #define MSR_MTRRfix4K_C0000 0x00000268 73 #define MSR_MTRRfix4K_C8000 0x00000269 74 #define MSR_MTRRfix4K_D0000 0x0000026a 75 #define MSR_MTRRfix4K_D8000 0x0000026b 76 #define MSR_MTRRfix4K_E0000 0x0000026c 77 #define MSR_MTRRfix4K_E8000 0x0000026d 78 #define MSR_MTRRfix4K_F0000 0x0000026e 79 #define MSR_MTRRfix4K_F8000 0x0000026f 80 #define MSR_MTRRdefType 0x000002ff 81 82 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 83 #define IA32_DEBUGCTLMSR_LBR (1<<0) /* Last Branch Record */ 84 #define IA32_DEBUGCTLMSR_BTF (1<<1) /* Single Step on Branches */ 85 #define IA32_DEBUGCTLMSR_TR (1<<6) /* Trace Message Enable */ 86 #define IA32_DEBUGCTLMSR_BTS (1<<7) /* Branch Trace Store */ 87 #define IA32_DEBUGCTLMSR_BTINT (1<<8) /* Branch Trace Interrupt */ 88 #define IA32_DEBUGCTLMSR_BTS_OFF_OS (1<<9) /* BTS off if CPL 0 */ 89 #define IA32_DEBUGCTLMSR_BTS_OFF_USR (1<<10) /* BTS off if CPL > 0 */ 90 #define IA32_DEBUGCTLMSR_RTM (1<<15) /* RTM debugging enable */ 91 92 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 93 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 94 #define MSR_IA32_LASTINTFROMIP 0x000001dd 95 #define MSR_IA32_LASTINTTOIP 0x000001de 96 97 #define MSR_IA32_POWER_CTL 0x000001fc 98 99 #define MSR_IA32_MTRR_PHYSBASE(n) (0x00000200 + 2 * (n)) 100 #define MSR_IA32_MTRR_PHYSMASK(n) (0x00000201 + 2 * (n)) 101 102 #define MSR_IA32_CR_PAT 0x00000277 103 #define MSR_IA32_CR_PAT_RESET 0x0007040600070406ULL 104 105 #define MSR_IA32_MC0_CTL 0x00000400 106 #define MSR_IA32_MC0_STATUS 0x00000401 107 #define MSR_IA32_MC0_ADDR 0x00000402 108 #define MSR_IA32_MC0_MISC 0x00000403 109 #define MSR_IA32_MC0_CTL2 0x00000280 110 #define CMCI_EN (1UL<<30) 111 #define CMCI_THRESHOLD_MASK 0x7FFF 112 113 #define MSR_AMD64_MC0_MASK 0xc0010044 114 115 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 116 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 117 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 118 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 119 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 120 121 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 122 123 /* MSRs & bits used for VMX enabling */ 124 #define MSR_IA32_VMX_BASIC 0x480 125 #define MSR_IA32_VMX_PINBASED_CTLS 0x481 126 #define MSR_IA32_VMX_PROCBASED_CTLS 0x482 127 #define MSR_IA32_VMX_EXIT_CTLS 0x483 128 #define MSR_IA32_VMX_ENTRY_CTLS 0x484 129 #define MSR_IA32_VMX_MISC 0x485 130 #define MSR_IA32_VMX_CR0_FIXED0 0x486 131 #define MSR_IA32_VMX_CR0_FIXED1 0x487 132 #define MSR_IA32_VMX_CR4_FIXED0 0x488 133 #define MSR_IA32_VMX_CR4_FIXED1 0x489 134 #define MSR_IA32_VMX_VMCS_ENUM 0x48a 135 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x48b 136 #define MSR_IA32_VMX_EPT_VPID_CAP 0x48c 137 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48d 138 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48e 139 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48f 140 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490 141 #define MSR_IA32_VMX_VMFUNC 0x491 142 143 /* K7/K8 MSRs. Not complete. See the architecture manual for a more 144 complete list. */ 145 #define MSR_K7_EVNTSEL0 0xc0010000 146 #define MSR_K7_PERFCTR0 0xc0010004 147 #define MSR_K7_EVNTSEL1 0xc0010001 148 #define MSR_K7_PERFCTR1 0xc0010005 149 #define MSR_K7_EVNTSEL2 0xc0010002 150 #define MSR_K7_PERFCTR2 0xc0010006 151 #define MSR_K7_EVNTSEL3 0xc0010003 152 #define MSR_K7_PERFCTR3 0xc0010007 153 #define MSR_K8_TOP_MEM1 0xc001001a 154 #define MSR_K7_CLK_CTL 0xc001001b 155 #define MSR_K8_TOP_MEM2 0xc001001d 156 #define MSR_K8_SYSCFG 0xc0010010 157 158 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 159 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 160 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 161 162 #define MSR_K7_HWCR 0xc0010015 163 #define MSR_K8_HWCR 0xc0010015 164 #define MSR_K7_FID_VID_CTL 0xc0010041 165 #define MSR_K7_FID_VID_STATUS 0xc0010042 166 #define MSR_K8_PSTATE_LIMIT 0xc0010061 167 #define MSR_K8_PSTATE_CTRL 0xc0010062 168 #define MSR_K8_PSTATE_STATUS 0xc0010063 169 #define MSR_K8_PSTATE0 0xc0010064 170 #define MSR_K8_PSTATE1 0xc0010065 171 #define MSR_K8_PSTATE2 0xc0010066 172 #define MSR_K8_PSTATE3 0xc0010067 173 #define MSR_K8_PSTATE4 0xc0010068 174 #define MSR_K8_PSTATE5 0xc0010069 175 #define MSR_K8_PSTATE6 0xc001006A 176 #define MSR_K8_PSTATE7 0xc001006B 177 #define MSR_K8_ENABLE_C1E 0xc0010055 178 #define MSR_K8_VM_CR 0xc0010114 179 #define MSR_K8_VM_HSAVE_PA 0xc0010117 180 181 #define MSR_AMD_FAM15H_EVNTSEL0 0xc0010200 182 #define MSR_AMD_FAM15H_PERFCTR0 0xc0010201 183 #define MSR_AMD_FAM15H_EVNTSEL1 0xc0010202 184 #define MSR_AMD_FAM15H_PERFCTR1 0xc0010203 185 #define MSR_AMD_FAM15H_EVNTSEL2 0xc0010204 186 #define MSR_AMD_FAM15H_PERFCTR2 0xc0010205 187 #define MSR_AMD_FAM15H_EVNTSEL3 0xc0010206 188 #define MSR_AMD_FAM15H_PERFCTR3 0xc0010207 189 #define MSR_AMD_FAM15H_EVNTSEL4 0xc0010208 190 #define MSR_AMD_FAM15H_PERFCTR4 0xc0010209 191 #define MSR_AMD_FAM15H_EVNTSEL5 0xc001020a 192 #define MSR_AMD_FAM15H_PERFCTR5 0xc001020b 193 194 #define MSR_AMD_L7S0_FEATURE_MASK 0xc0011002 195 #define MSR_AMD_THRM_FEATURE_MASK 0xc0011003 196 #define MSR_K8_FEATURE_MASK 0xc0011004 197 #define MSR_K8_EXT_FEATURE_MASK 0xc0011005 198 199 /* MSR_K8_VM_CR bits: */ 200 #define _K8_VMCR_SVME_DISABLE 4 201 #define K8_VMCR_SVME_DISABLE (1 << _K8_VMCR_SVME_DISABLE) 202 203 /* AMD64 MSRs */ 204 #define MSR_AMD64_NB_CFG 0xc001001f 205 #define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46 206 #define MSR_AMD64_LS_CFG 0xc0011020 207 #define MSR_AMD64_IC_CFG 0xc0011021 208 #define MSR_AMD64_DC_CFG 0xc0011022 209 #define MSR_AMD64_DE_CFG 0xc0011029 210 211 #define MSR_AMD64_DR0_ADDRESS_MASK 0xc0011027 212 #define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019 213 #define MSR_AMD64_DR2_ADDRESS_MASK 0xc001101a 214 #define MSR_AMD64_DR3_ADDRESS_MASK 0xc001101b 215 216 /* AMD Family10h machine check MSRs */ 217 #define MSR_F10_MC4_MISC1 0xc0000408 218 #define MSR_F10_MC4_MISC2 0xc0000409 219 #define MSR_F10_MC4_MISC3 0xc000040A 220 221 /* AMD Family10h Bus Unit MSRs */ 222 #define MSR_F10_BU_CFG 0xc0011023 223 #define MSR_F10_BU_CFG2 0xc001102a 224 225 /* Other AMD Fam10h MSRs */ 226 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 227 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 228 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 229 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 230 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 231 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 232 233 /* AMD Microcode MSRs */ 234 #define MSR_AMD_PATCHLEVEL 0x0000008b 235 #define MSR_AMD_PATCHLOADER 0xc0010020 236 237 /* AMD TSC RATE MSR */ 238 #define MSR_AMD64_TSC_RATIO 0xc0000104 239 240 /* AMD Lightweight Profiling MSRs */ 241 #define MSR_AMD64_LWP_CFG 0xc0000105 242 #define MSR_AMD64_LWP_CBADDR 0xc0000106 243 244 /* AMD OS Visible Workaround MSRs */ 245 #define MSR_AMD_OSVW_ID_LENGTH 0xc0010140 246 #define MSR_AMD_OSVW_STATUS 0xc0010141 247 248 /* K6 MSRs */ 249 #define MSR_K6_EFER 0xc0000080 250 #define MSR_K6_STAR 0xc0000081 251 #define MSR_K6_WHCR 0xc0000082 252 #define MSR_K6_UWCCR 0xc0000085 253 #define MSR_K6_EPMR 0xc0000086 254 #define MSR_K6_PSOR 0xc0000087 255 #define MSR_K6_PFIR 0xc0000088 256 257 /* Centaur-Hauls/IDT defined MSRs. */ 258 #define MSR_IDT_FCR1 0x00000107 259 #define MSR_IDT_FCR2 0x00000108 260 #define MSR_IDT_FCR3 0x00000109 261 #define MSR_IDT_FCR4 0x0000010a 262 263 #define MSR_IDT_MCR0 0x00000110 264 #define MSR_IDT_MCR1 0x00000111 265 #define MSR_IDT_MCR2 0x00000112 266 #define MSR_IDT_MCR3 0x00000113 267 #define MSR_IDT_MCR4 0x00000114 268 #define MSR_IDT_MCR5 0x00000115 269 #define MSR_IDT_MCR6 0x00000116 270 #define MSR_IDT_MCR7 0x00000117 271 #define MSR_IDT_MCR_CTRL 0x00000120 272 273 /* VIA Cyrix defined MSRs*/ 274 #define MSR_VIA_FCR 0x00001107 275 #define MSR_VIA_LONGHAUL 0x0000110a 276 #define MSR_VIA_RNG 0x0000110b 277 #define MSR_VIA_BCR2 0x00001147 278 279 /* Transmeta defined MSRs */ 280 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 281 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 282 #define MSR_TMTA_LRTI_READOUT 0x80868018 283 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 284 285 /* Intel defined MSRs. */ 286 #define MSR_IA32_P5_MC_ADDR 0x00000000 287 #define MSR_IA32_P5_MC_TYPE 0x00000001 288 #define MSR_IA32_TSC 0x00000010 289 #define MSR_IA32_PLATFORM_ID 0x00000017 290 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 291 #define MSR_IA32_EBC_FREQUENCY_ID 0x0000002c 292 293 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 294 #define IA32_FEATURE_CONTROL_LOCK 0x0001 295 #define IA32_FEATURE_CONTROL_ENABLE_VMXON_INSIDE_SMX 0x0002 296 #define IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX 0x0004 297 #define IA32_FEATURE_CONTROL_SENTER_PARAM_CTL 0x7f00 298 #define IA32_FEATURE_CONTROL_ENABLE_SENTER 0x8000 299 #define IA32_FEATURE_CONTROL_SGX_ENABLE 0x40000 300 #define IA32_FEATURE_CONTROL_LMCE_ON 0x100000 301 302 #define MSR_IA32_TSC_ADJUST 0x0000003b 303 304 #define MSR_IA32_APICBASE 0x0000001b 305 #define MSR_IA32_APICBASE_BSP (1<<8) 306 #define MSR_IA32_APICBASE_EXTD (1<<10) 307 #define MSR_IA32_APICBASE_ENABLE (1<<11) 308 #define MSR_IA32_APICBASE_BASE 0x000ffffffffff000ul 309 #define MSR_IA32_APICBASE_MSR 0x800 310 #define MSR_IA32_APICTPR_MSR 0x808 311 #define MSR_IA32_APICPPR_MSR 0x80a 312 #define MSR_IA32_APICEOI_MSR 0x80b 313 #define MSR_IA32_APICTMICT_MSR 0x838 314 #define MSR_IA32_APICTMCCT_MSR 0x839 315 #define MSR_IA32_APICSELF_MSR 0x83f 316 317 #define MSR_IA32_UCODE_WRITE 0x00000079 318 #define MSR_IA32_UCODE_REV 0x0000008b 319 320 #define MSR_IA32_PERF_STATUS 0x00000198 321 #define MSR_IA32_PERF_CTL 0x00000199 322 323 #define MSR_IA32_MPERF 0x000000e7 324 #define MSR_IA32_APERF 0x000000e8 325 326 #define MSR_IA32_THERM_CONTROL 0x0000019a 327 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 328 #define MSR_IA32_THERM_STATUS 0x0000019c 329 #define MSR_IA32_MISC_ENABLE 0x000001a0 330 #define MSR_IA32_MISC_ENABLE_PERF_AVAIL (1<<7) 331 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11) 332 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12) 333 #define MSR_IA32_MISC_ENABLE_MONITOR_ENABLE (1<<18) 334 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1<<22) 335 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1<<23) 336 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 337 338 #define MSR_IA32_TSC_DEADLINE 0x000006E0 339 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 340 341 /* Platform Shared Resource MSRs */ 342 #define MSR_IA32_CMT_EVTSEL 0x00000c8d 343 #define MSR_IA32_CMT_EVTSEL_UE_MASK 0x0000ffff 344 #define MSR_IA32_CMT_CTR 0x00000c8e 345 #define MSR_IA32_PSR_ASSOC 0x00000c8f 346 #define MSR_IA32_PSR_L3_QOS_CFG 0x00000c81 347 #define MSR_IA32_PSR_L3_MASK(n) (0x00000c90 + (n)) 348 #define MSR_IA32_PSR_L3_MASK_CODE(n) (0x00000c90 + (n) * 2 + 1) 349 #define MSR_IA32_PSR_L3_MASK_DATA(n) (0x00000c90 + (n) * 2) 350 #define MSR_IA32_PSR_L2_MASK(n) (0x00000d10 + (n)) 351 352 /* Intel Model 6 */ 353 #define MSR_P6_PERFCTR(n) (0x000000c1 + (n)) 354 #define MSR_P6_EVNTSEL(n) (0x00000186 + (n)) 355 356 /* P4/Xeon+ specific */ 357 #define MSR_IA32_MCG_EAX 0x00000180 358 #define MSR_IA32_MCG_EBX 0x00000181 359 #define MSR_IA32_MCG_ECX 0x00000182 360 #define MSR_IA32_MCG_EDX 0x00000183 361 #define MSR_IA32_MCG_ESI 0x00000184 362 #define MSR_IA32_MCG_EDI 0x00000185 363 #define MSR_IA32_MCG_EBP 0x00000186 364 #define MSR_IA32_MCG_ESP 0x00000187 365 #define MSR_IA32_MCG_EFLAGS 0x00000188 366 #define MSR_IA32_MCG_EIP 0x00000189 367 #define MSR_IA32_MCG_MISC 0x0000018a 368 #define MSR_IA32_MCG_R8 0x00000190 369 #define MSR_IA32_MCG_R9 0x00000191 370 #define MSR_IA32_MCG_R10 0x00000192 371 #define MSR_IA32_MCG_R11 0x00000193 372 #define MSR_IA32_MCG_R12 0x00000194 373 #define MSR_IA32_MCG_R13 0x00000195 374 #define MSR_IA32_MCG_R14 0x00000196 375 #define MSR_IA32_MCG_R15 0x00000197 376 377 /* Pentium IV performance counter MSRs */ 378 #define MSR_P4_BPU_PERFCTR0 0x00000300 379 #define MSR_P4_BPU_PERFCTR1 0x00000301 380 #define MSR_P4_BPU_PERFCTR2 0x00000302 381 #define MSR_P4_BPU_PERFCTR3 0x00000303 382 #define MSR_P4_MS_PERFCTR0 0x00000304 383 #define MSR_P4_MS_PERFCTR1 0x00000305 384 #define MSR_P4_MS_PERFCTR2 0x00000306 385 #define MSR_P4_MS_PERFCTR3 0x00000307 386 #define MSR_P4_FLAME_PERFCTR0 0x00000308 387 #define MSR_P4_FLAME_PERFCTR1 0x00000309 388 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 389 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 390 #define MSR_P4_IQ_PERFCTR0 0x0000030c 391 #define MSR_P4_IQ_PERFCTR1 0x0000030d 392 #define MSR_P4_IQ_PERFCTR2 0x0000030e 393 #define MSR_P4_IQ_PERFCTR3 0x0000030f 394 #define MSR_P4_IQ_PERFCTR4 0x00000310 395 #define MSR_P4_IQ_PERFCTR5 0x00000311 396 #define MSR_P4_BPU_CCCR0 0x00000360 397 #define MSR_P4_BPU_CCCR1 0x00000361 398 #define MSR_P4_BPU_CCCR2 0x00000362 399 #define MSR_P4_BPU_CCCR3 0x00000363 400 #define MSR_P4_MS_CCCR0 0x00000364 401 #define MSR_P4_MS_CCCR1 0x00000365 402 #define MSR_P4_MS_CCCR2 0x00000366 403 #define MSR_P4_MS_CCCR3 0x00000367 404 #define MSR_P4_FLAME_CCCR0 0x00000368 405 #define MSR_P4_FLAME_CCCR1 0x00000369 406 #define MSR_P4_FLAME_CCCR2 0x0000036a 407 #define MSR_P4_FLAME_CCCR3 0x0000036b 408 #define MSR_P4_IQ_CCCR0 0x0000036c 409 #define MSR_P4_IQ_CCCR1 0x0000036d 410 #define MSR_P4_IQ_CCCR2 0x0000036e 411 #define MSR_P4_IQ_CCCR3 0x0000036f 412 #define MSR_P4_IQ_CCCR4 0x00000370 413 #define MSR_P4_IQ_CCCR5 0x00000371 414 #define MSR_P4_ALF_ESCR0 0x000003ca 415 #define MSR_P4_ALF_ESCR1 0x000003cb 416 #define MSR_P4_BPU_ESCR0 0x000003b2 417 #define MSR_P4_BPU_ESCR1 0x000003b3 418 #define MSR_P4_BSU_ESCR0 0x000003a0 419 #define MSR_P4_BSU_ESCR1 0x000003a1 420 #define MSR_P4_CRU_ESCR0 0x000003b8 421 #define MSR_P4_CRU_ESCR1 0x000003b9 422 #define MSR_P4_CRU_ESCR2 0x000003cc 423 #define MSR_P4_CRU_ESCR3 0x000003cd 424 #define MSR_P4_CRU_ESCR4 0x000003e0 425 #define MSR_P4_CRU_ESCR5 0x000003e1 426 #define MSR_P4_DAC_ESCR0 0x000003a8 427 #define MSR_P4_DAC_ESCR1 0x000003a9 428 #define MSR_P4_FIRM_ESCR0 0x000003a4 429 #define MSR_P4_FIRM_ESCR1 0x000003a5 430 #define MSR_P4_FLAME_ESCR0 0x000003a6 431 #define MSR_P4_FLAME_ESCR1 0x000003a7 432 #define MSR_P4_FSB_ESCR0 0x000003a2 433 #define MSR_P4_FSB_ESCR1 0x000003a3 434 #define MSR_P4_IQ_ESCR0 0x000003ba 435 #define MSR_P4_IQ_ESCR1 0x000003bb 436 #define MSR_P4_IS_ESCR0 0x000003b4 437 #define MSR_P4_IS_ESCR1 0x000003b5 438 #define MSR_P4_ITLB_ESCR0 0x000003b6 439 #define MSR_P4_ITLB_ESCR1 0x000003b7 440 #define MSR_P4_IX_ESCR0 0x000003c8 441 #define MSR_P4_IX_ESCR1 0x000003c9 442 #define MSR_P4_MOB_ESCR0 0x000003aa 443 #define MSR_P4_MOB_ESCR1 0x000003ab 444 #define MSR_P4_MS_ESCR0 0x000003c0 445 #define MSR_P4_MS_ESCR1 0x000003c1 446 #define MSR_P4_PMH_ESCR0 0x000003ac 447 #define MSR_P4_PMH_ESCR1 0x000003ad 448 #define MSR_P4_RAT_ESCR0 0x000003bc 449 #define MSR_P4_RAT_ESCR1 0x000003bd 450 #define MSR_P4_SAAT_ESCR0 0x000003ae 451 #define MSR_P4_SAAT_ESCR1 0x000003af 452 #define MSR_P4_SSU_ESCR0 0x000003be 453 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 454 455 #define MSR_P4_TBPU_ESCR0 0x000003c2 456 #define MSR_P4_TBPU_ESCR1 0x000003c3 457 #define MSR_P4_TC_ESCR0 0x000003c4 458 #define MSR_P4_TC_ESCR1 0x000003c5 459 #define MSR_P4_U2L_ESCR0 0x000003b0 460 #define MSR_P4_U2L_ESCR1 0x000003b1 461 462 /* Netburst (P4) last-branch recording */ 463 #define MSR_P4_LER_FROM_LIP 0x000001d7 464 #define MSR_P4_LER_TO_LIP 0x000001d8 465 #define MSR_P4_LASTBRANCH_TOS 0x000001da 466 #define MSR_P4_LASTBRANCH_0 0x000001db 467 #define NUM_MSR_P4_LASTBRANCH 4 468 #define MSR_P4_LASTBRANCH_0_FROM_LIP 0x00000680 469 #define MSR_P4_LASTBRANCH_0_TO_LIP 0x000006c0 470 #define NUM_MSR_P4_LASTBRANCH_FROM_TO 16 471 472 /* Core 2 and Atom last-branch recording */ 473 #define MSR_C2_LASTBRANCH_TOS 0x000001c9 474 #define MSR_C2_LASTBRANCH_0_FROM_IP 0x00000040 475 #define MSR_C2_LASTBRANCH_0_TO_IP 0x00000060 476 #define NUM_MSR_C2_LASTBRANCH_FROM_TO 4 477 #define NUM_MSR_ATOM_LASTBRANCH_FROM_TO 8 478 479 /* Skylake (and newer) last-branch recording */ 480 #define MSR_SKL_LASTBRANCH_TOS 0x000001c9 481 #define MSR_SKL_LASTBRANCH_0_FROM_IP 0x00000680 482 #define MSR_SKL_LASTBRANCH_0_TO_IP 0x000006c0 483 #define MSR_SKL_LASTBRANCH_0_INFO 0x00000dc0 484 #define NUM_MSR_SKL_LASTBRANCH 32 485 486 /* Goldmont last-branch recording */ 487 #define MSR_GM_LASTBRANCH_TOS 0x000001c9 488 #define MSR_GM_LASTBRANCH_0_FROM_IP 0x00000680 489 #define MSR_GM_LASTBRANCH_0_TO_IP 0x000006c0 490 #define NUM_MSR_GM_LASTBRANCH_FROM_TO 32 491 492 /* Intel Core-based CPU performance counters */ 493 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 494 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 495 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 496 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 497 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 498 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 499 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 500 501 /* Intel cpuid spoofing MSRs */ 502 #define MSR_INTEL_MASK_V1_CPUID1 0x00000478 503 504 #define MSR_INTEL_MASK_V2_CPUID1 0x00000130 505 #define MSR_INTEL_MASK_V2_CPUID80000001 0x00000131 506 507 #define MSR_INTEL_MASK_V3_CPUID1 0x00000132 508 #define MSR_INTEL_MASK_V3_CPUID80000001 0x00000133 509 #define MSR_INTEL_MASK_V3_CPUIDD_01 0x00000134 510 511 /* Intel cpuid faulting MSRs */ 512 #define MSR_INTEL_PLATFORM_INFO 0x000000ce 513 #define _MSR_PLATFORM_INFO_CPUID_FAULTING 31 514 #define MSR_PLATFORM_INFO_CPUID_FAULTING (1ULL << _MSR_PLATFORM_INFO_CPUID_FAULTING) 515 516 #define MSR_INTEL_MISC_FEATURES_ENABLES 0x00000140 517 #define _MSR_MISC_FEATURES_CPUID_FAULTING 0 518 #define MSR_MISC_FEATURES_CPUID_FAULTING (1ULL << _MSR_MISC_FEATURES_CPUID_FAULTING) 519 520 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 521 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 522 523 /* Interrupt Response Limit */ 524 #define MSR_PKGC3_IRTL 0x0000060a 525 #define MSR_PKGC6_IRTL 0x0000060b 526 #define MSR_PKGC7_IRTL 0x0000060c 527 #define MSR_PKGC8_IRTL 0x00000633 528 #define MSR_PKGC9_IRTL 0x00000634 529 #define MSR_PKGC10_IRTL 0x00000635 530 531 #endif /* __ASM_MSR_INDEX_H */ 532