1 /* SPDX-License-Identifier: ISC */
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6 #ifndef __MT7996_H
7 #define __MT7996_H
8
9 #include <linux/interrupt.h>
10 #include <linux/ktime.h>
11 #include "../mt76_connac.h"
12 #include "regs.h"
13
14 #define MT7996_MAX_INTERFACES 19 /* per-band */
15 #define MT7996_MAX_WMM_SETS 4
16 #define MT7996_WTBL_RESERVED (mt7996_wtbl_size(dev) - 1)
17 #define MT7996_WTBL_STA (MT7996_WTBL_RESERVED - \
18 mt7996_max_interface_num(dev))
19
20 #define MT7996_WATCHDOG_TIME (HZ / 10)
21 #define MT7996_RESET_TIMEOUT (30 * HZ)
22
23 #define MT7996_TX_RING_SIZE 2048
24 #define MT7996_TX_MCU_RING_SIZE 256
25 #define MT7996_TX_FWDL_RING_SIZE 128
26
27 #define MT7996_RX_RING_SIZE 1536
28 #define MT7996_RX_MCU_RING_SIZE 512
29
30 #define MT7996_FIRMWARE_WA "mediatek/mt7996/mt7996_wa.bin"
31 #define MT7996_FIRMWARE_WM "mediatek/mt7996/mt7996_wm.bin"
32 #define MT7996_ROM_PATCH "mediatek/mt7996/mt7996_rom_patch.bin"
33
34 #define MT7996_EEPROM_DEFAULT "mediatek/mt7996/mt7996_eeprom.bin"
35 #define MT7996_EEPROM_SIZE 7680
36 #define MT7996_EEPROM_BLOCK_SIZE 16
37 #define MT7996_TOKEN_SIZE 8192
38
39 #define MT7996_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */
40 #define MT7996_CFEND_RATE_11B 0x03 /* 11B LP, 11M */
41
42 #define MT7996_MAX_TWT_AGRT 16
43 #define MT7996_MAX_STA_TWT_AGRT 8
44 #define MT7996_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 3)
45
46 struct mt7996_vif;
47 struct mt7996_sta;
48 struct mt7996_dfs_pulse;
49 struct mt7996_dfs_pattern;
50
51 enum mt7996_txq_id {
52 MT7996_TXQ_FWDL = 16,
53 MT7996_TXQ_MCU_WM,
54 MT7996_TXQ_BAND0,
55 MT7996_TXQ_BAND1,
56 MT7996_TXQ_MCU_WA,
57 MT7996_TXQ_BAND2,
58 };
59
60 enum mt7996_rxq_id {
61 MT7996_RXQ_MCU_WM = 0,
62 MT7996_RXQ_MCU_WA,
63 MT7996_RXQ_MCU_WA_MAIN = 2,
64 MT7996_RXQ_MCU_WA_EXT = 2,/* unused */
65 MT7996_RXQ_MCU_WA_TRI = 3,
66 MT7996_RXQ_BAND0 = 4,
67 MT7996_RXQ_BAND1 = 4,/* unused */
68 MT7996_RXQ_BAND2 = 5,
69 };
70
71 struct mt7996_twt_flow {
72 struct list_head list;
73 u64 start_tsf;
74 u64 tsf;
75 u32 duration;
76 u16 wcid;
77 __le16 mantissa;
78 u8 exp;
79 u8 table_id;
80 u8 id;
81 u8 protection:1;
82 u8 flowtype:1;
83 u8 trigger:1;
84 u8 sched:1;
85 };
86
87 DECLARE_EWMA(avg_signal, 10, 8)
88
89 struct mt7996_sta {
90 struct mt76_wcid wcid; /* must be first */
91
92 struct mt7996_vif *vif;
93
94 struct list_head poll_list;
95 struct list_head rc_list;
96 u32 airtime_ac[8];
97
98 int ack_signal;
99 struct ewma_avg_signal avg_ack_signal;
100
101 unsigned long changed;
102 unsigned long jiffies;
103 unsigned long ampdu_state;
104
105 struct mt76_sta_stats stats;
106
107 struct mt76_connac_sta_key_conf bip;
108
109 struct {
110 u8 flowid_mask;
111 struct mt7996_twt_flow flow[MT7996_MAX_STA_TWT_AGRT];
112 } twt;
113 };
114
115 struct mt7996_vif_cap {
116 bool ht_ldpc:1;
117 bool vht_ldpc:1;
118 bool he_ldpc:1;
119 bool vht_su_ebfer:1;
120 bool vht_su_ebfee:1;
121 bool vht_mu_ebfer:1;
122 bool vht_mu_ebfee:1;
123 bool he_su_ebfer:1;
124 bool he_su_ebfee:1;
125 bool he_mu_ebfer:1;
126 bool eht_su_ebfer:1;
127 bool eht_su_ebfee:1;
128 };
129
130 struct mt7996_vif {
131 struct mt76_vif mt76; /* must be first */
132
133 struct mt7996_vif_cap cap;
134 struct mt7996_sta sta;
135 struct mt7996_phy *phy;
136
137 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS];
138 struct cfg80211_bitrate_mask bitrate_mask;
139 };
140
141 /* per-phy stats. */
142 struct mib_stats {
143 u32 ack_fail_cnt;
144 u32 fcs_err_cnt;
145 u32 rts_cnt;
146 u32 rts_retries_cnt;
147 u32 ba_miss_cnt;
148 u32 tx_mu_bf_cnt;
149 u32 tx_mu_mpdu_cnt;
150 u32 tx_mu_acked_mpdu_cnt;
151 u32 tx_su_acked_mpdu_cnt;
152 u32 tx_bf_ibf_ppdu_cnt;
153 u32 tx_bf_ebf_ppdu_cnt;
154
155 u32 tx_bf_rx_fb_all_cnt;
156 u32 tx_bf_rx_fb_eht_cnt;
157 u32 tx_bf_rx_fb_he_cnt;
158 u32 tx_bf_rx_fb_vht_cnt;
159 u32 tx_bf_rx_fb_ht_cnt;
160
161 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */
162 u32 tx_bf_rx_fb_nc_cnt;
163 u32 tx_bf_rx_fb_nr_cnt;
164 u32 tx_bf_fb_cpl_cnt;
165 u32 tx_bf_fb_trig_cnt;
166
167 u32 tx_ampdu_cnt;
168 u32 tx_stop_q_empty_cnt;
169 u32 tx_mpdu_attempts_cnt;
170 u32 tx_mpdu_success_cnt;
171 /* BF counter is PPDU-based, so remove MPDU-based BF counter */
172
173 u32 tx_rwp_fail_cnt;
174 u32 tx_rwp_need_cnt;
175
176 /* rx stats */
177 u32 rx_fifo_full_cnt;
178 u32 channel_idle_cnt;
179 u32 rx_vector_mismatch_cnt;
180 u32 rx_delimiter_fail_cnt;
181 u32 rx_len_mismatch_cnt;
182 u32 rx_mpdu_cnt;
183 u32 rx_ampdu_cnt;
184 u32 rx_ampdu_bytes_cnt;
185 u32 rx_ampdu_valid_subframe_cnt;
186 u32 rx_ampdu_valid_subframe_bytes_cnt;
187 u32 rx_pfdrop_cnt;
188 u32 rx_vec_queue_overflow_drop_cnt;
189 u32 rx_ba_cnt;
190
191 u32 tx_amsdu[8];
192 u32 tx_amsdu_cnt;
193 };
194
195 struct mt7996_hif {
196 struct list_head list;
197
198 struct device *dev;
199 void __iomem *regs;
200 int irq;
201 };
202
203 struct mt7996_phy {
204 struct mt76_phy *mt76;
205 struct mt7996_dev *dev;
206
207 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
208
209 struct ieee80211_vif *monitor_vif;
210
211 u32 rxfilter;
212 u64 omac_mask;
213
214 u16 noise;
215
216 s16 coverage_class;
217 u8 slottime;
218
219 u8 rdd_state;
220
221 u32 rx_ampdu_ts;
222 u32 ampdu_ref;
223
224 struct mib_stats mib;
225 struct mt76_channel_state state_ts;
226 };
227
228 struct mt7996_dev {
229 union { /* must be first */
230 struct mt76_dev mt76;
231 struct mt76_phy mphy;
232 };
233
234 struct mt7996_hif *hif2;
235 struct mt7996_reg_desc reg;
236 u8 q_id[MT7996_MAX_QUEUE];
237 u32 q_int_mask[MT7996_MAX_QUEUE];
238 u32 q_wfdma_mask;
239
240 const struct mt76_bus_ops *bus_ops;
241 struct tasklet_struct irq_tasklet;
242 struct mt7996_phy phy;
243
244 /* monitor rx chain configured channel */
245 struct cfg80211_chan_def rdd2_chandef;
246 struct mt7996_phy *rdd2_phy;
247
248 u16 chainmask;
249 u8 chainshift[__MT_MAX_BAND];
250 u32 hif_idx;
251
252 struct work_struct init_work;
253 struct work_struct rc_work;
254 struct work_struct reset_work;
255 wait_queue_head_t reset_wait;
256 u32 reset_state;
257
258 struct list_head sta_rc_list;
259 struct list_head sta_poll_list;
260 struct list_head twt_list;
261 spinlock_t sta_poll_lock;
262
263 u32 hw_pattern;
264
265 bool dbdc_support:1;
266 bool tbtc_support:1;
267 bool flash_mode:1;
268 bool has_eht:1;
269
270 bool ibf;
271 u8 fw_debug_wm;
272 u8 fw_debug_wa;
273 u8 fw_debug_bin;
274 u16 fw_debug_seq;
275
276 struct dentry *debugfs_dir;
277 struct rchan *relay_fwlog;
278
279 struct {
280 u8 table_mask;
281 u8 n_agrt;
282 } twt;
283
284 u32 reg_l1_backup;
285 u32 reg_l2_backup;
286
287 u8 wtbl_size_group;
288 };
289
290 enum {
291 WFDMA0 = 0x0,
292 WFDMA1,
293 WFDMA_EXT,
294 __MT_WFDMA_MAX,
295 };
296
297 enum {
298 MT_CTX0,
299 MT_HIF0 = 0x0,
300
301 MT_LMAC_AC00 = 0x0,
302 MT_LMAC_AC01,
303 MT_LMAC_AC02,
304 MT_LMAC_AC03,
305 MT_LMAC_ALTX0 = 0x10,
306 MT_LMAC_BMC0,
307 MT_LMAC_BCN0,
308 MT_LMAC_PSMP0,
309 };
310
311 enum {
312 MT_RX_SEL0,
313 MT_RX_SEL1,
314 MT_RX_SEL2, /* monitor chain */
315 };
316
317 enum mt7996_rdd_cmd {
318 RDD_STOP,
319 RDD_START,
320 RDD_DET_MODE,
321 RDD_RADAR_EMULATE,
322 RDD_START_TXQ = 20,
323 RDD_CAC_START = 50,
324 RDD_CAC_END,
325 RDD_NORMAL_START,
326 RDD_DISABLE_DFS_CAL,
327 RDD_PULSE_DBG,
328 RDD_READ_PULSE,
329 RDD_RESUME_BF,
330 RDD_IRQ_OFF,
331 };
332
333 static inline struct mt7996_phy *
mt7996_hw_phy(struct ieee80211_hw * hw)334 mt7996_hw_phy(struct ieee80211_hw *hw)
335 {
336 struct mt76_phy *phy = hw->priv;
337
338 return phy->priv;
339 }
340
341 static inline struct mt7996_dev *
mt7996_hw_dev(struct ieee80211_hw * hw)342 mt7996_hw_dev(struct ieee80211_hw *hw)
343 {
344 struct mt76_phy *phy = hw->priv;
345
346 return container_of(phy->dev, struct mt7996_dev, mt76);
347 }
348
349 static inline struct mt7996_phy *
__mt7996_phy(struct mt7996_dev * dev,enum mt76_band_id band)350 __mt7996_phy(struct mt7996_dev *dev, enum mt76_band_id band)
351 {
352 struct mt76_phy *phy = dev->mt76.phys[band];
353
354 if (!phy)
355 return NULL;
356
357 return phy->priv;
358 }
359
360 static inline struct mt7996_phy *
mt7996_phy2(struct mt7996_dev * dev)361 mt7996_phy2(struct mt7996_dev *dev)
362 {
363 return __mt7996_phy(dev, MT_BAND1);
364 }
365
366 static inline struct mt7996_phy *
mt7996_phy3(struct mt7996_dev * dev)367 mt7996_phy3(struct mt7996_dev *dev)
368 {
369 return __mt7996_phy(dev, MT_BAND2);
370 }
371
372 extern const struct ieee80211_ops mt7996_ops;
373 extern struct pci_driver mt7996_pci_driver;
374 extern struct pci_driver mt7996_hif_driver;
375
376 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev,
377 void __iomem *mem_base, u32 device_id);
378 void mt7996_wfsys_reset(struct mt7996_dev *dev);
379 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance);
380 u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif *mvif);
381 int mt7996_register_device(struct mt7996_dev *dev);
382 void mt7996_unregister_device(struct mt7996_dev *dev);
383 int mt7996_eeprom_init(struct mt7996_dev *dev);
384 int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy);
385 int mt7996_eeprom_get_target_power(struct mt7996_dev *dev,
386 struct ieee80211_channel *chan);
387 s8 mt7996_eeprom_get_power_delta(struct mt7996_dev *dev, int band);
388 int mt7996_dma_init(struct mt7996_dev *dev);
389 void mt7996_dma_prefetch(struct mt7996_dev *dev);
390 void mt7996_dma_cleanup(struct mt7996_dev *dev);
391 int mt7996_mcu_init(struct mt7996_dev *dev);
392 int mt7996_mcu_twt_agrt_update(struct mt7996_dev *dev,
393 struct mt7996_vif *mvif,
394 struct mt7996_twt_flow *flow,
395 int cmd);
396 int mt7996_mcu_add_dev_info(struct mt7996_phy *phy,
397 struct ieee80211_vif *vif, bool enable);
398 int mt7996_mcu_add_bss_info(struct mt7996_phy *phy,
399 struct ieee80211_vif *vif, int enable);
400 int mt7996_mcu_add_sta(struct mt7996_dev *dev, struct ieee80211_vif *vif,
401 struct ieee80211_sta *sta, bool enable);
402 int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev,
403 struct ieee80211_ampdu_params *params,
404 bool add);
405 int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev,
406 struct ieee80211_ampdu_params *params,
407 bool add);
408 int mt7996_mcu_update_bss_color(struct mt7996_dev *dev, struct ieee80211_vif *vif,
409 struct cfg80211_he_bss_color *he_bss_color);
410 int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
411 int enable);
412 int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev,
413 struct ieee80211_vif *vif, u32 changed);
414 int mt7996_mcu_add_obss_spr(struct mt7996_phy *phy, struct ieee80211_vif *vif,
415 struct ieee80211_he_obss_pd *he_obss_pd);
416 int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct ieee80211_vif *vif,
417 struct ieee80211_sta *sta, bool changed);
418 int mt7996_set_channel(struct mt7996_phy *phy);
419 int mt7996_mcu_set_chan_info(struct mt7996_phy *phy, u16 tag);
420 int mt7996_mcu_set_tx(struct mt7996_dev *dev, struct ieee80211_vif *vif);
421 int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev,
422 void *data, u16 version);
423 int mt7996_mcu_set_eeprom(struct mt7996_dev *dev);
424 int mt7996_mcu_get_eeprom(struct mt7996_dev *dev, u32 offset);
425 int mt7996_mcu_get_eeprom_free_block(struct mt7996_dev *dev, u8 *block_num);
426 int mt7996_mcu_get_chip_config(struct mt7996_dev *dev, u32 *cap);
427 int mt7996_mcu_set_ser(struct mt7996_dev *dev, u8 action, u8 set, u8 band);
428 int mt7996_mcu_set_txbf(struct mt7996_dev *dev, u8 action);
429 int mt7996_mcu_set_fcc5_lpn(struct mt7996_dev *dev, int val);
430 int mt7996_mcu_set_pulse_th(struct mt7996_dev *dev,
431 const struct mt7996_dfs_pulse *pulse);
432 int mt7996_mcu_set_radar_th(struct mt7996_dev *dev, int index,
433 const struct mt7996_dfs_pattern *pattern);
434 int mt7996_mcu_set_radio_en(struct mt7996_phy *phy, bool enable);
435 void mt7996_mcu_set_pm(void *priv, u8 *mac, struct ieee80211_vif *vif);
436 int mt7996_mcu_set_rts_thresh(struct mt7996_phy *phy, u32 val);
437 int mt7996_mcu_get_chan_mib_info(struct mt7996_phy *phy, bool chan_switch);
438 int mt7996_mcu_rdd_cmd(struct mt7996_dev *dev, int cmd, u8 index,
439 u8 rx_sel, u8 val);
440 int mt7996_mcu_rdd_background_enable(struct mt7996_phy *phy,
441 struct cfg80211_chan_def *chandef);
442 int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set);
443 int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans);
444 int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u8 val);
445 int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3);
446 int mt7996_mcu_fw_log_2_host(struct mt7996_dev *dev, u8 type, u8 ctrl);
447 int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level);
448 void mt7996_mcu_rx_event(struct mt7996_dev *dev, struct sk_buff *skb);
449 void mt7996_mcu_exit(struct mt7996_dev *dev);
450
mt7996_max_interface_num(struct mt7996_dev * dev)451 static inline u8 mt7996_max_interface_num(struct mt7996_dev *dev)
452 {
453 return MT7996_MAX_INTERFACES * (1 + dev->dbdc_support + dev->tbtc_support);
454 }
455
mt7996_wtbl_size(struct mt7996_dev * dev)456 static inline u16 mt7996_wtbl_size(struct mt7996_dev *dev)
457 {
458 return (dev->wtbl_size_group << 8) + 64;
459 }
460
461 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg,
462 u32 clear, u32 set);
463
mt7996_irq_enable(struct mt7996_dev * dev,u32 mask)464 static inline void mt7996_irq_enable(struct mt7996_dev *dev, u32 mask)
465 {
466 if (dev->hif2)
467 mt7996_dual_hif_set_irq_mask(dev, false, 0, mask);
468 else
469 mt76_set_irq_mask(&dev->mt76, 0, 0, mask);
470
471 tasklet_schedule(&dev->irq_tasklet);
472 }
473
mt7996_irq_disable(struct mt7996_dev * dev,u32 mask)474 static inline void mt7996_irq_disable(struct mt7996_dev *dev, u32 mask)
475 {
476 if (dev->hif2)
477 mt7996_dual_hif_set_irq_mask(dev, true, mask, 0);
478 else
479 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
480 }
481
482 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw);
483 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask);
484 void mt7996_mac_reset_counters(struct mt7996_phy *phy);
485 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy);
486 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band);
487 void mt7996_mac_enable_rtscts(struct mt7996_dev *dev,
488 struct ieee80211_vif *vif, bool enable);
489 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
490 struct sk_buff *skb, struct mt76_wcid *wcid, int pid,
491 struct ieee80211_key_conf *key, u32 changed);
492 void mt7996_mac_set_timing(struct mt7996_phy *phy);
493 int mt7996_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
494 struct ieee80211_sta *sta);
495 void mt7996_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
496 struct ieee80211_sta *sta);
497 void mt7996_mac_work(struct work_struct *work);
498 void mt7996_mac_reset_work(struct work_struct *work);
499 void mt7996_mac_sta_rc_work(struct work_struct *work);
500 void mt7996_mac_update_stats(struct mt7996_phy *phy);
501 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev,
502 struct mt7996_sta *msta,
503 u8 flowid);
504 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw,
505 struct ieee80211_sta *sta,
506 struct ieee80211_twt_setup *twt);
507 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
508 enum mt76_txq_id qid, struct mt76_wcid *wcid,
509 struct ieee80211_sta *sta,
510 struct mt76_tx_info *tx_info);
511 void mt7996_tx_token_put(struct mt7996_dev *dev);
512 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
513 struct sk_buff *skb, u32 *info);
514 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len);
515 void mt7996_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
516 void mt7996_stats_work(struct work_struct *work);
517 int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force);
518 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy);
519 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy);
520 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy);
521 void mt7996_update_channel(struct mt76_phy *mphy);
522 int mt7996_init_debugfs(struct mt7996_phy *phy);
523 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len);
524 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len);
525 int mt7996_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
526 struct mt76_connac_sta_key_conf *sta_key_conf,
527 struct ieee80211_key_conf *key, int mcu_cmd,
528 struct mt76_wcid *wcid, enum set_key_cmd cmd);
529 int mt7996_mcu_wtbl_update_hdr_trans(struct mt7996_dev *dev,
530 struct ieee80211_vif *vif,
531 struct ieee80211_sta *sta);
532 #ifdef CONFIG_MAC80211_DEBUGFS
533 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
534 struct ieee80211_sta *sta, struct dentry *dir);
535 #endif
536
537 #endif
538