1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_hal_dma.h 4 * @author MCD Application Team 5 * @version V1.0.1 6 * @date 25-June-2015 7 * @brief Header file of DMA HAL module. 8 ****************************************************************************** 9 * @attention 10 * 11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 12 * 13 * Redistribution and use in source and binary forms, with or without modification, 14 * are permitted provided that the following conditions are met: 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright notice, 18 * this list of conditions and the following disclaimer in the documentation 19 * and/or other materials provided with the distribution. 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 ****************************************************************************** 36 */ 37 38 /* Define to prevent recursive inclusion -------------------------------------*/ 39 #ifndef __STM32F7xx_HAL_DMA_H 40 #define __STM32F7xx_HAL_DMA_H 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 /* Includes ------------------------------------------------------------------*/ 47 #include "stm32f7xx_hal_def.h" 48 49 /** @addtogroup STM32F7xx_HAL_Driver 50 * @{ 51 */ 52 53 /** @addtogroup DMA 54 * @{ 55 */ 56 57 /* Exported types ------------------------------------------------------------*/ 58 59 /** @defgroup DMA_Exported_Types DMA Exported Types 60 * @brief DMA Exported Types 61 * @{ 62 */ 63 64 /** 65 * @brief DMA Configuration Structure definition 66 */ 67 typedef struct { 68 uint32_t Channel; /*!< Specifies the channel used for the specified stream. 69 This parameter can be a value of @ref DMA_Channel_selection */ 70 71 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 72 from memory to memory or from peripheral to memory. 73 This parameter can be a value of @ref DMA_Data_transfer_direction */ 74 75 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 76 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 77 78 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 79 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 80 81 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 82 This parameter can be a value of @ref DMA_Peripheral_data_size */ 83 84 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 85 This parameter can be a value of @ref DMA_Memory_data_size */ 86 87 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. 88 This parameter can be a value of @ref DMA_mode 89 @note The circular buffer mode cannot be used if the memory-to-memory 90 data transfer is configured on the selected Stream */ 91 92 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. 93 This parameter can be a value of @ref DMA_Priority_level */ 94 95 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. 96 This parameter can be a value of @ref DMA_FIFO_direct_mode 97 @note The Direct mode (FIFO mode disabled) cannot be used if the 98 memory-to-memory data transfer is configured on the selected stream */ 99 100 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. 101 This parameter can be a value of @ref DMA_FIFO_threshold_level */ 102 103 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. 104 It specifies the amount of data to be transferred in a single non interruptible 105 transaction. 106 This parameter can be a value of @ref DMA_Memory_burst 107 @note The burst mode is possible only if the address Increment mode is enabled. */ 108 109 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. 110 It specifies the amount of data to be transferred in a single non interruptible 111 transaction. 112 This parameter can be a value of @ref DMA_Peripheral_burst 113 @note The burst mode is possible only if the address Increment mode is enabled. */ 114 } DMA_InitTypeDef; 115 116 /** 117 * @brief HAL DMA State structures definition 118 */ 119 typedef enum { 120 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ 121 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ 122 HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */ 123 HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */ 124 HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */ 125 HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */ 126 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ 127 HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */ 128 HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */ 129 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ 130 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ 131 } HAL_DMA_StateTypeDef; 132 133 /** 134 * @brief HAL DMA Error Code structure definition 135 */ 136 typedef enum { 137 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ 138 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ 139 } HAL_DMA_LevelCompleteTypeDef; 140 141 /** 142 * @brief DMA handle Structure definition 143 */ 144 typedef struct __DMA_HandleTypeDef { 145 DMA_Stream_TypeDef *Instance; /*!< Register base address */ 146 147 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 148 149 HAL_LockTypeDef Lock; /*!< DMA locking object */ 150 151 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 152 153 void *Parent; /*!< Parent object state */ 154 155 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 156 157 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 158 159 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ 160 161 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 162 163 __IO uint32_t ErrorCode; /*!< DMA Error code */ 164 } DMA_HandleTypeDef; 165 166 /** 167 * @} 168 */ 169 170 171 /* Exported constants --------------------------------------------------------*/ 172 173 /** @defgroup DMA_Exported_Constants DMA Exported Constants 174 * @brief DMA Exported constants 175 * @{ 176 */ 177 178 /** @defgroup DMA_Error_Code DMA Error Code 179 * @brief DMA Error Code 180 * @{ 181 */ 182 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ 183 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ 184 #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */ 185 #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */ 186 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ 187 /** 188 * @} 189 */ 190 191 /** @defgroup DMA_Channel_selection DMA Channel selection 192 * @brief DMA channel selection 193 * @{ 194 */ 195 #define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */ 196 #define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */ 197 #define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */ 198 #define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */ 199 #define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */ 200 #define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */ 201 #define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */ 202 #define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */ 203 /** 204 * @} 205 */ 206 207 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 208 * @brief DMA data transfer direction 209 * @{ 210 */ 211 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ 212 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ 213 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ 214 /** 215 * @} 216 */ 217 218 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 219 * @brief DMA peripheral incremented mode 220 * @{ 221 */ 222 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ 223 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */ 224 /** 225 * @} 226 */ 227 228 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 229 * @brief DMA memory incremented mode 230 * @{ 231 */ 232 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ 233 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */ 234 /** 235 * @} 236 */ 237 238 239 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 240 * @brief DMA peripheral data size 241 * @{ 242 */ 243 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */ 244 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ 245 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ 246 /** 247 * @} 248 */ 249 250 251 /** @defgroup DMA_Memory_data_size DMA Memory data size 252 * @brief DMA memory data size 253 * @{ 254 */ 255 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */ 256 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ 257 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ 258 /** 259 * @} 260 */ 261 262 /** @defgroup DMA_mode DMA mode 263 * @brief DMA mode 264 * @{ 265 */ 266 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ 267 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ 268 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ 269 /** 270 * @} 271 */ 272 273 274 /** @defgroup DMA_Priority_level DMA Priority level 275 * @brief DMA priority levels 276 * @{ 277 */ 278 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */ 279 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ 280 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ 281 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ 282 /** 283 * @} 284 */ 285 286 287 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode 288 * @brief DMA FIFO direct mode 289 * @{ 290 */ 291 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */ 292 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ 293 /** 294 * @} 295 */ 296 297 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level 298 * @brief DMA FIFO level 299 * @{ 300 */ 301 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */ 302 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ 303 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ 304 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ 305 /** 306 * @} 307 */ 308 309 /** @defgroup DMA_Memory_burst DMA Memory burst 310 * @brief DMA memory burst 311 * @{ 312 */ 313 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000) 314 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) 315 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) 316 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) 317 /** 318 * @} 319 */ 320 321 322 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst 323 * @brief DMA peripheral burst 324 * @{ 325 */ 326 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000) 327 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) 328 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) 329 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) 330 /** 331 * @} 332 */ 333 334 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 335 * @brief DMA interrupts definition 336 * @{ 337 */ 338 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) 339 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) 340 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) 341 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) 342 #define DMA_IT_FE ((uint32_t)0x00000080) 343 /** 344 * @} 345 */ 346 347 /** @defgroup DMA_flag_definitions DMA flag definitions 348 * @brief DMA flag definitions 349 * @{ 350 */ 351 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001) 352 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004) 353 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008) 354 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010) 355 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020) 356 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040) 357 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100) 358 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200) 359 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400) 360 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800) 361 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000) 362 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000) 363 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000) 364 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000) 365 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000) 366 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000) 367 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000) 368 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000) 369 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000) 370 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000) 371 /** 372 * @} 373 */ 374 375 /** 376 * @} 377 */ 378 379 /* Exported macro ------------------------------------------------------------*/ 380 381 /** @brief Reset DMA handle state 382 * @param __HANDLE__: specifies the DMA handle. 383 * @retval None 384 */ 385 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 386 387 /** 388 * @brief Return the current DMA Stream FIFO filled level. 389 * @param __HANDLE__: DMA handle 390 * @retval The FIFO filling state. 391 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 392 * and not empty. 393 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. 394 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. 395 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. 396 * - DMA_FIFOStatus_Empty: when FIFO is empty 397 * - DMA_FIFOStatus_Full: when FIFO is full 398 */ 399 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) 400 401 /** 402 * @brief Enable the specified DMA Stream. 403 * @param __HANDLE__: DMA handle 404 * @retval None 405 */ 406 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) 407 408 /** 409 * @brief Disable the specified DMA Stream. 410 * @param __HANDLE__: DMA handle 411 * @retval None 412 */ 413 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) 414 415 /* Interrupt & Flag management */ 416 417 /** 418 * @brief Return the current DMA Stream transfer complete flag. 419 * @param __HANDLE__: DMA handle 420 * @retval The specified transfer complete flag index. 421 */ 422 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 423 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ 424 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ 425 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ 426 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ 427 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ 428 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ 429 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ 430 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ 431 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ 432 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ 433 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ 434 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ 435 DMA_FLAG_TCIF3_7) 436 437 /** 438 * @brief Return the current DMA Stream half transfer complete flag. 439 * @param __HANDLE__: DMA handle 440 * @retval The specified half transfer complete flag index. 441 */ 442 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 443 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ 444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ 445 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ 446 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ 447 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ 448 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ 449 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ 450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ 451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ 452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ 455 DMA_FLAG_HTIF3_7) 456 457 /** 458 * @brief Return the current DMA Stream transfer error flag. 459 * @param __HANDLE__: DMA handle 460 * @retval The specified transfer error flag index. 461 */ 462 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 463 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ 468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ 469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ 475 DMA_FLAG_TEIF3_7) 476 477 /** 478 * @brief Return the current DMA Stream FIFO error flag. 479 * @param __HANDLE__: DMA handle 480 * @retval The specified FIFO error flag index. 481 */ 482 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ 483 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ 484 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ 485 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ 486 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ 491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ 492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ 495 DMA_FLAG_FEIF3_7) 496 497 /** 498 * @brief Return the current DMA Stream direct mode error flag. 499 * @param __HANDLE__: DMA handle 500 * @retval The specified direct mode error flag index. 501 */ 502 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ 503 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ 511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ 512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ 514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ 515 DMA_FLAG_DMEIF3_7) 516 517 /** 518 * @brief Get the DMA Stream pending flags. 519 * @param __HANDLE__: DMA handle 520 * @param __FLAG__: Get the specified flag. 521 * This parameter can be any combination of the following values: 522 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 523 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 524 * @arg DMA_FLAG_TEIFx: Transfer error flag. 525 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 526 * @arg DMA_FLAG_FEIFx: FIFO error flag. 527 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 528 * @retval The state of FLAG (SET or RESET). 529 */ 530 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ 531 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ 532 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ 533 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) 534 535 /** 536 * @brief Clear the DMA Stream pending flags. 537 * @param __HANDLE__: DMA handle 538 * @param __FLAG__: specifies the flag to clear. 539 * This parameter can be any combination of the following values: 540 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 541 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 542 * @arg DMA_FLAG_TEIFx: Transfer error flag. 543 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 544 * @arg DMA_FLAG_FEIFx: FIFO error flag. 545 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 546 * @retval None 547 */ 548 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 549 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ 550 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ 551 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) 552 553 /** 554 * @brief Enable the specified DMA Stream interrupts. 555 * @param __HANDLE__: DMA handle 556 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 557 * This parameter can be any combination of the following values: 558 * @arg DMA_IT_TC: Transfer complete interrupt mask. 559 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 560 * @arg DMA_IT_TE: Transfer error interrupt mask. 561 * @arg DMA_IT_FE: FIFO error interrupt mask. 562 * @arg DMA_IT_DME: Direct mode error interrupt. 563 * @retval None 564 */ 565 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 566 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) 567 568 /** 569 * @brief Disable the specified DMA Stream interrupts. 570 * @param __HANDLE__: DMA handle 571 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 572 * This parameter can be any combination of the following values: 573 * @arg DMA_IT_TC: Transfer complete interrupt mask. 574 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 575 * @arg DMA_IT_TE: Transfer error interrupt mask. 576 * @arg DMA_IT_FE: FIFO error interrupt mask. 577 * @arg DMA_IT_DME: Direct mode error interrupt. 578 * @retval None 579 */ 580 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 581 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) 582 583 /** 584 * @brief Check whether the specified DMA Stream interrupt is enabled or not. 585 * @param __HANDLE__: DMA handle 586 * @param __INTERRUPT__: specifies the DMA interrupt source to check. 587 * This parameter can be one of the following values: 588 * @arg DMA_IT_TC: Transfer complete interrupt mask. 589 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 590 * @arg DMA_IT_TE: Transfer error interrupt mask. 591 * @arg DMA_IT_FE: FIFO error interrupt mask. 592 * @arg DMA_IT_DME: Direct mode error interrupt. 593 * @retval The state of DMA_IT. 594 */ 595 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 596 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ 597 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) 598 599 /** 600 * @brief Writes the number of data units to be transferred on the DMA Stream. 601 * @param __HANDLE__: DMA handle 602 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) 603 * Number of data items depends only on the Peripheral data format. 604 * 605 * @note If Peripheral data format is Bytes: number of data units is equal 606 * to total number of bytes to be transferred. 607 * 608 * @note If Peripheral data format is Half-Word: number of data units is 609 * equal to total number of bytes to be transferred / 2. 610 * 611 * @note If Peripheral data format is Word: number of data units is equal 612 * to total number of bytes to be transferred / 4. 613 * 614 * @retval The number of remaining data units in the current DMAy Streamx transfer. 615 */ 616 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) 617 618 /** 619 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. 620 * @param __HANDLE__: DMA handle 621 * 622 * @retval The number of remaining data units in the current DMA Stream transfer. 623 */ 624 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) 625 626 627 /* Include DMA HAL Extension module */ 628 #include "stm32f7xx_hal_dma_ex.h" 629 630 /* Exported functions --------------------------------------------------------*/ 631 632 /** @defgroup DMA_Exported_Functions DMA Exported Functions 633 * @brief DMA Exported functions 634 * @{ 635 */ 636 637 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions 638 * @brief Initialization and de-initialization functions 639 * @{ 640 */ 641 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 642 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 643 /** 644 * @} 645 */ 646 647 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions 648 * @brief I/O operation functions 649 * @{ 650 */ 651 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 652 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 653 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 654 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); 655 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 656 /** 657 * @} 658 */ 659 660 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions 661 * @brief Peripheral State functions 662 * @{ 663 */ 664 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 665 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 666 /** 667 * @} 668 */ 669 /** 670 * @} 671 */ 672 /* Private Constants -------------------------------------------------------------*/ 673 /** @defgroup DMA_Private_Constants DMA Private Constants 674 * @brief DMA private defines and constants 675 * @{ 676 */ 677 /** 678 * @} 679 */ 680 681 /* Private macros ------------------------------------------------------------*/ 682 /** @defgroup DMA_Private_Macros DMA Private Macros 683 * @brief DMA private macros 684 * @{ 685 */ 686 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ 687 ((CHANNEL) == DMA_CHANNEL_1) || \ 688 ((CHANNEL) == DMA_CHANNEL_2) || \ 689 ((CHANNEL) == DMA_CHANNEL_3) || \ 690 ((CHANNEL) == DMA_CHANNEL_4) || \ 691 ((CHANNEL) == DMA_CHANNEL_5) || \ 692 ((CHANNEL) == DMA_CHANNEL_6) || \ 693 ((CHANNEL) == DMA_CHANNEL_7)) 694 695 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 696 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 697 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 698 699 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) 700 701 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 702 ((STATE) == DMA_PINC_DISABLE)) 703 704 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 705 ((STATE) == DMA_MINC_DISABLE)) 706 707 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 708 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 709 ((SIZE) == DMA_PDATAALIGN_WORD)) 710 711 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 712 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 713 ((SIZE) == DMA_MDATAALIGN_WORD )) 714 715 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 716 ((MODE) == DMA_CIRCULAR) || \ 717 ((MODE) == DMA_PFCTRL)) 718 719 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 720 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 721 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 722 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 723 724 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ 725 ((STATE) == DMA_FIFOMODE_ENABLE)) 726 727 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ 728 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ 729 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ 730 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) 731 732 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ 733 ((BURST) == DMA_MBURST_INC4) || \ 734 ((BURST) == DMA_MBURST_INC8) || \ 735 ((BURST) == DMA_MBURST_INC16)) 736 737 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ 738 ((BURST) == DMA_PBURST_INC4) || \ 739 ((BURST) == DMA_PBURST_INC8) || \ 740 ((BURST) == DMA_PBURST_INC16)) 741 /** 742 * @} 743 */ 744 745 /* Private functions ---------------------------------------------------------*/ 746 /** @defgroup DMA_Private_Functions DMA Private Functions 747 * @brief DMA private functions 748 * @{ 749 */ 750 /** 751 * @} 752 */ 753 754 /** 755 * @} 756 */ 757 758 /** 759 * @} 760 */ 761 762 #ifdef __cplusplus 763 } 764 #endif 765 766 #endif /* __STM32F7xx_HAL_DMA_H */ 767 768 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 769