1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef CONFIG_CLOCK_H
9 #define CONFIG_CLOCK_H
10 
11 #include <fwk_macros.h>
12 
13 /*
14  * DDR Subsystem clock in MHz
15  */
16 #define DDR_CLOCK_MHZ (4000.0 / 3) // 1333Mhz
17 
18 /*
19  * SCC & PIK clock rates.
20  */
21 #define SCC_CLK_RATE_IOFPGA_TMIF2XCLK  (120 * FWK_MHZ)
22 #define SCC_CLK_RATE_IOFPGA_TSIF2XCLK  (120 * FWK_MHZ)
23 #define SCC_CLK_RATE_SYSAPBCLK         (120 * FWK_MHZ)
24 #define SCC_CLK_RATE_SCPNICCLK         (300 * FWK_MHZ)
25 #define SCC_CLK_RATE_SCPI2CCLK         (100 * FWK_MHZ)
26 #define SCC_CLK_RATE_SCPQSPICLK        (50 * FWK_MHZ)
27 #define SCC_CLK_RATE_SENSORCLK         (100 * FWK_MHZ)
28 #define SCC_CLK_RATE_MCPNICCLK         (300 * FWK_MHZ)
29 #define SCC_CLK_RATE_MCPI2CCLK         (100 * FWK_MHZ)
30 #define SCC_CLK_RATE_MCPQSPICLK        (50 * FWK_MHZ)
31 #define SCC_CLK_RATE_PCIEAXICLK        (1200 * FWK_MHZ)
32 #define SCC_CLK_RATE_CCIXAXICLK        (1200 * FWK_MHZ)
33 #define SCC_CLK_RATE_PCIEAPBCLK        (200 * FWK_MHZ)
34 #define SCC_CLK_RATE_CCIXAPBCLK        (200 * FWK_MHZ)
35 
36 #define PIK_CLK_RATE_CLUS0_CPU         (2600 * FWK_MHZ)
37 #define PIK_CLK_RATE_CLUS1_CPU         (2600 * FWK_MHZ)
38 #define PIK_CLK_RATE_CLUS0             (1600 * FWK_MHZ)
39 #define PIK_CLK_RATE_CLUS1             (1600 * FWK_MHZ)
40 #define PIK_CLK_RATE_CLUS0_PPU         (300 * FWK_MHZ)
41 #define PIK_CLK_RATE_CLUS1_PPU         (300 * FWK_MHZ)
42 #define PIK_CLK_RATE_CLUS0_PCLK        (900 * FWK_MHZ)
43 #define PIK_CLK_RATE_CLUS0_ATCLK       (900 * FWK_MHZ)
44 #define PIK_CLK_RATE_CLUS0_GIC         (900 * FWK_MHZ)
45 #define PIK_CLK_RATE_CLUS0_AMBACLK     (900 * FWK_MHZ)
46 #define PIK_CLK_RATE_CLUS1_PCLK        (900 * FWK_MHZ)
47 #define PIK_CLK_RATE_CLUS1_ATCLK       (900 * FWK_MHZ)
48 #define PIK_CLK_RATE_CLUS1_GIC         (900 * FWK_MHZ)
49 #define PIK_CLK_RATE_CLUS1_AMBACLK     (900 * FWK_MHZ)
50 
51 #define PIK_CLK_RATE_SCP_CORECLK       (300 * FWK_MHZ)
52 #define PIK_CLK_RATE_SCP_AXICLK        (300 * FWK_MHZ)
53 #define PIK_CLK_RATE_SCP_SYNCCLK       (150 * FWK_MHZ)
54 
55 #define PIK_CLK_RATE_SYS_PPU           (300 * FWK_MHZ)
56 #define PIK_CLK_RATE_INTERCONNECT      (1600 * FWK_MHZ)
57 #define PIK_CLK_RATE_PCLKSCP           (300 * FWK_MHZ)
58 #define PIK_CLK_RATE_SYS_GIC           (800 * FWK_MHZ)
59 #define PIK_CLK_RATE_SYSPCLKDBG        (300 * FWK_MHZ)
60 #define PIK_CLK_RATE_SYSPERCLK         (600 * FWK_MHZ)
61 #define PIK_CLK_RATE_UART              (50 * FWK_MHZ)
62 #define PIK_CLK_RATE_TCU0              (1200 * FWK_MHZ)
63 #define PIK_CLK_RATE_TCU1              (1200 * FWK_MHZ)
64 #define PIK_CLK_RATE_TCU2              (1200 * FWK_MHZ)
65 #define PIK_CLK_RATE_TCU3              (1200 * FWK_MHZ)
66 
67 #define PIK_CLK_RATE_ATCLKDBG          (600 * FWK_MHZ)
68 #define PIK_CLK_RATE_PCLKDBG           (300 * FWK_MHZ)
69 #define PIK_CLK_RATE_TRACECLK          (300 * FWK_MHZ)
70 #define PIK_CLK_RATE_DMC               (DDR_CLOCK_MHZ * FWK_MHZ)
71 
72 /*
73  * N1SDP PLL clock rates.
74  */
75 #define N1SDP_PLL_RATE_CPU_PLL0         (2600 * FWK_MHZ)
76 #define N1SDP_PLL_RATE_CPU_PLL1         (2600 * FWK_MHZ)
77 #define N1SDP_PLL_RATE_CLUSTER_PLL      (1600 * FWK_MHZ)
78 #define N1SDP_PLL_RATE_INTERCONNECT_PLL (1600 * FWK_MHZ)
79 #define N1SDP_PLL_RATE_SYSTEM_PLL       (2400 * FWK_MHZ)
80 #define N1SDP_PLL_RATE_DMC_PLL          (DDR_CLOCK_MHZ * FWK_MHZ)
81 
82 /*
83  * CSS clock rates.
84  */
85 #define CSS_CLK_RATE_CPU_GRP0_SUPER_UNDERDRIVE  (2600 * FWK_MHZ)
86 #define CSS_CLK_RATE_CPU_GRP0_UNDERDRIVE        (2700 * FWK_MHZ)
87 #define CSS_CLK_RATE_CPU_GRP0_NOMINAL           (2800 * FWK_MHZ)
88 #define CSS_CLK_RATE_CPU_GRP0_OVERDRIVE         (2900 * FWK_MHZ)
89 #define CSS_CLK_RATE_CPU_GRP0_SUPER_OVERDRIVE   (3000 * FWK_MHZ)
90 
91 #define CSS_CLK_RATE_CPU_GRP1_SUPER_UNDERDRIVE  (2600 * FWK_MHZ)
92 #define CSS_CLK_RATE_CPU_GRP1_UNDERDRIVE        (2700 * FWK_MHZ)
93 #define CSS_CLK_RATE_CPU_GRP1_NOMINAL           (2800 * FWK_MHZ)
94 #define CSS_CLK_RATE_CPU_GRP1_OVERDRIVE         (2900 * FWK_MHZ)
95 #define CSS_CLK_RATE_CPU_GRP1_SUPER_OVERDRIVE   (3000 * FWK_MHZ)
96 
97 #define OSC_FREQ_HZ                             (24 * FWK_MHZ)
98 /*
99  * Clock indexes.
100  */
101 enum clock_idx {
102     CLOCK_IDX_INTERCONNECT,
103     CLOCK_IDX_CPU_GROUP0,
104     CLOCK_IDX_CPU_GROUP1,
105     CLOCK_IDX_COUNT
106 };
107 
108 /*
109  * SCC & PIK clock indexes.
110  */
111 enum clock_pik_idx {
112     /* SCC Clocks */
113     CLOCK_SCC_IDX_IOFPGA_TMIF2XCLK,
114     CLOCK_SCC_IDX_IOFPGA_TSIF2XCLK,
115     CLOCK_SCC_IDX_SYSAPBCLK,
116     CLOCK_SCC_IDX_SCPNICCLK,
117     CLOCK_SCC_IDX_SCPI2CCLK,
118     CLOCK_SCC_IDX_SCPQSPICLK,
119     CLOCK_SCC_IDX_SENSORCLK,
120     CLOCK_SCC_IDX_MCPNICCLK,
121     CLOCK_SCC_IDX_MCPI2CCLK,
122     CLOCK_SCC_IDX_MCPQSPICLK,
123     CLOCK_SCC_IDX_PCIEAXICLK,
124     CLOCK_SCC_IDX_CCIXAXICLK,
125     CLOCK_SCC_IDX_PCIEAPBCLK,
126     CLOCK_SCC_IDX_CCIXAPBCLK,
127 
128     /* PIK Clocks */
129 
130     /* CPU element clocks */
131     CLOCK_PIK_IDX_CLUS0_CPU0,
132     CLOCK_PIK_IDX_CLUS0_CPU1,
133     CLOCK_PIK_IDX_CLUS1_CPU0,
134     CLOCK_PIK_IDX_CLUS1_CPU1,
135     CLOCK_PIK_IDX_CLUS0,
136     CLOCK_PIK_IDX_CLUS1,
137     CLOCK_PIK_IDX_CLUS0_PPU,
138     CLOCK_PIK_IDX_CLUS1_PPU,
139     CLOCK_PIK_IDX_CLUS0_PCLK,
140     CLOCK_PIK_IDX_CLUS0_ATCLK,
141     CLOCK_PIK_IDX_CLUS0_GIC,
142     CLOCK_PIK_IDX_CLUS0_AMBACLK,
143     CLOCK_PIK_IDX_CLUS1_PCLK,
144     CLOCK_PIK_IDX_CLUS1_ATCLK,
145     CLOCK_PIK_IDX_CLUS1_GIC,
146     CLOCK_PIK_IDX_CLUS1_AMBACLK,
147     /* SCP element clocks */
148     CLOCK_PIK_IDX_SCP_CORECLK,
149     CLOCK_PIK_IDX_SCP_AXICLK,
150     CLOCK_PIK_IDX_SCP_SYNCCLK,
151     /* Top element clocks */
152     CLOCK_PIK_IDX_SYS_PPU,
153     CLOCK_PIK_IDX_INTERCONNECT,
154     CLOCK_PIK_IDX_PCLKSCP,
155     CLOCK_PIK_IDX_SYS_GIC,
156     CLOCK_PIK_IDX_SYSPCLKDBG,
157     CLOCK_PIK_IDX_SYSPERCLK,
158     CLOCK_PIK_IDX_UART,
159     CLOCK_PIK_IDX_TCU0,
160     CLOCK_PIK_IDX_TCU1,
161     CLOCK_PIK_IDX_TCU2,
162     CLOCK_PIK_IDX_TCU3,
163     /* Debug element clocks */
164     CLOCK_PIK_IDX_ATCLKDBG,
165     CLOCK_PIK_IDX_PCLKDBG,
166     CLOCK_PIK_IDX_TRACECLK,
167     /* DMC element clock */
168     CLOCK_PIK_IDX_DMC,
169     /* Number of generated clocks */
170     CLOCK_PIK_IDX_COUNT
171 };
172 
173 /*
174  * CSS clock indexes.
175  */
176 enum clock_css_idx {
177     CLOCK_CSS_IDX_CPU_GROUP0,
178     CLOCK_CSS_IDX_CPU_GROUP1,
179     CLOCK_CSS_IDX_COUNT
180 };
181 
182 /*
183  * SoC PLL indexes.
184  */
185 enum clock_pll_idx {
186     CLOCK_PLL_IDX_CPU0,
187     CLOCK_PLL_IDX_CPU1,
188     CLOCK_PLL_IDX_CLUS,
189     CLOCK_PLL_IDX_INTERCONNECT,
190     CLOCK_PLL_IDX_SYS,
191     CLOCK_PLL_IDX_DMC,
192     CLOCK_PLL_IDX_COUNT
193 };
194 
195 #endif /* CONFIG_CLOCK_H */
196