1 /*
2  * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef NEOVERSE_V2_H
8 #define NEOVERSE_V2_H
9 
10 #define NEOVERSE_V2_MIDR				U(0x410FD4F0)
11 
12 /* Neoverse V2 loop count for CVE-2022-23960 mitigation */
13 #define NEOVERSE_V2_BHB_LOOP_COUNT			U(132)
14 
15 /*******************************************************************************
16  * CPU Extended Control register specific definitions
17  ******************************************************************************/
18 #define NEOVERSE_V2_CPUECTLR_EL1			S3_0_C15_C1_4
19 
20 /*******************************************************************************
21  * CPU Power Control register specific definitions
22  ******************************************************************************/
23 #define NEOVERSE_V2_CPUPWRCTLR_EL1			S3_0_C15_C2_7
24 #define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT	U(1)
25 
26 #endif /* NEOVERSE_V2_H */
27