1 /*
2 * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef NRF_GPIO_H__
33 #define NRF_GPIO_H__
34
35 #include <nrfx.h>
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 #ifndef NRF_P0
42 #define NRF_P0 NRF_GPIO
43 #endif
44
45 #if (GPIO_COUNT == 1)
46 #define NUMBER_OF_PINS (P0_PIN_NUM)
47 #define GPIO_REG_LIST {NRF_P0}
48 #elif (GPIO_COUNT == 2)
49 #define NUMBER_OF_PINS (P0_PIN_NUM + P1_PIN_NUM)
50 #define GPIO_REG_LIST {NRF_P0, NRF_P1}
51 #else
52 #error "Not supported."
53 #endif
54
55 #if defined(NRF52820_XXAA)
56 #include <nrf_erratas.h>
57 #endif
58
59 /**
60 * @defgroup nrf_gpio_hal GPIO HAL
61 * @{
62 * @ingroup nrf_gpio
63 * @brief Hardware access layer for managing the GPIO peripheral.
64 */
65
66 #if defined(GPIO_LATCH_PIN0_Msk) || defined(__NRFX_DOXYGEN__)
67 /** @brief Symbol indicating whether the functionality of latching GPIO state change is present. */
68 #define NRF_GPIO_LATCH_PRESENT
69 #endif
70
71 /** @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions. */
72 #define NRF_GPIO_PIN_MAP(port, pin) (((port) << 5) | ((pin) & 0x1F))
73
74
75 /** @brief Pin direction definitions. */
76 typedef enum
77 {
78 NRF_GPIO_PIN_DIR_INPUT = GPIO_PIN_CNF_DIR_Input, ///< Input.
79 NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< Output.
80 } nrf_gpio_pin_dir_t;
81
82 /** @brief Connection of input buffer. */
83 typedef enum
84 {
85 NRF_GPIO_PIN_INPUT_CONNECT = GPIO_PIN_CNF_INPUT_Connect, ///< Connect input buffer.
86 NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< Disconnect input buffer.
87 } nrf_gpio_pin_input_t;
88
89 /**
90 * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin
91 * configuration.
92 */
93 typedef enum
94 {
95 NRF_GPIO_PIN_NOPULL = GPIO_PIN_CNF_PULL_Disabled, ///< Pin pull-up resistor disabled.
96 NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown, ///< Pin pull-down resistor enabled.
97 NRF_GPIO_PIN_PULLUP = GPIO_PIN_CNF_PULL_Pullup, ///< Pin pull-up resistor enabled.
98 } nrf_gpio_pin_pull_t;
99
100 /** @brief Enumerator used for selecting output drive mode. */
101 typedef enum
102 {
103 NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< Standard '0', standard '1'.
104 NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< High drive '0', standard '1'.
105 NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< Standard '0', high drive '1'.
106 NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< High drive '0', high drive '1'.
107 NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< Disconnect '0' standard '1'.
108 NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< Disconnect '0', high drive '1'.
109 NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< Standard '0', disconnect '1'.
110 NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< High drive '0', disconnect '1'.
111 #if defined(GPIO_PIN_CNF_DRIVE_E0S1) || defined(__NRFX_DOXYGEN__)
112 NRF_GPIO_PIN_E0S1 = GPIO_PIN_CNF_DRIVE_E0S1, ///< Extra high drive '0', standard '1'.
113 #endif
114 #if defined(GPIO_PIN_CNF_DRIVE_S0E1) || defined(__NRFX_DOXYGEN__)
115 NRF_GPIO_PIN_S0E1 = GPIO_PIN_CNF_DRIVE_S0E1, ///< Standard '0', extra high drive '1'.
116 #endif
117 #if defined(GPIO_PIN_CNF_DRIVE_E0E1) || defined(__NRFX_DOXYGEN__)
118 NRF_GPIO_PIN_E0E1 = GPIO_PIN_CNF_DRIVE_E0E1, ///< Extra high drive '0', extra high drive '1'.
119 #endif
120 #if defined(GPIO_PIN_CNF_DRIVE_E0H1) || defined(__NRFX_DOXYGEN__)
121 NRF_GPIO_PIN_E0H1 = GPIO_PIN_CNF_DRIVE_E0H1, ///< Extra high drive '0', high drive '1'.
122 #endif
123 #if defined(GPIO_PIN_CNF_DRIVE_H0E1) || defined(__NRFX_DOXYGEN__)
124 NRF_GPIO_PIN_H0E1 = GPIO_PIN_CNF_DRIVE_H0E1, ///< High drive '0', extra high drive '1'.
125 #endif
126 #if defined(GPIO_PIN_CNF_DRIVE_D0E1) || defined(__NRFX_DOXYGEN__)
127 NRF_GPIO_PIN_D0E1 = GPIO_PIN_CNF_DRIVE_D0E1, ///< Disconnect '0', extra high drive '1'.
128 #endif
129 #if defined(GPIO_PIN_CNF_DRIVE_E0D1) || defined(__NRFX_DOXYGEN__)
130 NRF_GPIO_PIN_E0D1 = GPIO_PIN_CNF_DRIVE_E0D1, ///< Extra high drive '0', disconnect '1'.
131 #endif
132 } nrf_gpio_pin_drive_t;
133
134 /** @brief Enumerator used for selecting the pin to sense high or low level on the pin input. */
135 typedef enum
136 {
137 NRF_GPIO_PIN_NOSENSE = GPIO_PIN_CNF_SENSE_Disabled, ///< Pin sense level disabled.
138 NRF_GPIO_PIN_SENSE_LOW = GPIO_PIN_CNF_SENSE_Low, ///< Pin sense low level.
139 NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level.
140 } nrf_gpio_pin_sense_t;
141
142 #if defined(GPIO_PIN_CNF_MCUSEL_Msk) || defined(__NRFX_DOXYGEN__)
143 /** @brief Enumerator used for selecting the MCU/Subsystem to control the specified pin. */
144 typedef enum
145 {
146 NRF_GPIO_PIN_MCUSEL_APP = GPIO_PIN_CNF_MCUSEL_AppMCU, ///< Pin controlled by Application MCU.
147 NRF_GPIO_PIN_MCUSEL_NETWORK = GPIO_PIN_CNF_MCUSEL_NetworkMCU, ///< Pin controlled by Network MCU.
148 NRF_GPIO_PIN_MCUSEL_PERIPHERAL = GPIO_PIN_CNF_MCUSEL_Peripheral, ///< Pin controlled by dedicated peripheral.
149 NRF_GPIO_PIN_MCUSEL_TND = GPIO_PIN_CNF_MCUSEL_TND, ///< Pin controlled by Trace and Debug Subsystem.
150 } nrf_gpio_pin_mcusel_t;
151 #endif
152
153 /**
154 * @brief Function for configuring the GPIO pin range as output pins with normal drive strength.
155 * This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
156 *
157 * @note For configuring only one pin as output, use @ref nrf_gpio_cfg_output.
158 * Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
159 *
160 * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
161 * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
162 */
163 NRF_STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end);
164
165 /**
166 * @brief Function for configuring the GPIO pin range as input pins with given initial value set, hiding inner details.
167 * This function can be used to configure pin range as simple input.
168 *
169 * @note For configuring only one pin as input, use @ref nrf_gpio_cfg_input.
170 * Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
171 *
172 * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
173 * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
174 * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
175 */
176 NRF_STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start,
177 uint32_t pin_range_end,
178 nrf_gpio_pin_pull_t pull_config);
179
180 /**
181 * @brief Pin configuration function.
182 *
183 * The main pin configuration function.
184 * This function allows to set any aspect in PIN_CNF register.
185 *
186 * @param pin_number Specifies the pin number.
187 * @param dir Pin direction.
188 * @param input Connect or disconnect the input buffer.
189 * @param pull Pull configuration.
190 * @param drive Drive configuration.
191 * @param sense Pin sensing mechanism.
192 */
193 NRF_STATIC_INLINE void nrf_gpio_cfg(
194 uint32_t pin_number,
195 nrf_gpio_pin_dir_t dir,
196 nrf_gpio_pin_input_t input,
197 nrf_gpio_pin_pull_t pull,
198 nrf_gpio_pin_drive_t drive,
199 nrf_gpio_pin_sense_t sense);
200
201 /**
202 * @brief Function for configuring the given GPIO pin number as output, hiding inner details.
203 * This function can be used to configure a pin as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
204 *
205 * @note Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
206 *
207 * @param pin_number Specifies the pin number.
208 */
209 NRF_STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number);
210
211 /**
212 * @brief Function for configuring the given GPIO pin number as input, hiding inner details.
213 * This function can be used to configure a pin as simple input.
214 *
215 * @note Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
216 *
217 * @param pin_number Specifies the pin number.
218 * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
219 */
220 NRF_STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config);
221
222 /**
223 * @brief Function for resetting pin configuration to its default state.
224 *
225 * @param pin_number Specifies the pin number.
226 */
227 NRF_STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number);
228
229 /**
230 * @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected.
231 *
232 * @param pin_number Specifies the pin number.
233 *
234 */
235 NRF_STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number);
236
237 /**
238 * @brief Function for disconnecting input for the given GPIO.
239 *
240 * @param pin_number Specifies the pin number.
241 */
242 NRF_STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number);
243
244 /**
245 * @brief Function for configuring the given GPIO pin number as input, hiding inner details.
246 * This function can be used to configure pin range as simple input.
247 * Sense capability on the pin is configurable and input is connected to buffer so that the GPIO->IN register is readable.
248 *
249 * @param pin_number Specifies the pin number.
250 * @param pull_config State of the pin pull resistor (no pull, pulled down, or pulled high).
251 * @param sense_config Sense level of the pin (no sense, sense low, or sense high).
252 */
253 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number,
254 nrf_gpio_pin_pull_t pull_config,
255 nrf_gpio_pin_sense_t sense_config);
256
257 /**
258 * @brief Function for configuring sense level for the given GPIO.
259 *
260 * @param pin_number Specifies the pin number.
261 * @param sense_config Sense configuration.
262 */
263 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number,
264 nrf_gpio_pin_sense_t sense_config);
265
266 /**
267 * @brief Function for setting the direction for a GPIO pin.
268 *
269 * @param pin_number Specifies the pin number for which to set the direction.
270 * @param direction Specifies the direction.
271 */
272 NRF_STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction);
273
274 /**
275 * @brief Function for setting a GPIO pin.
276 *
277 * For this function to have any effect, the pin must be configured as an output.
278 *
279 * @param pin_number Specifies the pin number to be set.
280 */
281 NRF_STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number);
282
283 /**
284 * @brief Function for clearing a GPIO pin.
285 *
286 * For this function to have any effect, the pin must be configured as an output.
287 *
288 * @param pin_number Specifies the pin number to clear.
289 */
290 NRF_STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number);
291
292 /**
293 * @brief Function for toggling a GPIO pin.
294 *
295 * For this function to have any effect, the pin must be configured as an output.
296 *
297 * @param pin_number Specifies the pin number to toggle.
298 */
299 NRF_STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number);
300
301 /**
302 * @brief Function for writing a value to a GPIO pin.
303 *
304 * For this function to have any effect, the pin must be configured as an output.
305 *
306 * @param pin_number Specifies the pin number to write.
307 * @param value Specifies the value to be written to the pin.
308 * @arg 0 Clears the pin.
309 * @arg >=1 Sets the pin.
310 */
311 NRF_STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value);
312
313 /**
314 * @brief Function for reading the input level of a GPIO pin.
315 *
316 * If the value returned by this function is to be valid, the pin's input buffer must be connected.
317 *
318 * @param pin_number Specifies the pin number to read.
319 *
320 * @return 0 if the pin input level is low. Positive value if the pin is high.
321 */
322 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number);
323
324 /**
325 * @brief Function for reading the output level of a GPIO pin.
326 *
327 * @param pin_number Specifies the pin number to read.
328 *
329 * @return 0 if the pin output level is low. Positive value if pin output is high.
330 */
331 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number);
332
333 /**
334 * @brief Function for reading the sense configuration of a GPIO pin.
335 *
336 * @param pin_number Specifies the pin number to read.
337 *
338 * @return Sense configuration.
339 */
340 NRF_STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number);
341
342 /**
343 * @brief Function for reading the direction configuration of a GPIO pin.
344 *
345 * @param pin_number Specifies the pin number to read.
346 *
347 * @return Direction configuration.
348 */
349 NRF_STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number);
350
351 /**
352 * @brief Function for reading the status of GPIO pin input buffer.
353 *
354 * @param pin_number Pin number to be read.
355 *
356 * @retval Input buffer configuration.
357 */
358 NRF_STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number);
359
360 /**
361 * @brief Function for reading the pull configuration of a GPIO pin.
362 *
363 * @param pin_number Specifies the pin number to read.
364 *
365 * @retval Pull configuration.
366 */
367 NRF_STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number);
368
369 /**
370 * @brief Function for setting output direction on the selected pins on the given port.
371 *
372 * @param p_reg Pointer to the structure of registers of the peripheral.
373 * @param out_mask Mask specifying the pins to set as output.
374 */
375 NRF_STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask);
376
377 /**
378 * @brief Function for setting input direction on selected pins on a given port.
379 *
380 * @param p_reg Pointer to the structure of registers of the peripheral.
381 * @param in_mask Mask that specifies the pins to be set as input.
382 */
383 NRF_STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask);
384
385 /**
386 * @brief Function for writing the direction configuration of the GPIO pins in the given port.
387 *
388 * @param p_reg Pointer to the structure of registers of the peripheral.
389 * @param dir_mask Mask that specifies the direction of pins. Bit set means that the given pin is configured as output.
390 */
391 NRF_STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t dir_mask);
392
393 /**
394 * @brief Function for reading the direction configuration of a GPIO port.
395 *
396 * @param p_reg Pointer to the structure of registers of the peripheral.
397 *
398 * @return Pin configuration of the current direction settings. Bit set means that the given pin is configured as output.
399 */
400 NRF_STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg);
401
402 /**
403 * @brief Function for reading the input signals of the GPIO pins on the given port.
404 *
405 * @param p_reg Pointer to the peripheral registers structure.
406 *
407 * @return Port input values.
408 */
409 NRF_STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg);
410
411 /**
412 * @brief Function for reading the output signals of the GPIO pins on the given port.
413 *
414 * @param p_reg Pointer to the peripheral registers structure.
415 *
416 * @return Port output values.
417 */
418 NRF_STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg);
419
420 /**
421 * @brief Function for writing the GPIO pins output on a given port.
422 *
423 * @param p_reg Pointer to the structure of registers of the peripheral.
424 * @param value Output port mask.
425 */
426 NRF_STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value);
427
428 /**
429 * @brief Function for setting high level on selected the GPIO pins on the given port.
430 *
431 * @param p_reg Pointer to the structure of registers of the peripheral.
432 * @param set_mask Mask with pins to be set as logical high level.
433 */
434 NRF_STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask);
435
436 /**
437 * @brief Function for setting low level on selected the GPIO pins on the given port.
438 *
439 * @param p_reg Pointer to the structure of registers of the peripheral.
440 * @param clr_mask Mask with pins to be set as logical low level.
441 */
442 NRF_STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask);
443
444 /**
445 * @brief Function for reading pin state of multiple consecutive ports.
446 *
447 * @param start_port Index of the first port to read.
448 * @param length Number of ports to read.
449 * @param p_masks Pointer to output array where port states will be stored.
450 */
451 NRF_STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port,
452 uint32_t length,
453 uint32_t * p_masks);
454
455 #if defined(NRF_GPIO_LATCH_PRESENT)
456 /**
457 * @brief Function for reading latch state of multiple consecutive ports.
458 *
459 * @param start_port Index of the first port to read.
460 * @param length Number of ports to read.
461 * @param p_masks Pointer to output array where latch states will be stored.
462 */
463 NRF_STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port,
464 uint32_t length,
465 uint32_t * p_masks);
466
467 /**
468 * @brief Function for reading and immediate clearing latch state of multiple consecutive ports.
469 *
470 * @param start_port Index of the first port to read and clear.
471 * @param length Number of ports to read and clear.
472 * @param p_masks Pointer to output array where latch states will be stored.
473 */
474 NRF_STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port,
475 uint32_t length,
476 uint32_t * p_masks);
477
478 /**
479 * @brief Function for reading latch state of single pin.
480 *
481 * @param pin_number Pin number.
482 *
483 * @return 0 if latch is not set. Positive value otherwise.
484 */
485 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number);
486
487 /**
488 * @brief Function for clearing latch state of a single pin.
489 *
490 * @param pin_number Pin number.
491 */
492 NRF_STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number);
493 #endif // defined(NRF_GPIO_LATCH_PRESENT)
494
495 #if defined(GPIO_PIN_CNF_MCUSEL_Msk) || defined(__NRFX_DOXYGEN__)
496 /**
497 * @brief Function for selecting the MCU to control a GPIO pin.
498 *
499 * @param pin_number Pin_number.
500 * @param mcu MCU to control the pin.
501 */
502 NRF_STATIC_INLINE void nrf_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_mcusel_t mcu);
503 #endif
504
505 /**
506 * @brief Function for checking if provided pin is present on the MCU.
507 *
508 * @param[in] pin_number Number of the pin to be checked.
509 *
510 * @retval true Pin is present.
511 * @retval false Pin is not present.
512 */
513 NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number);
514
515 /**
516 * @brief Function for extracting port number and the relative pin number
517 * from the absolute pin number.
518 *
519 * @param[in,out] p_pin Pointer to the absolute pin number overridden by the pin number
520 * that is relative to the port.
521 *
522 * @return Port number.
523 */
524 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin);
525
526 #ifndef NRF_DECLARE_ONLY
527
528 /**
529 * @brief Function for extracting port and the relative pin number from the absolute pin number.
530 *
531 * @param[in,out] p_pin Pointer to the absolute pin number overridden by the pin number
532 * that is relative to the port.
533 *
534 * @return Pointer to port register set.
535 */
nrf_gpio_pin_port_decode(uint32_t * p_pin)536 NRF_STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin)
537 {
538 NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin));
539
540 switch (nrf_gpio_pin_port_number_extract(p_pin))
541 {
542 default:
543 NRFX_ASSERT(0);
544 break; // Supress fall through warnings
545 #if defined(P0_FEATURE_PINS_PRESENT)
546 case 0: return NRF_P0;
547 #endif
548 #if defined(P1_FEATURE_PINS_PRESENT)
549 case 1: return NRF_P1;
550 #endif
551 }
552 }
553
554
nrf_gpio_range_cfg_output(uint32_t pin_range_start,uint32_t pin_range_end)555 NRF_STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end)
556 {
557 for (; pin_range_start <= pin_range_end; pin_range_start++)
558 {
559 nrf_gpio_cfg_output(pin_range_start);
560 }
561 }
562
563
nrf_gpio_range_cfg_input(uint32_t pin_range_start,uint32_t pin_range_end,nrf_gpio_pin_pull_t pull_config)564 NRF_STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start,
565 uint32_t pin_range_end,
566 nrf_gpio_pin_pull_t pull_config)
567 {
568 for (; pin_range_start <= pin_range_end; pin_range_start++)
569 {
570 nrf_gpio_cfg_input(pin_range_start, pull_config);
571 }
572 }
573
574
nrf_gpio_cfg(uint32_t pin_number,nrf_gpio_pin_dir_t dir,nrf_gpio_pin_input_t input,nrf_gpio_pin_pull_t pull,nrf_gpio_pin_drive_t drive,nrf_gpio_pin_sense_t sense)575 NRF_STATIC_INLINE void nrf_gpio_cfg(
576 uint32_t pin_number,
577 nrf_gpio_pin_dir_t dir,
578 nrf_gpio_pin_input_t input,
579 nrf_gpio_pin_pull_t pull,
580 nrf_gpio_pin_drive_t drive,
581 nrf_gpio_pin_sense_t sense)
582 {
583 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
584
585 reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
586 | ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos)
587 | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)
588 | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos)
589 | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos);
590 }
591
592
nrf_gpio_cfg_output(uint32_t pin_number)593 NRF_STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number)
594 {
595 nrf_gpio_cfg(
596 pin_number,
597 NRF_GPIO_PIN_DIR_OUTPUT,
598 NRF_GPIO_PIN_INPUT_DISCONNECT,
599 NRF_GPIO_PIN_NOPULL,
600 NRF_GPIO_PIN_S0S1,
601 NRF_GPIO_PIN_NOSENSE);
602 }
603
604
nrf_gpio_cfg_input(uint32_t pin_number,nrf_gpio_pin_pull_t pull_config)605 NRF_STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config)
606 {
607 nrf_gpio_cfg(
608 pin_number,
609 NRF_GPIO_PIN_DIR_INPUT,
610 NRF_GPIO_PIN_INPUT_CONNECT,
611 pull_config,
612 NRF_GPIO_PIN_S0S1,
613 NRF_GPIO_PIN_NOSENSE);
614 }
615
616
nrf_gpio_cfg_default(uint32_t pin_number)617 NRF_STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number)
618 {
619 nrf_gpio_cfg(
620 pin_number,
621 NRF_GPIO_PIN_DIR_INPUT,
622 NRF_GPIO_PIN_INPUT_DISCONNECT,
623 NRF_GPIO_PIN_NOPULL,
624 NRF_GPIO_PIN_S0S1,
625 NRF_GPIO_PIN_NOSENSE);
626 }
627
628
nrf_gpio_cfg_watcher(uint32_t pin_number)629 NRF_STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number)
630 {
631 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
632 uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk;
633
634 reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos);
635 }
636
637
nrf_gpio_input_disconnect(uint32_t pin_number)638 NRF_STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number)
639 {
640 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
641 uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk;
642
643 reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos);
644 }
645
646
nrf_gpio_cfg_sense_input(uint32_t pin_number,nrf_gpio_pin_pull_t pull_config,nrf_gpio_pin_sense_t sense_config)647 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number,
648 nrf_gpio_pin_pull_t pull_config,
649 nrf_gpio_pin_sense_t sense_config)
650 {
651 nrf_gpio_cfg(
652 pin_number,
653 NRF_GPIO_PIN_DIR_INPUT,
654 NRF_GPIO_PIN_INPUT_CONNECT,
655 pull_config,
656 NRF_GPIO_PIN_S0S1,
657 sense_config);
658 }
659
660
nrf_gpio_cfg_sense_set(uint32_t pin_number,nrf_gpio_pin_sense_t sense_config)661 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number,
662 nrf_gpio_pin_sense_t sense_config)
663 {
664 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
665 uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
666
667 reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
668 }
669
670
nrf_gpio_pin_dir_set(uint32_t pin_number,nrf_gpio_pin_dir_t direction)671 NRF_STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction)
672 {
673 if (direction == NRF_GPIO_PIN_DIR_INPUT)
674 {
675 nrf_gpio_cfg(
676 pin_number,
677 NRF_GPIO_PIN_DIR_INPUT,
678 NRF_GPIO_PIN_INPUT_CONNECT,
679 NRF_GPIO_PIN_NOPULL,
680 NRF_GPIO_PIN_S0S1,
681 NRF_GPIO_PIN_NOSENSE);
682 }
683 else
684 {
685 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
686 reg->DIRSET = (1UL << pin_number);
687 }
688 }
689
690
nrf_gpio_pin_set(uint32_t pin_number)691 NRF_STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number)
692 {
693 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
694
695 nrf_gpio_port_out_set(reg, 1UL << pin_number);
696 }
697
698
nrf_gpio_pin_clear(uint32_t pin_number)699 NRF_STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number)
700 {
701 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
702
703 nrf_gpio_port_out_clear(reg, 1UL << pin_number);
704 }
705
706
nrf_gpio_pin_toggle(uint32_t pin_number)707 NRF_STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number)
708 {
709 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
710 uint32_t pins_state = reg->OUT;
711
712 reg->OUTSET = (~pins_state & (1UL << pin_number));
713 reg->OUTCLR = (pins_state & (1UL << pin_number));
714 }
715
716
nrf_gpio_pin_write(uint32_t pin_number,uint32_t value)717 NRF_STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value)
718 {
719 if (value == 0)
720 {
721 nrf_gpio_pin_clear(pin_number);
722 }
723 else
724 {
725 nrf_gpio_pin_set(pin_number);
726 }
727 }
728
729
nrf_gpio_pin_read(uint32_t pin_number)730 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number)
731 {
732 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
733
734 return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
735 }
736
737
nrf_gpio_pin_out_read(uint32_t pin_number)738 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number)
739 {
740 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
741
742 return ((nrf_gpio_port_out_read(reg) >> pin_number) & 1UL);
743 }
744
745
nrf_gpio_pin_sense_get(uint32_t pin_number)746 NRF_STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number)
747 {
748 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
749
750 return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
751 GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
752 }
753
754
nrf_gpio_pin_dir_get(uint32_t pin_number)755 NRF_STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number)
756 {
757 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
758
759 return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
760 GPIO_PIN_CNF_DIR_Msk) >> GPIO_PIN_CNF_DIR_Pos);
761 }
762
nrf_gpio_pin_input_get(uint32_t pin_number)763 NRF_STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number)
764 {
765 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
766
767 return (nrf_gpio_pin_input_t)((reg->PIN_CNF[pin_number] &
768 GPIO_PIN_CNF_INPUT_Msk) >> GPIO_PIN_CNF_INPUT_Pos);
769 }
770
nrf_gpio_pin_pull_get(uint32_t pin_number)771 NRF_STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number)
772 {
773 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
774
775 return (nrf_gpio_pin_pull_t)((reg->PIN_CNF[pin_number] &
776 GPIO_PIN_CNF_PULL_Msk) >> GPIO_PIN_CNF_PULL_Pos);
777 }
778
779
nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg,uint32_t out_mask)780 NRF_STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask)
781 {
782 p_reg->DIRSET = out_mask;
783 }
784
785
nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg,uint32_t in_mask)786 NRF_STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask)
787 {
788 p_reg->DIRCLR = in_mask;
789 }
790
791
nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg,uint32_t value)792 NRF_STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t value)
793 {
794 p_reg->DIR = value;
795 }
796
797
nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg)798 NRF_STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg)
799 {
800 return p_reg->DIR;
801 }
802
803
nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg)804 NRF_STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg)
805 {
806 return p_reg->IN;
807 }
808
809
nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg)810 NRF_STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg)
811 {
812 return p_reg->OUT;
813 }
814
815
nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg,uint32_t value)816 NRF_STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value)
817 {
818 p_reg->OUT = value;
819 }
820
821
nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg,uint32_t set_mask)822 NRF_STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask)
823 {
824 p_reg->OUTSET = set_mask;
825 }
826
827
nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg,uint32_t clr_mask)828 NRF_STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask)
829 {
830 p_reg->OUTCLR = clr_mask;
831 }
832
833
nrf_gpio_ports_read(uint32_t start_port,uint32_t length,uint32_t * p_masks)834 NRF_STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port,
835 uint32_t length,
836 uint32_t * p_masks)
837 {
838 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
839
840 NRFX_ASSERT(start_port + length <= GPIO_COUNT);
841 uint32_t i;
842
843 for (i = start_port; i < (start_port + length); i++)
844 {
845 *p_masks = nrf_gpio_port_in_read(gpio_regs[i]);
846 p_masks++;
847 }
848 }
849
850
851 #if defined(NRF_GPIO_LATCH_PRESENT)
nrf_gpio_latches_read(uint32_t start_port,uint32_t length,uint32_t * p_masks)852 NRF_STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port,
853 uint32_t length,
854 uint32_t * p_masks)
855 {
856 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
857 uint32_t i;
858
859 for (i = start_port; i < (start_port + length); i++)
860 {
861 *p_masks = gpio_regs[i]->LATCH;
862 p_masks++;
863 }
864 }
865
nrf_gpio_latches_read_and_clear(uint32_t start_port,uint32_t length,uint32_t * p_masks)866 NRF_STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port,
867 uint32_t length,
868 uint32_t * p_masks)
869 {
870 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
871 uint32_t i;
872
873 for (i = start_port; i < (start_port + length); i++)
874 {
875 *p_masks = gpio_regs[i]->LATCH;
876
877 // The LATCH register is cleared by writing a '1' to the bit that shall be cleared.
878 gpio_regs[i]->LATCH = *p_masks;
879
880 p_masks++;
881 }
882 }
883
nrf_gpio_pin_latch_get(uint32_t pin_number)884 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number)
885 {
886 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
887
888 return (reg->LATCH & (1 << pin_number)) ? 1 : 0;
889 }
890
891
nrf_gpio_pin_latch_clear(uint32_t pin_number)892 NRF_STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number)
893 {
894 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
895
896 reg->LATCH = (1 << pin_number);
897 }
898 #endif // defined(NRF_GPIO_LATCH_PRESENT)
899
900 #if defined(GPIO_PIN_CNF_MCUSEL_Msk)
nrf_gpio_pin_mcu_select(uint32_t pin_number,nrf_gpio_pin_mcusel_t mcu)901 NRF_STATIC_INLINE void nrf_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_mcusel_t mcu)
902 {
903 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
904 uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_MCUSEL_Msk;
905 reg->PIN_CNF[pin_number] = cnf | (mcu << GPIO_PIN_CNF_MCUSEL_Pos);
906 }
907 #endif
908
nrf_gpio_pin_present_check(uint32_t pin_number)909 NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number)
910 {
911 uint32_t port = pin_number >> 5;
912 uint32_t mask = 0;
913
914 switch (port)
915 {
916 #ifdef P0_FEATURE_PINS_PRESENT
917 case 0:
918 mask = P0_FEATURE_PINS_PRESENT;
919 #if defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833)
920 /* Allow use of the following additional GPIOs that are connected to LEDs and buttons
921 * on the nRF52833 DK:
922 * - P0.11 - Button 1
923 * - P0.12 - Button 2
924 * - P0.13 - LED 1
925 * - P0.24 - Button 3
926 * - P0.25 - Button 4
927 */
928 mask |= 0x03003800;
929 #endif // defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833)
930 break;
931 #endif
932 #ifdef P1_FEATURE_PINS_PRESENT
933 case 1:
934 mask = P1_FEATURE_PINS_PRESENT;
935 break;
936 #endif
937 }
938
939 pin_number &= 0x1F;
940
941 return (mask & (1UL << pin_number)) ? true : false;
942 }
943
nrf_gpio_pin_port_number_extract(uint32_t * p_pin)944 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
945 {
946 uint32_t pin_number = *p_pin;
947 *p_pin = pin_number & 0x1F;
948
949 return pin_number >> 5;
950 }
951
952 #endif // NRF_DECLARE_ONLY
953
954 /** @} */
955
956 #ifdef __cplusplus
957 }
958 #endif
959
960 #endif // NRF_GPIO_H__
961