1 /**
2 ******************************************************************************
3 * @file rtl8721dlp_clk.c
4 * @author
5 * @version V1.0.0
6 * @date 2016-05-17
7 * @brief This file provides firmware rom patch functions to manage clk
8 ******************************************************************************
9 * @attention
10 *
11 * This module is a confidential and proprietary property of RealTek and
12 * possession or use of this module requires written permission of RealTek.
13 *
14 * Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
15 ******************************************************************************
16 */
17
18 #include "ameba_soc.h"
19
20 /**
21 * @brief backup XTAL cap value to dummy register for DSLP mode with RTC trigger calib
22 * @param none
23 * @retval none
24 */
XTAL_CAP_BKP(void)25 VOID XTAL_CAP_BKP(void)
26 {
27 u32 sysreg;
28 u32 dumy_reg;
29
30 /*Get XTAL cap from 0x4800_0228[30:20]*/
31 sysreg = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_SYS_EFUSE_SYSCFG2);
32 sysreg = (sysreg >> 20) & 0x7FF;
33
34 /*backup XTAL cap to dummy reg 0x4800_00C8[10:0]*/
35 dumy_reg = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_XTAL_CTRL);
36 dumy_reg &= ~0x7FF;
37 dumy_reg |= sysreg;
38 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_XTAL_CTRL, dumy_reg);
39 }
40
SDM32K_Read(u32 Address)41 u32 SDM32K_Read(u32 Address)
42 {
43 u32 Temp = 0;
44
45 /* set indirect access address */
46 Temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_AON_CK32KGEN_AD);
47 Temp &= (~BIT_LS_MASK_SDM_ADDR);
48 Temp |= Address;
49 HAL_WRITE32(SYSTEM_CTRL_BASE, REG_AON_CK32KGEN_AD, Temp);
50
51 /* get indirect access val */
52 Temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_AON_CK32KGEN_RWD);
53
54 return Temp;
55 }
56
SDM32K_Write(u32 Address,u32 Val)57 void SDM32K_Write(u32 Address, u32 Val)
58 {
59 u32 Temp = 0;
60
61 /* set indirect access address */
62 Temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_AON_CK32KGEN_AD);
63 Temp &= (~BIT_LS_MASK_SDM_ADDR);
64 Temp |= Address;
65 HAL_WRITE32(SYSTEM_CTRL_BASE, REG_AON_CK32KGEN_AD, Temp);
66
67 /* set indirect access val */
68 HAL_WRITE32(SYSTEM_CTRL_BASE, REG_AON_CK32KGEN_RWD, Val);
69 }
70
71 /**
72 * @brief 32K clock Enable,
73 * @param SDM32KCalType: can be one of the following values:
74 * @arg SDM32K_ONE_CAL calibration once when sdm power on
75 * @arg SDM32K_AUTO_CAL open auto calibration
76 * @arg SDM32K_ALWAYS_CAL open always calibration
77 * @note NA
78 */
SDM32K_Enable(u32 SDM32KCalType)79 void SDM32K_Enable(u32 SDM32KCalType)
80 {
81 u32 Temp = 0;
82
83 /* SDM function clock enable & SDM function enable */
84 RCC_PeriphClockCmd(APBPeriph_CK32KGEN, APBPeriph_CK32KGEN_CLOCK, ENABLE);
85
86 Temp = SDM32K_Read(REG_SDM_CTRL0);
87
88 /*clear SDM32K auto/always calibration*/
89 Temp &= ~(BIT_AON_SDM_AUTO_CAL_EN | BIT_AON_SDM_ALWAYS_CAL_EN);
90
91 /*default enable once calibration*/
92 Temp |= (BIT_AON_SDM_FUNC_EN | BIT_AON_SDM_ONE_CAL_EN);
93
94 if (SDM32KCalType == SDM32K_ONE_CAL) {
95 //bit[31]: calibration one when first enable SDM; bit[30]: SDM enable
96 SDM32K_Write(REG_SDM_CTRL0, Temp);
97 } else if (SDM32KCalType == SDM32K_AUTO_CAL) {
98 //write threshold
99 SDM32K_Write(AUTO_CAL_MAX_ERROR, 0x80);
100
101 // bit[16]:auto calibration enable
102 Temp |= BIT_AON_SDM_AUTO_CAL_EN;
103 SDM32K_Write(REG_SDM_CTRL0, Temp);
104 } else if (SDM32KCalType == SDM32K_ALWAYS_CAL) {
105 //bit[18]: always calibration enable
106 Temp |= BIT_AON_SDM_ALWAYS_CAL_EN;
107 SDM32K_Write(REG_SDM_CTRL0, Temp);
108 }
109 }
110
111 /**
112 * @brief 32K clock RTC auto calibration Enable,
113 * @param RTCCalibration: can be one of the following values:
114 * @arg TRUE open RTC auto-calibration
115 * @arg FALSE not open RTC auto-calibration
116 * @note NA
117 */
SDM32K_RTCCalEnable(u32 RTCCalibration)118 void SDM32K_RTCCalEnable(u32 RTCCalibration)
119 {
120 u32 Temp = 0;
121
122 Temp = SDM32K_Read(REG_SDM_CTRL0);
123 Temp &= ~ BIT_AON_SDM_RTC_CAL_EN;
124
125 if (!RTCCalibration) {
126 SDM32K_Write(REG_SDM_CTRL0, Temp);
127 } else {
128 //bit[17]: RTC auto calibration enable
129 Temp |= BIT_AON_SDM_RTC_CAL_EN;
130 SDM32K_Write(REG_SDM_CTRL0, Temp);
131
132 /*backup XTAL cap to dummy register*/
133 XTAL_CAP_BKP();
134 }
135 }
136
137 /* setbit/clearbit is: BIT0~BIT5 defined in BIT_AON_MASK_OSC32K_RCAL_5_0 */
OSC131_R_Set(u32 setbit,u32 clearbit)138 VOID OSC131_R_Set(u32 setbit, u32 clearbit)
139 {
140 u32 temp = 0;
141
142 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC32K_CTRL);
143
144 if (setbit) {
145 temp |= (setbit << BIT_AON_SHIFT_OSC32K_RCAL_5_0);
146 }
147
148 if (clearbit) {
149 temp &= ~(clearbit << BIT_AON_SHIFT_OSC32K_RCAL_5_0);
150 }
151
152 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_OSC32K_CTRL, temp);
153
154 /* It takes 1ms to stable */
155 DelayMs(1);
156 }
157
158 /**
159 * @brief 131.072K calibration
160 * @param max_delta: target_40m_counter-calibration_result, default 10
161 * @note Here XTAL clock is used to count N cycles of calibration clock, the total used XTAL clock cycles can be read by this register, N= 8
162 */
OSC131K_Calibration(u32 ppm_limit)163 u32 OSC131K_Calibration(u32 ppm_limit)
164 {
165 u32 temp = 0;
166 u32 cal_n = 0;
167 u32 rsel_bit_index = 0;
168 u32 delta = 0;
169 u32 min_delta = 0xFFFFFFFF;
170 u32 cur_ppm = 0;
171 u32 min_delta_r = 0;
172 u32 target_40m_counter = 2441; //8*40000000/131072
173 u32 clearbit = 0;
174
175 /* Step1: Enable LS_VENDOR_REG clock/reset: 0x4800_020C[0] = 0x1, 0x4800_0214[0] = 0x1 */
176 RCC_PeriphClockCmd(APBPeriph_VENDOR_REG, APBPeriph_VENDOR_REG_CLOCK, ENABLE);
177
178 /* Step2: Power on OSC131K: 0x4800_002C[0]= 0x1 */
179 /* BOOT_ROM_OSC131_Enable have done this in rom, so here we check it */
180 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC32K_CTRL);
181 temp &= ~(BIT_AON_MASK_OSC32K_RCAL_5_0 << BIT_AON_SHIFT_OSC32K_RCAL_5_0); // reset R, or second calibration may fail in some chip
182 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_OSC32K_CTRL, temp);
183 if ((temp & BIT_AON_OSC32K_EN) == 0) {
184 temp |= BIT_AON_OSC32K_EN;
185 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_OSC32K_CTRL, temp);
186 }
187 while (1) {
188 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSTEM_CFG1);
189 if (temp & BIT_OSC128K_CLKRDY) {
190 break;
191 }
192 }
193
194 /* Step2.1: Set OSC calibration parameter: 0x4800_2840[25:24], select 131K as calibration source */
195 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC_CAL);
196 temp &= ~(BIT_MASK_CAL_CLK_SEL << BIT_SHIFT_CAL_CLK_SEL);
197 temp |= (0x03 << BIT_SHIFT_CAL_CLK_SEL); /* select 131K */
198 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_OSC_CAL, temp);
199
200 /* Step3: Enter the following loop: each loop decides one bit of 4800002c[13:8]-RCAL, i.e. the first loop decides RCAL[5], the second loop decides RCAL[4] ��, suppose the current loop is N (N=1..6) */
201 /* Loop Step1: Set RCAL[6-N] = 0x1 */
202 /* Loop Step2: Wait some time for clock stable (this wait time decide by SW) */
203 /* Loop Step3: Enable Calibration: 0x4800_2840 = 0x8200_0000 */
204 /* Loop Step2: Poll 0x4800_2840[31] = 0x0, read calibration result: 0x4800_2840[15:0] */
205 /* Loop Step3: */
206 /* If(frequency is in the allowed deviation range) */
207 /* Calibration will end successfully */
208 /* Else if (frequency counter > target frequency counter) */ /* (frequency > target frequency) */
209 /* RCAL[6-N] = 0x0 */
210 /* Else */
211 /* RCAL[6-N] keep 1. */
212 /* If (N=6) */
213 /* Calibration will end, and if the last loop frequency is OK , then calibration is OK, otherwise calibration is fail */
214 /* Else */
215 /* Go to Loop step1 */
216 for (cal_n = 1; cal_n <= 6; cal_n++) {
217 rsel_bit_index = 6 - cal_n;
218 OSC131_R_Set(BIT(rsel_bit_index), clearbit);
219
220 /* start calibration */
221 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC_CAL);
222 temp |= BIT_CAL_START;
223 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_OSC_CAL, temp);
224
225 /* poll calibration complete */
226 while (1) {
227 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC_CAL);
228 if ((temp & BIT_CAL_START) == 0) {
229 break;
230 }
231 }
232
233 /* read calibration result */
234 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC_CAL) >> BIT_SHIFT_CAL_RPT;
235 temp = temp & BIT_MASK_CAL_RPT;
236
237 if (temp < target_40m_counter) {
238 delta = target_40m_counter - temp;
239 clearbit = BIT(rsel_bit_index);
240 } else {
241 delta = temp - target_40m_counter;
242 clearbit = 0;
243 }
244
245 if (delta < min_delta) {
246 min_delta = delta;
247 min_delta_r = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC32K_CTRL);
248 min_delta_r &= (BIT_AON_MASK_OSC32K_RCAL_5_0 << BIT_AON_SHIFT_OSC32K_RCAL_5_0);
249 }
250
251 //DBG_8195A("[CAL131K]:cal_n %d delta:%d \n", cal_n, delta);
252 }
253
254 /* the last one is not the best one */
255 if (delta > min_delta) {
256 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC32K_CTRL);
257 temp &= ~(BIT_AON_MASK_OSC32K_RCAL_5_0 << BIT_AON_SHIFT_OSC32K_RCAL_5_0);
258 temp |= min_delta_r;
259 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_OSC32K_CTRL, temp);
260
261 /* It takes 1ms to stable */
262 DelayMs(1);
263
264 /* start calibration */
265 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC_CAL);
266 temp |= BIT_CAL_START;
267 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_OSC_CAL, temp);
268
269 /* poll calibration complete */
270 while (1) {
271 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC_CAL);
272 if ((temp & BIT_CAL_START) == 0) {
273 break;
274 }
275 }
276
277 /* read calibration result */
278 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC_CAL) >> BIT_SHIFT_CAL_RPT;
279 temp = temp & BIT_MASK_CAL_RPT;
280
281 if (temp < target_40m_counter) {
282 delta = target_40m_counter - temp;
283 } else {
284 delta = temp - target_40m_counter;
285 }
286 }
287
288 cur_ppm = delta*1000000/target_40m_counter;
289 DBG_8195A("[CAL131K]: delta:%d target:%d PPM: %d PPM_Limit:%d \n", delta, target_40m_counter, cur_ppm, ppm_limit);
290
291 if (cur_ppm >= ppm_limit) {
292 DBG_8195A("[CAL131K]: PPM: %d PPM_Limit:%d \n", cur_ppm, ppm_limit);
293 assert_param(0);
294 }
295
296 return TRUE;
297 }
298
299 /* bitnum is: 0~7 defined in BIT_MASK_OSC2M_R_SEL */
OSC2M_R_Set(u32 setbit,u32 clearbit)300 VOID OSC2M_R_Set(u32 setbit, u32 clearbit)
301 {
302 u32 temp = 0;
303
304 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_OSC2M_CTRL);
305
306 if (setbit)
307 temp |= (setbit << BIT_SHIFT_OSC2M_R_SEL);
308
309 if (clearbit)
310 temp &= ~(clearbit << BIT_SHIFT_OSC2M_R_SEL);
311
312 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_OSC2M_CTRL, temp);
313 }
314
315 /**
316 * @brief OSC2M calibration
317 * @param cal_osc_cycles: can be one of the following values:
318 * @arg OSC2M_CAL_CYC_16
319 * @arg OSC2M_CAL_CYC_32
320 * @arg OSC2M_CAL_CYC_64
321 * @arg OSC2M_CAL_CYC_128
322 * @param max_delta: target_40m_counter-calibration_result, default 10
323 * @note NA
324 */
OSC2M_Calibration(u32 cal_osc_cycles,u32 ppm_limit)325 u32 OSC2M_Calibration(u32 cal_osc_cycles, u32 ppm_limit)
326 {
327 u32 temp = 0;
328 u32 cal_n = 0;
329 u32 rsel_bit_index = 0;
330 u32 delta = 0;
331 u32 min_delta = 0xFFFFFFFF;
332 u32 cur_ppm = 0;
333 u32 min_delta_r = 0;
334 u32 target_40m_counter = (16 << cal_osc_cycles) * (40/2); //2560
335 u32 clearbit = 0;
336
337 /* Step1: Enable LS_VENDOR_REG clock/reset: 0x4800_020C[0] = 0x1, 0x4800_0214[0] = 0x1 */
338 RCC_PeriphClockCmd(APBPeriph_VENDOR_REG, APBPeriph_VENDOR_REG_CLOCK, ENABLE);
339
340 /* Step2: Power on OSC2M: 0x4800_0298[0]= 0x1 */
341 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_OSC2M_CTRL);
342 temp |= BIT_OSC2M_EN;
343 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_OSC2M_CTRL, temp);
344
345 /* Step3: Set OSC2M calibration parameter: 0x4800_2844[13:12]/ 0x4800_2844[11:8] */
346 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC2M_CAL);
347 temp |= (0x03 << BIT_SHIFT_OSC2M_CAL_CYC_SEL); /* "Target cycles of OSC2M2'b00: 16 2'b01: 322'b10: 642'b11: 128" */
348 temp |= (0xF << BIT_SHIFT_OSC2M_CAL_DLY); /* HW will wait (BIT_OSC2M_CAL_DLY+1) OSC2M cycles before start to count N cycles of OSC2M clock by XTAL */
349 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_OSC2M_CAL, temp);
350
351 /* Step4: Enable OSC2M calibration function: 0x4800_2844[1]= 0x1 */
352 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC2M_CAL);
353 temp |= BIT_OSC2M_CAL_FEN;
354 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_OSC2M_CAL, temp);
355
356 /* clear 2m calibration parameter first */
357 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_OSC2M_CTRL);
358 temp &= ~(BIT_MASK_OSC2M_R_SEL << BIT_SHIFT_OSC2M_R_SEL);
359 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_OSC2M_CTRL, temp);
360
361 /* Step5: Enter the following loop: suppose the current loop is N (N=1..8) */
362 /* Loop Step1: Set OSC2M_R_SEL[8-N] = 0x1 */
363 /* Loop Step2: Enable Calibration: 0x4800_2844 [0] = 0x1 */
364 /* Loop Step2: Poll 0x4800_2844[0] = 0x0, read calibration result: 0x4800_2844[31:16] */
365 /* Loop Step3: */
366 /* If(frequency is in the allowed deviation range) */
367 /* Calibration will end successfully */
368 /* Else if (frequency counter > target frequency counter) */ /* (frequency < target frequency) */
369 /* OSC2M_R_SEL[8-N] = 0x0 */
370 /* Else */
371 /* OSC2M_R_SEL[8-N] keep 1. */
372 for (cal_n = 1; cal_n <= 8; cal_n++) {
373 rsel_bit_index = 8 - cal_n;
374 OSC2M_R_Set(BIT(rsel_bit_index), clearbit);
375
376 /* start calibration */
377 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC2M_CAL);
378 temp |= BIT_OSC2M_CAL_START;
379 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_OSC2M_CAL, temp);
380
381 /* poll calibration complete */
382 while (1) {
383 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC2M_CAL);
384 if ((temp & BIT_OSC2M_CAL_START) == 0) {
385 break;
386 }
387 }
388
389 /* read calibration result */
390 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC2M_CAL) >> BIT_SHIFT_OSC2M_CAL_RPT;
391 //DBG_8195A("OSC2M_Calibration:cal_n %d result:%d target:%d delta:%d\n", cal_n, temp, target_40m_counter, delta);
392
393 if (temp <= target_40m_counter) {
394 delta = target_40m_counter - temp;
395 clearbit = 0;
396 } else {
397 delta = temp - target_40m_counter;
398 clearbit = BIT(rsel_bit_index);
399 }
400
401 if (delta < min_delta) {
402 min_delta = delta;
403 min_delta_r = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_OSC2M_CTRL);
404 min_delta_r &= (BIT_MASK_OSC2M_R_SEL << BIT_SHIFT_OSC2M_R_SEL);
405 }
406 //DBG_8195A("[CAL2M]:cal_n %d delta:%d \n", cal_n, delta);
407 }
408
409 /* the last one is not the best one */
410 if (delta > min_delta) {
411 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_OSC2M_CTRL);
412 temp &= ~(BIT_MASK_OSC2M_R_SEL << BIT_SHIFT_OSC2M_R_SEL);
413 temp |= min_delta_r;
414 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_OSC2M_CTRL, temp);
415
416 /* start calibration */
417 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC2M_CAL);
418 temp |= BIT_OSC2M_CAL_START;
419 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_OSC2M_CAL, temp);
420
421 /* poll calibration complete */
422 while (1) {
423 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC2M_CAL);
424 if ((temp & BIT_OSC2M_CAL_START) == 0) {
425 break;
426 }
427 }
428
429 /* read calibration result */
430 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_OSC2M_CAL) >> BIT_SHIFT_OSC2M_CAL_RPT;
431 //DBG_8195A("OSC2M_Calibration:cal_n %d result:%d target:%d delta:%d\n", cal_n, temp, target_40m_counter, delta);
432
433 if (temp < target_40m_counter) {
434 delta = target_40m_counter - temp;
435 } else {
436 delta = temp - target_40m_counter;
437 }
438 }
439
440 cur_ppm = delta*1000000/target_40m_counter;
441 DBG_8195A("[CAL2M]: delta:%d target:%d PPM: %d PPM_Limit:%d \n", delta, target_40m_counter, cur_ppm, ppm_limit);
442
443 if (cur_ppm >= ppm_limit) {
444 DBG_8195A("[CAL2M]: PPM: %d PPM_Limit:%d \n", cur_ppm, ppm_limit);
445 assert_param(0);
446 }
447
448 return TRUE;
449 }
450
451 /**
452 * @brief Configure NCO 2M Clock
453 * @param clk_out_Hz: the NCO output clock(unit: Hz).
454 * @note [14:0]: expected frequency of nco output clk, unit is 1KHz
455 * @note [16]: function enable
456 * @retval none
457 */
NCO2M_Init(u32 clk_out_Hz)458 void NCO2M_Init(u32 clk_out_Hz)
459 {
460 u32 Temp;
461 u32 clk_out = clk_out_Hz / 1000;
462
463 /* Check the parameters */
464 assert_param((clk_out > 0 && clk_out <= 0x7FFF));
465
466 /*disable the NCO clock and configure NCO output clock*/
467 Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_UART_XTAL_DIV_CTRL);
468
469 Temp &= (~(BIT_LSYS_UART_XTAL_DIV_EN |BIT_LSYS_MASK_UART_XTAL_DIV_FREQ));
470
471 Temp |= clk_out;
472
473 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_UART_XTAL_DIV_CTRL, Temp);
474 }
475
476 /**
477 * @brief enable or disable the NCO2M Clock
478 * @param NewState: the new state of the NCO 2M clock.
479 * This parameter can be: ENABLE or DISABLE.
480 * @retval none
481 */
NCO2M_Cmd(u32 NewState)482 void NCO2M_Cmd(u32 NewState)
483 {
484 u32 Temp;
485
486 Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_UART_XTAL_DIV_CTRL);
487
488 if(NewState != DISABLE) {
489 /*enable XTAL division circuit for UART*/
490 Temp |= BIT_LSYS_UART_XTAL_DIV_EN;
491 } else {
492 /*disable XTAL division circuit for UART*/
493 Temp &= (~BIT_LSYS_UART_XTAL_DIV_EN);
494 }
495
496 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_UART_XTAL_DIV_CTRL, Temp);
497 }
498
499 /**
500 * @brief OSC4M Init
501 * @param NA
502 * @note NA
503 */
OSC4M_Init(void)504 void OSC4M_Init(void)
505 {
506 u32 temp = 0;
507
508 /* Enable OSC4M wake up */
509 temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_OSC4M_CTRL);
510 temp |= BIT_OSC4M_WAKE_EN;
511 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_OSC4M_CTRL, temp);
512 }
513 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
514