1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3  * Copyright (c) 2014, STMicroelectronics International N.V.
4  */
5 #ifndef TZ_SSVCE_DEF_H
6 #define TZ_SSVCE_DEF_H
7 
8 #include <stdint.h>
9 #include <util.h>
10 
11 /*
12  * ARMv7 Secure Services library
13  */
14 
15 #define CPSR_OFFSET                U(0x00)
16 #define STACK_INT_USAGE            U(0x04)
17 
18 /*
19  * tee service IDs (TODO: align with the service ID list).
20  * Set by NSec in R4 before SMC to request a TEE service.
21  */
22 #define SSAPI_RET_FROM_INT_SERV             U(4)
23 #define SSAPI_RET_FROM_RPC_SERV             U(5)
24 
25 /*
26  * TEE monitor: status returned by the routine that checks the entry
27  * reason (valid Service ID / secure context).
28  */
29 #define SEC_INVALID_ENTRY                  U(0)
30 #define SEC_PRE_INIT_ENTRY                 U(1)
31 #define SEC_RET_FROM_INT_ENTRY             U(2)
32 #define SEC_RET_FROM_RPC_ENTRY             U(3)
33 #define SEC_NORMAL_ENTRY                   U(4)
34 
35 /*
36  * teecore exit reason.
37  * Set by Secure in R4 before SMC to request a switch to NSec.
38  */
39 #define SEC_EXIT_NORMAL                    U(1)
40 #define SEC_EXIT_START_EXT_CODE            U(2)
41 #define SEC_EXIT_INT                       U(3)
42 #define SEC_EXIT_RPC_CALL                  U(4)
43 #define SEC_EXIT_FIRST                     U(5)
44 #define SEC_EXIT_DEEP_SLEEP                U(6)
45 
46 /* misc */
47 
48 #define  SEC_UNDEF_STACK_OFFSET             U(4)
49 #define  SEC_ABORT_STACK_OFFSET             U(12)
50 
51 #define  SEC_ENTRY_STATUS_NOK             U(0)
52 #define  SEC_ENTRY_STATUS_OK              U(1)
53 
54 /*
55  * Outer cache iomem
56  */
57 #define PL310_LINE_SIZE		U(32)
58 #define PL310_8_WAYS		U(8)
59 
60 #define PL310_CACHE_ID		0x0
61 /* reg1 */
62 #define PL310_CTRL		U(0x100)
63 #define PL310_AUX_CTRL		U(0x104)
64 #define PL310_TAG_RAM_CTRL	U(0x108)
65 #define PL310_DATA_RAM_CTRL	U(0x10C)
66 /* reg7 */
67 #define PL310_SYNC		U(0x730)
68 #define PL310_INV_BY_WAY	U(0x77C)
69 #define PL310_CLEAN_BY_WAY	U(0x7BC)
70 #define PL310_FLUSH_BY_WAY	U(0x7FC)
71 #define PL310_INV_BY_PA		U(0x770)
72 #define PL310_CLEAN_BY_PA	U(0x7B0)
73 #define PL310_FLUSH_BY_PA	U(0x7F0)
74 #define PL310_FLUSH_BY_INDEXWAY	U(0x7F8)
75 /* reg9 */
76 #define PL310_DCACHE_LOCKDOWN_BASE U(0x900)
77 #define PL310_ICACHE_LOCKDOWN_BASE U(0x904)
78 /* reg12 */
79 #define PL310_ADDR_FILT_START	U(0xC00)
80 #define PL310_ADDR_FILT_END	U(0xC04)
81 /* reg15 */
82 #define PL310_DEBUG_CTRL	U(0xF40)
83 #define PL310_PREFETCH_CTRL	U(0xF60)
84 #define PL310_POWER_CTRL	U(0xF80)
85 
86 #define PL310_CTRL_ENABLE_BIT	BIT32(0)
87 #define PL310_AUX_16WAY_BIT	BIT32(16)
88 
89 #define PL310_CACHE_ID_PART_MASK	GENMASK_32(9, 6)
90 #define PL310_CACHE_ID_PART_L310	0xC0
91 #define PL310_CACHE_ID_RTL_MASK		GENMASK_32(5, 0)
92 #define PL310_CACHE_ID_RTL_R3P2		0x8
93 
94 /*
95  * SCU iomem
96  */
97 #define SCU_CTRL	U(0x00)
98 #define SCU_CONFIG	U(0x04)
99 #define SCU_POWER	U(0x08)
100 #define SCU_INV_SEC	U(0x0C)
101 #define SCU_FILT_SA	U(0x40)
102 #define SCU_FILT_EA	U(0x44)
103 #define SCU_SAC		U(0x50)
104 #define SCU_NSAC	U(0x54)
105 #define SCU_SIZE	U(0x58)
106 #define SCU_ERRATA744369 U(0x30)
107 
108 #define SCU_ACCESS_CONTROL_CPU0		BIT32(0)
109 #define SCU_ACCESS_CONTROL_CPU1		BIT32(1)
110 #define SCU_ACCESS_CONTROL_CPU2		BIT32(2)
111 #define SCU_ACCESS_CONTROL_CPU3		BIT32(3)
112 #define SCU_NSAC_SCU_SHIFT		U(0)
113 #define SCU_NSAC_PTIMER_SHIFT		U(4)
114 #define SCU_NSAC_GTIMER_SHIFT		U(8)
115 
116 /*
117  * GIC iomem
118  */
119 #define GIC_DIST_ISR0	U(0x080)
120 #define GIC_DIST_ISR1	U(0x084)
121 #define GIC_DIST_IPRIO	U(0x400)
122 
123 /*
124  * CPU iomem
125  */
126 #define CORE_ICC_ICCPMR	U(0x0004)
127 
128 #endif /* TZ_SSVCE_DEF_H */
129