1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #include <arch.h> 12 #include <common/interrupt_props.h> 13 #include <common/tbbr/tbbr_img_def.h> 14 #include <plat/common/common_def.h> 15 16 /* Platform Type */ 17 #define PLAT_SOCFPGA_STRATIX10 1 18 #define PLAT_SOCFPGA_AGILEX 2 19 #define PLAT_SOCFPGA_N5X 3 20 #define PLAT_SOCFPGA_EMULATOR 0 21 22 /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ 23 #define PLAT_CPU_RELEASE_ADDR 0xffd12210 24 25 /* 26 * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset 27 * is done and HPS should trigger warm reset via RMR_EL3. 28 */ 29 #define L2_RESET_DONE_REG 0xFFD12218 30 31 /* Magic word to indicate L2 reset is completed */ 32 #define L2_RESET_DONE_STATUS 0x1228E5E7 33 34 /* Define next boot image name and offset */ 35 #define PLAT_NS_IMAGE_OFFSET 0x10000000 36 #define PLAT_HANDOFF_OFFSET 0xFFE3F000 37 38 /******************************************************************************* 39 * Platform binary types for linking 40 ******************************************************************************/ 41 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 42 #define PLATFORM_LINKER_ARCH aarch64 43 44 /* SoCFPGA supports up to 124GB RAM */ 45 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 46 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 47 48 49 /******************************************************************************* 50 * Generic platform constants 51 ******************************************************************************/ 52 #define PLAT_PRIMARY_CPU 0 53 #define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 54 55 /* Size of cacheable stacks */ 56 #define PLATFORM_STACK_SIZE 0x2000 57 58 /* PSCI related constant */ 59 #define PLAT_NUM_POWER_DOMAINS 5 60 #define PLAT_MAX_PWR_LVL 1 61 #define PLAT_MAX_RET_STATE 1 62 #define PLAT_MAX_OFF_STATE 2 63 #define PLATFORM_SYSTEM_COUNT U(1) 64 #define PLATFORM_CLUSTER_COUNT U(1) 65 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 66 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 67 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 68 PLATFORM_CLUSTER0_CORE_COUNT) 69 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 70 71 /* Interrupt related constant */ 72 73 #define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29 74 75 #define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8 76 #define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9 77 #define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10 78 #define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11 79 #define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12 80 #define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13 81 #define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14 82 #define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15 83 84 #define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 85 #define TSP_SEC_MEM_BASE BL32_BASE 86 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 87 /******************************************************************************* 88 * Platform memory map related constants 89 ******************************************************************************/ 90 #define DRAM_BASE (0x0) 91 #define DRAM_SIZE (0x80000000) 92 93 #define OCRAM_BASE (0xFFE00000) 94 #define OCRAM_SIZE (0x00040000) 95 96 #define MEM64_BASE (0x0100000000) 97 #define MEM64_SIZE (0x1F00000000) 98 99 #define DEVICE1_BASE (0x80000000) 100 #define DEVICE1_SIZE (0x60000000) 101 102 #define DEVICE2_BASE (0xF7000000) 103 #define DEVICE2_SIZE (0x08E00000) 104 105 #define DEVICE3_BASE (0xFFFC0000) 106 #define DEVICE3_SIZE (0x00008000) 107 108 #define DEVICE4_BASE (0x2000000000) 109 #define DEVICE4_SIZE (0x0100000000) 110 111 /******************************************************************************* 112 * BL31 specific defines. 113 ******************************************************************************/ 114 /* 115 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 116 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 117 * little space for growth. 118 */ 119 120 121 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 122 123 #define BL1_RO_BASE (0xffe00000) 124 #define BL1_RO_LIMIT (0xffe0f000) 125 #define BL1_RW_BASE (0xffe10000) 126 #define BL1_RW_LIMIT (0xffe1ffff) 127 #define BL1_RW_SIZE (0x14000) 128 129 #define BL2_BASE (0xffe00000) 130 #define BL2_LIMIT (0xffe1b000) 131 132 #define BL31_BASE (0x1000) 133 #define BL31_LIMIT (0x81000) 134 135 #define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET 136 137 #define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16) 138 #define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8) 139 140 #define PLAT_SEC_WARM_ENTRY 0 141 142 /******************************************************************************* 143 * Platform specific page table and MMU setup constants 144 ******************************************************************************/ 145 #define MAX_XLAT_TABLES 8 146 #define MAX_MMAP_REGIONS 16 147 148 /******************************************************************************* 149 * Declarations and constants to access the mailboxes safely. Each mailbox is 150 * aligned on the biggest cache line size in the platform. This is known only 151 * to the platform as it might have a combination of integrated and external 152 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 153 * line at any cache level. They could belong to different cpus/clusters & 154 * get written while being protected by different locks causing corruption of 155 * a valid mailbox address. 156 ******************************************************************************/ 157 #define CACHE_WRITEBACK_SHIFT 6 158 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 159 160 #define PLAT_GIC_BASE (0xFFFC0000) 161 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) 162 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) 163 #define PLAT_GICR_BASE 0 164 165 /******************************************************************************* 166 * UART related constants 167 ******************************************************************************/ 168 #define PLAT_UART0_BASE (0xFFC02000) 169 #define PLAT_UART1_BASE (0xFFC02100) 170 171 #define CRASH_CONSOLE_BASE PLAT_UART0_BASE 172 #define PLAT_INTEL_UART_BASE PLAT_UART0_BASE 173 174 #if PLAT_SOCFPGA_EMULATOR 175 #define PLAT_BAUDRATE (4800) 176 #define PLAT_UART_CLOCK (76800) 177 #else 178 #define PLAT_BAUDRATE (115200) 179 #define PLAT_UART_CLOCK (100000000) 180 #endif 181 182 /******************************************************************************* 183 * PHY related constants 184 ******************************************************************************/ 185 186 #define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII 187 #define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII 188 #define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII 189 190 /******************************************************************************* 191 * System counter frequency related constants 192 ******************************************************************************/ 193 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) 194 #define PLAT_SYS_COUNTER_CONVERT_TO_MHZ (1000000) 195 196 #define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE 197 #define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE 198 199 /* 200 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 201 * terminology. On a GICv2 system or mode, the lists will be merged and treated 202 * as Group 0 interrupts. 203 */ 204 #define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \ 205 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \ 206 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 207 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \ 208 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 209 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \ 210 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 211 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \ 212 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 213 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \ 214 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 215 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \ 216 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 217 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \ 218 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 219 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \ 220 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 221 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \ 222 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE) 223 224 #define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp) 225 226 #define MAX_IO_HANDLES 4 227 #define MAX_IO_DEVICES 4 228 #define MAX_IO_BLOCK_DEVICES 2 229 230 #ifndef __ASSEMBLER__ 231 struct socfpga_bl31_params { 232 param_header_t h; 233 image_info_t *bl31_image_info; 234 entry_point_info_t *bl32_ep_info; 235 image_info_t *bl32_image_info; 236 entry_point_info_t *bl33_ep_info; 237 image_info_t *bl33_image_info; 238 }; 239 #endif 240 241 #endif /* PLATFORM_DEF_H */ 242 243