1 /*
2  * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef PLATFORM_DEF_H
8 #define PLATFORM_DEF_H
9 
10 #include <lib/utils_def.h>
11 #include <plat/common/common_def.h>
12 
13 /* CPU topology */
14 #define PLAT_MAX_CORES_PER_CLUSTER	U(2)
15 #define PLAT_CLUSTER_COUNT		U(12)
16 #define PLATFORM_CORE_COUNT		(PLAT_CLUSTER_COUNT *	\
17 					 PLAT_MAX_CORES_PER_CLUSTER)
18 
19 /* Macros to read the SQ power domain state */
20 #define SQ_PWR_LVL0		MPIDR_AFFLVL0
21 #define SQ_PWR_LVL1		MPIDR_AFFLVL1
22 #define SQ_PWR_LVL2		MPIDR_AFFLVL2
23 
24 #define SQ_CORE_PWR_STATE(state)	(state)->pwr_domain_state[SQ_PWR_LVL0]
25 #define SQ_CLUSTER_PWR_STATE(state)	(state)->pwr_domain_state[SQ_PWR_LVL1]
26 #define SQ_SYSTEM_PWR_STATE(state)	((PLAT_MAX_PWR_LVL > SQ_PWR_LVL1) ?\
27 				(state)->pwr_domain_state[SQ_PWR_LVL2] : 0)
28 
29 #define PLAT_MAX_PWR_LVL		U(1)
30 #define PLAT_MAX_RET_STATE		U(1)
31 #define PLAT_MAX_OFF_STATE		U(2)
32 
33 #define SQ_LOCAL_STATE_RUN		0
34 #define SQ_LOCAL_STATE_RET		1
35 #define SQ_LOCAL_STATE_OFF		2
36 
37 #define CACHE_WRITEBACK_SHIFT		6
38 #define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
39 
40 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
41 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
42 #define MAX_XLAT_TABLES			8
43 #define MAX_MMAP_REGIONS		8
44 
45 #if TRUSTED_BOARD_BOOT
46 #define PLATFORM_STACK_SIZE		0x1000
47 #else
48 #define PLATFORM_STACK_SIZE		0x400
49 #endif
50 
51 #if !RESET_TO_BL31
52 
53 /* A mailbox page will be mapped from BL2 and BL31 */
54 #define BL2_MAILBOX_BASE		0x0403f000
55 #define BL2_MAILBOX_SIZE		0x1000
56 
57 #define PLAT_SQ_BOOTIDX_BASE		0x08510000
58 #define PLAT_SQ_MAX_BOOT_INDEX		2
59 
60 #define MAX_IO_HANDLES			2
61 #define MAX_IO_DEVICES			2
62 #define MAX_IO_BLOCK_DEVICES	U(1)
63 
64 #define BL2_BASE			0x04000000
65 #define BL2_SIZE			(256 * 1024)
66 #define BL2_LIMIT			(BL2_BASE + BL2_SIZE)
67 
68 /* If BL2 is enabled, the BL31 is loaded on secure DRAM */
69 #define BL31_BASE			0xfbe00000
70 #define BL31_SIZE			0x00100000
71 #else
72 
73 #define BL31_BASE			0x04000000
74 #define BL31_SIZE			0x00080000
75 #endif
76 
77 #define BL31_LIMIT			(BL31_BASE + BL31_SIZE)
78 
79 #define BL32_BASE			0xfc000000
80 #define BL32_SIZE			0x03c00000
81 #define BL32_LIMIT			(BL32_BASE + BL32_SIZE)
82 
83 /* Alternative BL33 */
84 #define PLAT_SQ_BL33_BASE		0xe0000000
85 #define PLAT_SQ_BL33_SIZE		0x00200000
86 
87 /* FWU FIP IO base */
88 #define PLAT_SQ_FIP_IOBASE		0x08600000
89 #define PLAT_SQ_FIP_MAXSIZE		0x00400000
90 
91 #define PLAT_SQ_CCN_BASE		0x32000000
92 #define PLAT_SQ_CLUSTER_TO_CCN_ID_MAP					\
93 					0,	/* Cluster 0 */		\
94 					18,	/* Cluster 1 */		\
95 					11,	/* Cluster 2 */		\
96 					29,	/* Cluster 3 */		\
97 					35,	/* Cluster 4 */		\
98 					17,	/* Cluster 5 */		\
99 					12,	/* Cluster 6 */		\
100 					30,	/* Cluster 7 */		\
101 					14,	/* Cluster 8 */		\
102 					32,	/* Cluster 9 */		\
103 					15,	/* Cluster 10 */	\
104 					33	/* Cluster 11 */
105 
106 /* UART related constants */
107 #define PLAT_SQ_BOOT_UART_BASE		0x2A400000
108 #define PLAT_SQ_BOOT_UART_CLK_IN_HZ	62500000
109 #define SQ_CONSOLE_BAUDRATE		115200
110 
111 #define SQ_SYS_CNTCTL_BASE		0x2a430000
112 
113 #define SQ_SYS_TIMCTL_BASE		0x2a810000
114 #define PLAT_SQ_NSTIMER_FRAME_ID	0
115 #define SQ_SYS_CNT_BASE_NS		0x2a830000
116 
117 #define DRAMINFO_BASE			0x2E00FFC0
118 
119 #define PLAT_SQ_MHU_BASE		0x45000000
120 
121 #define PLAT_SQ_SCP_COM_SHARED_MEM_BASE		0x45400000
122 #define SCPI_CMD_GET_DRAMINFO			0x1
123 
124 #define SQ_BOOT_CFG_ADDR			0x45410000
125 #define PLAT_SQ_PRIMARY_CPU_SHIFT		8
126 #define PLAT_SQ_PRIMARY_CPU_BIT_WIDTH		6
127 
128 #define PLAT_SQ_GICD_BASE		0x30000000
129 #define PLAT_SQ_GICR_BASE		0x30400000
130 
131 #define PLAT_SQ_GPIO_BASE		0x51000000
132 
133 #define PLAT_SPM_BUF_BASE		(BL32_LIMIT - 32 * PLAT_SPM_BUF_SIZE)
134 #define PLAT_SPM_BUF_SIZE		ULL(0x10000)
135 #define PLAT_SPM_SPM_BUF_EL0_MMAP	MAP_REGION2(PLAT_SPM_BUF_BASE, \
136 						    PLAT_SPM_BUF_BASE, \
137 						    PLAT_SPM_BUF_SIZE, \
138 						    MT_RO_DATA | MT_SECURE | \
139 						    MT_USER, PAGE_SIZE)
140 
141 #define PLAT_SP_IMAGE_NS_BUF_BASE	BL32_LIMIT
142 #define PLAT_SP_IMAGE_NS_BUF_SIZE	ULL(0x200000)
143 #define PLAT_SP_IMAGE_NS_BUF_MMAP	MAP_REGION2(PLAT_SP_IMAGE_NS_BUF_BASE, \
144 						    PLAT_SP_IMAGE_NS_BUF_BASE, \
145 						    PLAT_SP_IMAGE_NS_BUF_SIZE, \
146 						    MT_RW_DATA | MT_NS | \
147 						    MT_USER, PAGE_SIZE)
148 
149 #define PLAT_SP_IMAGE_STACK_PCPU_SIZE	ULL(0x10000)
150 #define PLAT_SP_IMAGE_STACK_SIZE	(32 * PLAT_SP_IMAGE_STACK_PCPU_SIZE)
151 #define PLAT_SP_IMAGE_STACK_BASE	(PLAT_SQ_SP_HEAP_BASE + PLAT_SQ_SP_HEAP_SIZE)
152 
153 #define PLAT_SQ_SP_IMAGE_SIZE		ULL(0x200000)
154 #define PLAT_SQ_SP_IMAGE_MMAP		MAP_REGION2(BL32_BASE, BL32_BASE, \
155 						    PLAT_SQ_SP_IMAGE_SIZE, \
156 						    MT_CODE | MT_SECURE | \
157 						    MT_USER, PAGE_SIZE)
158 
159 #define PLAT_SQ_SP_HEAP_BASE		(BL32_BASE + PLAT_SQ_SP_IMAGE_SIZE)
160 #define PLAT_SQ_SP_HEAP_SIZE		ULL(0x800000)
161 
162 #define PLAT_SQ_SP_IMAGE_RW_MMAP	MAP_REGION2(PLAT_SQ_SP_HEAP_BASE, \
163 						    PLAT_SQ_SP_HEAP_BASE, \
164 						    (PLAT_SQ_SP_HEAP_SIZE + \
165 						     PLAT_SP_IMAGE_STACK_SIZE), \
166 						    MT_RW_DATA | MT_SECURE | \
167 						    MT_USER, PAGE_SIZE)
168 
169 #define PLAT_SQ_SP_PRIV_BASE		(PLAT_SP_IMAGE_STACK_BASE + \
170 					 PLAT_SP_IMAGE_STACK_SIZE)
171 #define PLAT_SQ_SP_PRIV_SIZE		ULL(0x40000)
172 
173 #define PLAT_SP_PRI			0x20
174 #define PLAT_PRI_BITS			2
175 #define PLAT_SPM_COOKIE_0		ULL(0)
176 #define PLAT_SPM_COOKIE_1		ULL(0)
177 
178 /* Total number of memory regions with distinct properties */
179 #define PLAT_SP_IMAGE_NUM_MEM_REGIONS	6
180 
181 #define PLAT_SP_IMAGE_MMAP_REGIONS	30
182 #define PLAT_SP_IMAGE_MAX_XLAT_TABLES	20
183 #define PLAT_SP_IMAGE_XLAT_SECTION_NAME	"sp_xlat_table"
184 #define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME	"sp_xlat_table"
185 
186 #define PLAT_SQ_UART1_BASE		PLAT_SQ_BOOT_UART_BASE
187 #define PLAT_SQ_UART1_SIZE		ULL(0x1000)
188 #define PLAT_SQ_UART1_MMAP		MAP_REGION_FLAT(PLAT_SQ_UART1_BASE, \
189 							PLAT_SQ_UART1_SIZE, \
190 							MT_DEVICE | MT_RW | \
191 							MT_NS | MT_PRIVILEGED)
192 
193 #define PLAT_SQ_PERIPH_BASE		0x50000000
194 #define PLAT_SQ_PERIPH_SIZE		ULL(0x8000000)
195 #define PLAT_SQ_PERIPH_MMAP		MAP_REGION_FLAT(PLAT_SQ_PERIPH_BASE, \
196 							PLAT_SQ_PERIPH_SIZE, \
197 							MT_DEVICE | MT_RW | \
198 							MT_NS | MT_USER)
199 
200 #define PLAT_SQ_FLASH_BASE		0x08000000
201 #define PLAT_SQ_FLASH_SIZE		ULL(0x8000000)
202 #define PLAT_SQ_FLASH_MMAP		MAP_REGION_FLAT(PLAT_SQ_FLASH_BASE, \
203 							PLAT_SQ_FLASH_SIZE, \
204 							MT_DEVICE | MT_RW | \
205 							MT_NS | MT_USER)
206 
207 #endif /* PLATFORM_DEF_H */
208