1 /* 2 * Copyright (c) 2018 Travis Geiselbrecht 3 * 4 * Use of this source code is governed by a MIT-style 5 * license that can be found in the LICENSE file or at 6 * https://opensource.org/licenses/MIT 7 */ 8 #pragma once 9 10 // memory and irq layout of qemu's riscv virt platform 11 // 12 // mostly taken from the top of qemu/hw/riscv/virt.c and similar headers 13 14 #if RISCV_XMODE_OFFSET == RISCV_MACH_OFFSET 15 #define PLIC_HART_IDX(hart) (2 * (hart)) 16 #elif RISCV_XMODE_OFFSET == RISCV_SUPER_OFFSET 17 #define PLIC_HART_IDX(hart) ((2 * (hart)) + 1) 18 #endif 19 20 #define MEMORY_BASE_PHYS (0x80000000) 21 #if __riscv_xlen == 64 22 // up to 64 GB of ram, which seems to be a soft cap 23 #define MEMORY_APERTURE_SIZE (64ULL * 1024 * 1024 * 1024) 24 #else 25 // cap after 1GB 26 #define MEMORY_APERTURE_SIZE (1UL * 1024 * 1024 * 1024) 27 #endif 28 29 // map all of 0-1GB into kernel space in one shot 30 #define PERIPHERAL_BASE_PHYS (0) 31 #define PERIPHERAL_BASE_SIZE (0x40000000UL) // 1GB 32 33 // use the giant mapping at the bottom of the kernel as our peripheral space 34 #if WITH_KERNEL_VM 35 #define PERIPHERAL_BASE_VIRT (KERNEL_ASPACE_BASE + PERIPHERAL_BASE_PHYS) 36 #else 37 // if no mmu, just treat virt == phys 38 #define PERIPHERAL_BASE_VIRT (PERIPHERAL_BASE_PHYS) 39 #endif 40 41 // interrupts 42 #define IRQ_VIRTIO_BASE 1 43 #define IRQ_UART0 10 44 #define IRQ_PCIE_BASE 0x20 45 #define NUM_IRQS 127 46 47 // addresses of some peripherals 48 #define CLINT_BASE 0x02000000 49 #define CLINT_BASE_VIRT (PERIPHERAL_BASE_VIRT + CLINT_BASE) 50 #define PLIC_BASE 0x0c000000 51 #define PLIC_BASE_VIRT (PERIPHERAL_BASE_VIRT + PLIC_BASE) 52 #define UART0_BASE 0x10000000 53 #define UART0_BASE_VIRT (PERIPHERAL_BASE_VIRT + UART0_BASE) 54 #define VIRTIO_BASE 0x10001000 55 #define VIRTIO_BASE_VIRT (PERIPHERAL_BASE_VIRT + VIRTIO_BASE) 56 #define DRAM_BASE 0x80000000 57 #define DRAM_BASE_VIRT (PERIPHERAL_BASE_VIRT + DRAM_BASE) 58 59 #define NUM_VIRTIO_TRANSPORTS 8 60 #define VIRTIO_STRIDE 0x1000 61