1 /* 2 * Copyright (c) 2015 Brian Swetland 3 * 4 * Use of this source code is governed by a MIT-style 5 * license that can be found in the LICENSE file or at 6 * https://opensource.org/licenses/MIT 7 */ 8 9 #pragma once 10 11 #define FREQ_MON 0x40050014 12 #define XTAL_OSC_CTRL 0x40050018 13 14 #define PLL0USB_STAT 0x4005001C 15 #define PLL0USB_CTRL 0x40050020 16 #define PLL0USB_MDIV 0x40050024 17 #define PLL0USB_NP_DIV 0x40050028 18 19 #define PLL0AUDIO_STAT 0x4005002C 20 #define PLL0AUDIO_CTRL 0x40050030 21 #define PLL0AUDIO_MDIV 0x40050034 22 #define PLL0AUDIO_NP_DIV 0x40050038 23 #define PLL0AUDIO_FRAC 0x4005003C 24 25 #define PLL1_STAT 0x40050040 26 #define PLL1_CTRL 0x40050044 27 28 #define IDIVA_CTRL 0x40050048 // /(1..4) IRC, CLKIN, XTAL, PLLs 29 #define IDIVB_CTRL 0x4005004C // /(1..16) IRC, CLKIN, XTAL, PLL0AUDIO, PLL1, IDIVA 30 #define IDIVC_CTRL 0x40050050 // /(1..16) " 31 #define IDIVD_CTRL 0x40050054 // /(1..16) " 32 #define IDIVE_CTRL 0x40050058 // /(1..256) IRC, CLKIN, XTAL, PLL0AUDIO, PLL1, IDIVA 33 34 #define BASE_SAFE_CLK 0x4005005C // only CLK_IRC allowed 35 #define BASE_USB0_CLK 0x40050060 // only CLK_PLL0USB allowed 36 #define BASE_PERIPH_CLK 0x40050064 37 #define BASE_USB1_CLK 0x40050068 38 #define BASE_M4_CLK 0x4005006C 39 #define BASE_SPIFI_CLK 0x40050070 40 #define BASE_SPI_CLK 0x40050074 41 #define BASE_PHY_RX_CLK 0x40050078 42 #define BASE_PHY_TX_CLK 0x4005008C 43 #define BASE_APB1_CLK 0x40050080 44 #define BASE_APB3_CLK 0x40050084 45 #define BASE_LCD_CLK 0x40050088 46 #define BASE_ADCHS_CLK 0x4005008C 47 #define BASE_SDIO_CLK 0x40050090 48 #define BASE_SSP0_CLK 0x40050094 49 #define BASE_SSP1_CLK 0x40050098 50 #define BASE_UART0_CLK 0x4005009C 51 #define BASE_UART1_CLK 0x400500A0 52 #define BASE_UART2_CLK 0x400500A4 53 #define BASE_UART3_CLK 0x400500A8 54 #define BASE_OUT_CLK 0x400500AC 55 #define BASE_AUDIO_CLK 0x400500C0 56 #define BASE_CGU_OUT0_CLK 0x400500C4 57 #define BASE_CGU_OUT1_CLK 0x400500C8 58 59 #define BASE_PD (1 << 0) // power-down 60 #define BASE_AUTOBLOCK (1 << 11) 61 #define BASE_CLK_SEL(n) ((n) << 24) 62 63 #define PLL0_STAT_LOCK (1 << 0) 64 #define PLL0_STAT_FR (1 << 1) 65 66 #define PLL0_CTRL_PD (1 << 0) // power down 67 #define PLL0_CTRL_BYPASS (1 << 1) // input sent to post-div 68 #define PLL0_CTRL_DIRECTI (1 << 2) 69 #define PLL0_CTRL_DIRECTO (1 << 3) 70 #define PLL0_CTRL_CLKEN (1 << 4) 71 #define PLL0_CTRL_FRM (1 << 6) // free running mode 72 #define PLL0_CTRL_AUTOBLOCK (1 << 11) 73 #define PLL0_CTRL_CLK_SEL(n) ((n) << 24) // input clock select 74 // PLL0AUDIO only: 75 #define PLL0_CTRL_PLLFRACT_REQ (1 << 12) 76 #define PLL0_CTRL_SEL_EXT (1 << 13) 77 #define PLL0_CTRL_MOD_PD (1 << 14) 78 79 #define PLL1_STAT_LOCK (1 << 0) 80 81 #define PLL1_CTRL_PD (1 << 0) 82 #define PLL1_CTRL_BYPASS (1 << 1) 83 #define PLL1_CTRL_FBSEL (1 << 6) 84 #define PLL1_CTRL_DIRECT (1 << 7) 85 #define PLL1_CTRL_PSEL_1 (0 << 8) 86 #define PLL1_CTRL_PSEL_2 (1 << 8) 87 #define PLL1_CTRL_PSEL_4 (2 << 8) 88 #define PLL1_CTRL_PSEL_8 (3 << 8) 89 #define PLL1_CTRL_AUTOBLOCK (1 << 11) 90 #define PLL1_CTRL_NSEL_1 (0 << 12) 91 #define PLL1_CTRL_NSEL_2 (1 << 12) 92 #define PLL1_CTRL_NSEL_3 (2 << 12) 93 #define PLL1_CTRL_NSEL_4 (3 << 12) 94 #define PLL1_CTRL_MSEL(m) (((m) - 1) << 16) 95 #define PLL1_CTRL_CLK_SEL(c) ((c) << 24) 96 97 #define IDIV_PD (1 << 0) 98 #define IDIV_N(n) (((n) - 1) << 2) 99 #define IDIV_AUTOBLOCK (1 << 11) 100 #define IDIV_CLK_SEL(c) ((c) << 24) 101 102 #define CLK_32K 0x00 103 #define CLK_IRC 0x01 // 12MHz internal RC OSC 104 #define CLK_ENET_RX 0x02 105 #define CLK_ENET_TX 0x03 106 #define CLK_GP_CLKIN 0x04 107 #define CLK_XTAL 0x06 // crystal oscillator 108 #define CLK_PLL0USB 0x07 // only for BASE_{USB0,USB1,OUT}_CLK 109 #define CLK_PLL0AUDIO 0x08 110 #define CLK_PLL1 0x09 111 #define CLK_IDIVA 0x0C 112 #define CLK_IDIVB 0x0D 113 #define CLK_IDIVC 0x0E 114 #define CLK_IDIVD 0x0F 115 #define CLK_IDIVE 0x10 116 117