1 /**
2 ******************************************************************************
3 * @file rtl8721d_pll.c
4 * @author
5 * @version V1.0.0
6 * @date 2016-05-17
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the NCO clock:
9 * - NCO32k
10 * - NCO8M
11 * - EXT32k Disable/Enable
12 ******************************************************************************
13 * @attention
14 *
15 * This module is a confidential and proprietary property of RealTek and
16 * possession or use of this module requires written permission of RealTek.
17 *
18 * Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
19 ******************************************************************************
20 */
21
22 #include "ameba_soc.h"
23
24 /**
25 * @brief PLL divider set
26 * @param div: Division
27 */
PLL_Div(u32 div)28 void PLL_Div(u32 div)
29 {
30 u32 Tmp;
31
32 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PERI_CLK_CTRL3);
33 Tmp &= ~(BIT_MASK_HSYS_I2S_CLKDIV << BIT_SHIFT_HSYS_I2S_CLKDIV);
34 Tmp |= ((u32)div) << BIT_SHIFT_HSYS_I2S_CLKDIV;
35 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PERI_CLK_CTRL3, Tmp);
36 }
37
38 /**
39 * @brief I2S or PCM PLL select
40 * @param sel: PLL select
41 */
PLL_Sel(u32 sel)42 void PLL_Sel(u32 sel)
43 {
44 u32 Tmp;
45
46 if ((sel == PLL_PCM) ||(sel == PLL_I2S)){
47 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PERI_CLK_CTRL3);
48 Tmp &= ~(BIT_MASK_HSYS_AC_SPORT_CKSL << BIT_SHIFT_HSYS_AC_SPORT_CKSL);
49 Tmp |= ((u32)sel) << BIT_SHIFT_HSYS_AC_SPORT_CKSL;
50 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PERI_CLK_CTRL3, Tmp);
51 }
52 else{
53
54 }
55 }
56
57
58 /**
59 * @brief I2S PLL control register set.
60 * @param new_state: DISABLE/ENABLE
61 */
PLL_I2S_Set(u32 new_state)62 void PLL_I2S_Set(u32 new_state)
63 {
64 u32 Tmp;
65
66
67 if (ENABLE == new_state){
68 //enable 98.304M PLL
69 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0);
70 Tmp |= BIT_SYS_AMACRO_EN;
71 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0, Tmp);
72
73 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0);
74 Tmp |= (BIT_LP_PLL_BG_I_EN |BIT_LP_PLL_BG_EN);
75 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0, Tmp);
76
77 DelayUs(2);
78
79 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0);
80 Tmp |= BIT_LP_PLL_MBIAS_EN;
81 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0, Tmp);
82
83 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0);
84 Tmp |= BIT_PLL_I2S_POWCUT_EN;
85 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0, Tmp);
86
87 DelayUs(400);
88
89 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_XTAL_CTRL1);
90 Tmp &= ~BIT_XTAL_AAC_GM_EN;
91 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_XTAL_CTRL1, Tmp);
92
93 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0);
94 Tmp |= (BIT_PLL_I2S_DIV_EN | BIT_PLL_I2S_EN);
95 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0, Tmp);
96
97 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PWR_ISO_CTRL);
98 Tmp &= ~BIT_HSYS_ISO_AUXPLL_I2S;
99 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PWR_ISO_CTRL, Tmp);
100
101 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL1);
102 Tmp |= BIT_PLL_I2S_POW_SDM_FCODE;
103 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL1, Tmp);
104
105 while ((HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_TEST) & BIT_PLL_I2S_RDY) != BIT_PLL_I2S_RDY) ;
106
107 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0);
108 Tmp |= BIT_PLL_I2S_CLK_EN;
109 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0, Tmp);
110
111 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0);
112 Tmp |= BIT_PLL_I2S_DIV2_EN;
113 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0, Tmp);
114 }
115 else{
116 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0);
117 Tmp &= ~(BIT_PLL_I2S_CLK_EN|BIT_PLL_I2S_DIV2_EN|BIT_PLL_I2S_EN|BIT_PLL_I2S_DIV_EN|BIT_PLL_I2S_DIV_EN);
118 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0, Tmp);
119 }
120 }
121
122 /**
123 * @brief PCM PLL control register set.
124 * @param new_state: DISABLE/ENABLE
125 */
PLL_PCM_Set(u32 new_state)126 void PLL_PCM_Set(u32 new_state)
127 {
128 u32 Tmp;
129
130
131 if (ENABLE == new_state){
132 //enable 45.1584M PLL
133 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0);
134 Tmp |= BIT_SYS_AMACRO_EN;
135 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0, Tmp);
136
137 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0);
138 Tmp |= (BIT_LP_PLL_BG_I_EN |BIT_LP_PLL_BG_EN);
139 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0, Tmp);
140
141 DelayUs(2);
142
143 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0);
144 Tmp |= BIT_LP_PLL_MBIAS_EN;
145 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0, Tmp);
146
147 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0);
148 Tmp |= BIT_PLL_PCM_POWCUT_EN;
149 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0, Tmp);
150
151 DelayUs(400);
152
153 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_XTAL_CTRL1);
154 Tmp &= ~BIT_XTAL_AAC_GM_EN;
155 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_XTAL_CTRL1, Tmp);
156
157 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0);
158 Tmp |= (BIT_PLL_PCM_DIV_EN | BIT_PLL_PCM_EN);
159 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0, Tmp);
160
161 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PWR_ISO_CTRL);
162 Tmp &= ~BIT_HSYS_ISO_AUXPLL_PCM;
163 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PWR_ISO_CTRL, Tmp);
164
165 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL1);
166 Tmp |= BIT_PLL_PCM_POW_SDM_FCODE;
167 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL1, Tmp);
168
169 while ((HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_TEST) & BIT_PLL_PCM_RDY) != BIT_PLL_PCM_RDY) ;
170
171 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0);
172 Tmp |= BIT_PLL_PCM_CLK_EN;
173 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0, Tmp);
174
175 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0);
176 Tmp |= BIT_PLL_PCM_DIV2_EN;
177 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0, Tmp);
178 }
179 else{
180 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0);
181 Tmp &= ~(BIT_PLL_PCM_CLK_EN|BIT_PLL_PCM_DIV2_EN|BIT_PLL_PCM_EN|BIT_PLL_PCM_DIV_EN|BIT_PLL_PCM_DIV_EN);
182 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0, Tmp);
183 }
184 }
185
186 /**
187 * @brief I2S PLL output adjust by ppm.
188 * @param ppm: ~0.75ppm per FOF step
189 * @param action: slower or faster or reset
190 * This parameter can be one of the following values:
191 * @arg PLL_AUTO: reset to auto 98.304M
192 * @arg PLL_FASTER: pll clock faster than 98.304M
193 * @arg PLL_SLOWER: pll clock slower than 98.304M
194 */
PLL_I2S_ClkTune(u32 ppm,u32 action)195 void PLL_I2S_ClkTune(u32 ppm, u32 action)
196 {
197 u32 Tmp;
198 u32 FOF_new;
199
200 assert_param(ppm<=100);
201
202 if (action == PLL_AUTO){
203 //switch to auto mode
204 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0);
205 Tmp |= BIT2;
206 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0, Tmp);
207 return;
208 }
209
210 //switch to manual mode
211 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0);
212 Tmp &= ~BIT2;
213 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0, Tmp);
214
215 //set div.N
216 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL1);
217 Tmp &= ~(BIT_PLL_MASK_I2S_DIVN_SDM<<BIT_PLL_SHIFT_I2S_DIVN_SDM);
218 Tmp |= (u32)0x11<<BIT_PLL_SHIFT_I2S_DIVN_SDM;
219 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL1, Tmp);
220
221 //adjust fo.N, fo.f
222 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL3);
223 if (action == PLL_FASTER){
224 FOF_new = 0x92a+ppm*4/3;
225 }
226 else if (action == PLL_SLOWER){
227 FOF_new = 0x92a-ppm*4/3;
228 }
229 else{
230 FOF_new = 0x92a;
231 }
232 Tmp &= ~((BIT_PLL_MASK_I2S_SDM_FON<<BIT_PLL_SHIFT_I2S_SDM_FON)|(BIT_PLL_MASK_I2S_SDM_FOF<<BIT_PLL_SHIFT_I2S_SDM_FOF));
233 Tmp |= (u32)FOF_new<<BIT_PLL_SHIFT_I2S_SDM_FOF;
234 Tmp |= (u32)0x5<<BIT_PLL_SHIFT_I2S_SDM_FON;
235 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL3, Tmp);
236
237 //reset BIT_PLL_I2S_TRIG_RREQ_EN
238 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL1);
239 Tmp |= BIT_PLL_I2S_TRIG_RREQ_EN;
240 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL1, Tmp);
241
242 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL1);
243 Tmp &= ~BIT_PLL_I2S_TRIG_RREQ_EN;
244 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL1, Tmp);
245 }
246
247
248 /**
249 * @brief PCM PLL output adjust by ppm.
250 * @param ppm: ~5/6*ppm per FOF step
251 * @param action: slower or faster or reset
252 * This parameter can be one of the following values:
253 * @arg PLL_AUTO: reset to auto 45.1584M
254 * @arg PLL_FASTER: pll clock faster than 45.1584M
255 * @arg PLL_SLOWER: pll clock slower than 45.1584M
256 */
PLL_PCM_ClkTune(u32 ppm,u32 action)257 void PLL_PCM_ClkTune(u32 ppm, u32 action)
258 {
259 u32 Tmp;
260 u32 FOF_new;
261
262 assert_param(ppm<=100);
263
264 if (action == PLL_AUTO){
265 //switch to auto mode
266 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0);
267 Tmp |= BIT2;
268 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0, Tmp);
269 return;
270 }
271
272 //switch to manual mode
273 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0);
274 Tmp &= ~BIT2;
275 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0, Tmp);
276
277 //set div.N
278 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL1);
279 Tmp &= ~(BIT_PLL_MASK_PCM_DIVN_SDM<<BIT_PLL_SHIFT_PCM_DIVN_SDM);
280 Tmp |= (u32)0x10<<BIT_PLL_SHIFT_PCM_DIVN_SDM;
281 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL1, Tmp);
282
283 //adjust fo.N, fo.f
284 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL3);
285 if (action == PLL_FASTER){
286 FOF_new = 0x1038+ppm*6/5;
287 }
288 else if (action == PLL_SLOWER){
289 FOF_new = 0x1038-ppm*6/5;
290 }
291 else{
292 FOF_new = 0x1038;
293 }
294 Tmp &= ~((BIT_PLL_MASK_PCM_SDM_FON<<BIT_PLL_SHIFT_PCM_SDM_FON)|(BIT_PLL_MASK_PCM_SDM_FOF<<BIT_PLL_SHIFT_PCM_SDM_FOF));
295 Tmp |= (u32)FOF_new<<BIT_PLL_SHIFT_PCM_SDM_FOF;
296 Tmp |= (u32)0x0<<BIT_PLL_SHIFT_PCM_SDM_FON;
297 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL3, Tmp);
298
299 //reset BIT_PLL_PCM_TRIG_RREQ_EN
300 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL1);
301 Tmp |= BIT_PLL_PCM_TRIG_RREQ_EN;
302 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL1, Tmp);
303
304 Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL1);
305 Tmp &= ~BIT_PLL_PCM_TRIG_RREQ_EN;
306 HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL1, Tmp);
307 }
308
309 /**
310 * @brief PLL control register2 set.
311 * @param BitMask: set bit
312 * @param NewState: DISABLE/ENABLE
313 */
PLL2_Set(u32 BitMask,u32 NewState)314 void PLL2_Set(u32 BitMask, u32 NewState)
315 {
316 /* To avoid gcc warnings */
317 ( void ) BitMask;
318 ( void ) NewState;
319 #ifdef AMEBAD_TODO
320 DBG_8195A("%s Please check this function \n", __func__);
321 #endif
322 }
323
324 /**
325 * @brief PLL control register3 set.
326 * @param BitMask: set bit
327 * @param NewState: DISABLE/ENABLE
328 */
PLL3_Set(u32 BitMask,u32 NewState)329 void PLL3_Set(u32 BitMask, u32 NewState)
330 {
331 /* To avoid gcc warnings */
332 ( void ) BitMask;
333 ( void ) NewState;
334
335 #ifdef AMEBAD_TODO
336 DBG_8195A("%s Please check this function \n", __func__);
337 #endif
338 }
339 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
340