1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_INTEL_PT_H
3 #define _ASM_X86_INTEL_PT_H
4 
5 #define PT_CPUID_LEAVES		2
6 #define PT_CPUID_REGS_NUM	4 /* number of registers (eax, ebx, ecx, edx) */
7 
8 enum pt_capabilities {
9 	PT_CAP_max_subleaf = 0,
10 	PT_CAP_cr3_filtering,
11 	PT_CAP_psb_cyc,
12 	PT_CAP_ip_filtering,
13 	PT_CAP_mtc,
14 	PT_CAP_ptwrite,
15 	PT_CAP_power_event_trace,
16 	PT_CAP_event_trace,
17 	PT_CAP_tnt_disable,
18 	PT_CAP_topa_output,
19 	PT_CAP_topa_multiple_entries,
20 	PT_CAP_single_range_output,
21 	PT_CAP_output_subsys,
22 	PT_CAP_payloads_lip,
23 	PT_CAP_num_address_ranges,
24 	PT_CAP_mtc_periods,
25 	PT_CAP_cycle_thresholds,
26 	PT_CAP_psb_periods,
27 };
28 
29 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL)
30 void cpu_emergency_stop_pt(void);
31 extern u32 intel_pt_validate_hw_cap(enum pt_capabilities cap);
32 extern u32 intel_pt_validate_cap(u32 *caps, enum pt_capabilities cap);
33 extern int is_intel_pt_event(struct perf_event *event);
34 #else
cpu_emergency_stop_pt(void)35 static inline void cpu_emergency_stop_pt(void) {}
intel_pt_validate_hw_cap(enum pt_capabilities cap)36 static inline u32 intel_pt_validate_hw_cap(enum pt_capabilities cap) { return 0; }
intel_pt_validate_cap(u32 * caps,enum pt_capabilities capability)37 static inline u32 intel_pt_validate_cap(u32 *caps, enum pt_capabilities capability) { return 0; }
is_intel_pt_event(struct perf_event * event)38 static inline int is_intel_pt_event(struct perf_event *event) { return 0; }
39 #endif
40 
41 #endif /* _ASM_X86_INTEL_PT_H */
42