1 /**
2 ******************************************************************************
3 * @file rtl8721dlp_qdec.c
4 * @author
5 * @version V1.0.0
6 * @date 2017-10-17
7 * @brief This file contains all the functions prototypes for the QDec firmware
8 * library, including the following functionalities of the Qdecoder
9 * -Initialization
10 * -QDec Control (disable/enable):
11 * -QDec Reset
12 * -Get status Interface
13 * -Interrupts and trigger condition management
14 * -QDec speed meausure
15 * -QDec speed limit Interrupts
16 *
17 * @verbatim
18 *
19 * ===================================================================
20 * How to use this driver
21 * ===================================================================
22 * 1. configure the QDec pinmux.
23 *
24 * 2. Init Qdec.
25 *
26 * 3. Reset sub-function if needed.
27 *
28 * 4. Set Interrupt trigger condition as needed.
29 *
30 * 5. enable sub-function as needed.
31 *
32 * 6. Polling status or Get stauts according to the interrupt.
33 *
34 *
35 * @endverbatim
36 *
37 ******************************************************************************
38 * @attention
39 *
40 * This module is a confidential and proprietary property of RealTek and
41 * possession or use of this module requires written permission of RealTek.
42 *
43 * Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
44 ******************************************************************************
45 */
46
47
48 #include "ameba_soc.h"
49
50 /**
51 * @brief Deinitializes the QDEC peripheral registers .
52 * @param None.
53 * @retval None
54 */
QDEC_DeInit(void)55 void QDEC_DeInit(void)
56 {
57 RCC_PeriphClockCmd(APBPeriph_QDEC0, APBPeriph_QDEC0_CLOCK, DISABLE);
58 }
59
60 /**
61 * @brief Initializes the QDEC peripheral according to the specified.
62 * @param QDEC_InitStruct: pointer to a QDEC_InitTypeDef structure that
63 * contains the configuration information for the specified QDEC peripheral.
64 * @retval None.
65 */
QDEC_Init(QDEC_TypeDef * QDec,QDEC_InitTypeDef * QDEC_InitStruct)66 void QDEC_Init(QDEC_TypeDef *QDec, QDEC_InitTypeDef *QDEC_InitStruct)
67 {
68 u32 VTmr_rld;
69 u8 VTmr_Div = 0;
70
71 /* Check the parameters */
72 assert_param(IS_QD_SYS_CLK(QDEC_InitStruct->QD_SysClk));
73 assert_param(QDEC_InitStruct->QD_SmpClk <= QDEC_InitStruct->QD_SysClk);
74 assert_param(QDEC_InitStruct->QD_SmpClk >= (QDEC_InitStruct->QD_SysClk >> 5));
75 assert_param(QDEC_InitStruct->QD_DebounceTmr <= 0x7ff);
76 assert_param(IS_QD_RC_COUNT_MOD(QDEC_InitStruct->QD_Rc_Mod));
77 assert_param(IS_QD_PC_PHASE_COUTER(QDEC_InitStruct->QD_Cnt_Sc));
78 assert_param(QDEC_InitStruct->QD_MPC <= 0xFFFF);
79 assert_param(IS_QD_IDX_MODE(QDEC_InitStruct->QD_IdxMod));
80 assert_param(IS_QD_PC_RST_MODE(QDEC_InitStruct->QD_PC_Rst_Mod));
81 assert_param(IS_QD_PC_RST_PHASE(QDEC_InitStruct->QD_PC_Rst_Phase));
82 assert_param(IS_QD_VC_MODE(QDEC_InitStruct->QD_VCMod));
83
84 /*to avoid overflow*/
85 /*VTmr_rld =VTmr /(1000/SysClk) = VTmr*SysClk/1000 = Vtmr *(sysclk/1024)*/
86 VTmr_rld = QDEC_InitStruct->QD_VTmr * (QDEC_InitStruct->QD_SysClk/1000);
87 assert_param(VTmr_rld <= 0xFFFFFF);
88 while((VTmr_rld / (1+VTmr_Div)) > 0xFFFF){
89 VTmr_Div++;
90 }
91 VTmr_rld /= (VTmr_Div+1);
92
93 RCC_PeriphClockCmd(APBPeriph_QDEC0, APBPeriph_QDEC0_CLOCK, DISABLE);
94 if(QDEC_InitStruct->QD_SysClk == QD_SYS_CLK_2M){
95 RCC_PeriphClockSource_QDEC(0, QDEC_CLK_SEL_2M);
96 }
97 else{
98 RCC_PeriphClockSource_QDEC(0, QDEC_CLK_SEL_32K);
99 }
100 RCC_PeriphClockCmd(APBPeriph_QDEC0, APBPeriph_QDEC0_CLOCK, ENABLE);
101
102 QDec->QDEC_CLK_CFG = (((QDEC_InitStruct->QD_SysClk /QDEC_InitStruct->QD_SmpClk)-1) << 12) |\
103 (QDEC_InitStruct->QD_DebounceTmr);
104
105 QDec->QDEC_CTRL = QDEC_InitStruct->QD_Rc_Mod |QDEC_InitStruct->QD_Cnt_Sc | \
106 (QDEC_InitStruct->QD_DebounceTmr ? QD_DB_EN:0);
107
108 QDec->QDEC_MPC = QDEC_InitStruct ->QD_MPC;
109
110 QDec->QDEC_ISC = QDEC_InitStruct->QD_IdxMod | QDEC_InitStruct->QD_PC_Rst_Mod | \
111 QDEC_InitStruct->QD_PC_Rst_Phase;
112
113 QDec->QDEC_VCTRL = ((VTmr_Div) << 16) | QDEC_InitStruct->QD_VCMod;
114 QDec->QDEC_VTRLD = VTmr_rld;
115
116
117 }
118
119 /**
120 * @brief Fills each QDEC_InitStruct member with its default value.
121 * @param QDEC_InitStruct: pointer to an QDEC_InitTypeDef structure which will be initialized.
122 * @retval None.
123 */
QDEC_StructInit(QDEC_InitTypeDef * QDEC_InitStruct)124 void QDEC_StructInit(QDEC_InitTypeDef *QDEC_InitStruct)
125 {
126 QDEC_InitStruct->QD_SysClk = QD_SYS_CLK_32K;
127 QDEC_InitStruct->QD_SmpClk = 10000;
128 QDEC_InitStruct->QD_DebounceTmr = 1;
129 QDEC_InitStruct->QD_Rc_Mod = QD_RC_COUNT_OF;
130 QDEC_InitStruct->QD_Cnt_Sc = QD_PC_1PHSAE_1COUNTER;
131 QDEC_InitStruct->QD_MPC = 0xFFFF;
132 QDEC_InitStruct->QD_IdxMod = QD_IDX_DISABLE;
133
134 QDEC_InitStruct->QD_PC_Rst_Mod = QD_PC_RST_DISABLE;
135 QDEC_InitStruct->QD_PC_Rst_Phase = QD_PC_RST_PHASE_00;
136 QDEC_InitStruct->QD_VTmr = 1000;
137 QDEC_InitStruct->QD_VCMod = QD_VC_MOD_ABS;
138
139 }
140
141 /**
142 * @brief Enable or disable the QDec.
143 * @param QDec: selected Qdec peripheral.
144 * @param NewState: new state of the QDec.
145 * This parameter can be: ENABLE or DISABLE.
146 * @retval None.
147 */
QDEC_Cmd(QDEC_TypeDef * QDec,u32 NewState)148 void QDEC_Cmd(QDEC_TypeDef *QDec, u32 NewState)
149 {
150 u8 trycnt =200;
151 u32 Cur_status = 0;
152
153 assert_param(IS_QDEC_ALL_PERIPH(QDec));
154
155 if (NewState == ENABLE){
156 QDec->QDEC_CTRL &= ~QD_MANUAL_INIT;
157 QDec->QDEC_CTRL |= QD_AXIS_EN;
158
159 //auto init should check until auto load done
160 do{
161 Cur_status = QDec->QDEC_PC;
162
163 if(Cur_status & QD_AL_STATUS)
164 break;
165
166 }while(trycnt--);
167 } else if (NewState == DISABLE) {
168 QDec->QDEC_CTRL &= ~QD_AXIS_EN;
169 }
170 }
171
172
173
174 /**
175 * @brief Reset QDec position counter .
176 * @param QDec: selected Qdec peripheral.
177 * @retval None.
178 */
QDEC_RstPC(QDEC_TypeDef * QDec)179 void QDEC_RstPC(QDEC_TypeDef *QDec)
180 {
181 u32 reg_ctrl;
182
183 assert_param(IS_QDEC_ALL_PERIPH(QDec));
184
185 reg_ctrl = QDec->QDEC_CTRL;
186 /*disable compare interrupt to avoid error trigger */
187 QDec->QDEC_CTRL &= ~(QD_AXIS_EN | QD_PC_CMP_INT_EN);
188
189 QDec->QDEC_CTRL |= QD_PC_RST;
190 QDec->QDEC_CTRL &= ~QD_PC_RST;
191
192 QDec->QDEC_CTRL = reg_ctrl;
193 }
194
195 /**
196 * @brief Reset QDec rotation counter .
197 * @param QDec: selected Qdec peripheral.
198 * @retval None.
199 */
QDEC_RstRC(QDEC_TypeDef * QDec)200 void QDEC_RstRC(QDEC_TypeDef *QDec)
201 {
202 u32 reg_ctrl;
203
204 assert_param(IS_QDEC_ALL_PERIPH(QDec));
205
206 reg_ctrl = QDec->QDEC_CTRL;
207
208 QDec->QDEC_CTRL &= ~(QD_AXIS_EN | QD_RC_CMP_INT_EN);
209
210 QDec->QDEC_CTRL |= QD_RC_RST;
211 QDec->QDEC_CTRL &= ~QD_RC_RST;
212
213 QDec->QDEC_CTRL = reg_ctrl;
214 }
215
216 /**
217 * @brief Reset QDec state machine and all other functions .
218 * @param QDec: selected Qdec peripheral.
219 * @retval None.
220 */
QDEC_RstALL(QDEC_TypeDef * QDec)221 void QDEC_RstALL(QDEC_TypeDef *QDec)
222 {
223 u32 reg_ctrl;
224
225 assert_param(IS_QDEC_ALL_PERIPH(QDec));
226
227 reg_ctrl = QDec->QDEC_CTRL;
228
229 QDec->QDEC_CTRL &= ~QD_AXIS_EN;
230
231 QDec->QDEC_CTRL |= QD_ALL_RST;
232 QDec->QDEC_CTRL &= ~QD_ALL_RST;
233
234 QDec->QDEC_CTRL = reg_ctrl;
235 }
236
237 /**
238 * @brief Configure the number of phase state changed for the position accumulation counter.
239 * @param QDec: selected Qdec peripheral.
240 * @param cnt_sc:This parameter can be one of the following values:
241 * @arg QD_PC_1PHSAE_1COUNTER: position counter change one when Qdecoder change one pahse.
242 * @arg QD_PC_2PHSAE_1COUNTER: position counter change one when Qdecoder change two pahse.
243 * @retval None.
244 */
QDEC_SetCntSC(QDEC_TypeDef * QDec,u32 cnt_sc)245 void QDEC_SetCntSC(QDEC_TypeDef *QDec, u32 cnt_sc)
246 {
247 u32 reg_ctrl;
248
249 assert_param(IS_QDEC_ALL_PERIPH(QDec));
250 assert_param(IS_QD_PC_PHASE_COUTER(cnt_sc));
251
252 reg_ctrl = QDec->QDEC_CTRL;
253 reg_ctrl &= ~QD_CNT_SC;
254 reg_ctrl |= cnt_sc;
255 QDec->QDEC_CTRL = reg_ctrl;
256 }
257
258 /**
259 * @brief Set Qdecoder position counter change interrupt trigger valure .
260 * @param QDec: selected Qdec peripheral.
261 * @param Pchange:This parameter can be one of the following values:
262 * @arg QD_PC_CHG_1COUNTER: position counter change +/-1 will trigger interrupt.
263 * @arg QD_PC_CHG_2COUNTER: position counter change +/-2 will trigger interrupt.
264 * @arg QD_PC_CHG_4COUNTER: position counter change +/-4 will trigger interrupt.
265 * @retval None.
266 */
QDEC_SetPChg(QDEC_TypeDef * QDec,u32 Pchange)267 void QDEC_SetPChg(QDEC_TypeDef *QDec, u32 Pchange)
268 {
269 u32 reg_ctrl;
270
271 assert_param(IS_QDEC_ALL_PERIPH(QDec));
272 assert_param(IS_QD_PC_CHG_COUTER(Pchange));
273
274 reg_ctrl = QDec->QDEC_CTRL;
275 /*Jerry_dong suggest because hw do not Exaggerate clock domain*/
276 QDec->QDEC_CTRL &= ~(QD_AXIS_EN | QD_PC_CHG_INT_EN);
277 reg_ctrl &= ~QD_PC_CHG_LEVEL;
278 reg_ctrl |= Pchange;
279 QDec->QDEC_CTRL = reg_ctrl;
280
281 }
282
283 /**
284 * @brief Set Qdecoder position counter compare value.
285 * @param QDec: selected Qdec peripheral.
286 * @param CmpPC: compare position counter value.
287 * @retval None.
288 */
QDEC_SetPCC(QDEC_TypeDef * QDec,u32 CmpPC)289 void QDEC_SetPCC(QDEC_TypeDef *QDec, u32 CmpPC)
290 {
291 u32 reg_mpc;
292
293 assert_param(IS_QDEC_ALL_PERIPH(QDec));
294 assert_param(CmpPC <= 0xffff);
295
296 reg_mpc = QDec->QDEC_MPC;
297 reg_mpc &= ~QD_CMP_PC;
298 reg_mpc |= (CmpPC << 16);
299 QDec->QDEC_MPC = reg_mpc;
300 }
301
302 /**
303 * @brief Set Qdecoder max position counter.
304 * @param QDec: selected Qdec peripheral.
305 * @param MaxPC: compare rotation counter value.
306 * @retval None.
307 */
QDEC_SetMPC(QDEC_TypeDef * QDec,u32 MaxPC)308 void QDEC_SetMPC(QDEC_TypeDef *QDec, u32 MaxPC)
309 {
310 u32 reg_mpc;
311
312 assert_param(IS_QDEC_ALL_PERIPH(QDec));
313 assert_param(MaxPC <= 0xffff);
314
315 reg_mpc = QDec->QDEC_MPC;
316 reg_mpc &= ~QD_MAX_PC;
317 reg_mpc |= MaxPC;
318 QDec->QDEC_MPC = reg_mpc;
319 }
320
321 /**
322 * @brief Set Qdecoder rotation counter compare value.
323 * @param QDec: selected Qdec peripheral.
324 * @param CmpRC: compare rotation counter value.
325 * @retval None.
326 */
QDEC_SetRCC(QDEC_TypeDef * QDec,u32 CmpRC)327 void QDEC_SetRCC(QDEC_TypeDef *QDec, u32 CmpRC)
328 {
329 assert_param(IS_QDEC_ALL_PERIPH(QDec));
330 assert_param(CmpRC <= 0xfff);
331
332 QDec->QDEC_RC = CmpRC;
333 }
334
335 /**
336 * @brief Get Qdecoder rotation counter.
337 * @param QDec: selected Qdec peripheral.
338 * @retval Qdecoder current rotation counter.
339 */
QDEC_GetRC(QDEC_TypeDef * QDec)340 u32 QDEC_GetRC(QDEC_TypeDef *QDec)
341 {
342 assert_param(IS_QDEC_ALL_PERIPH(QDec));
343
344 return (((QDec->QDEC_PC) & QD_RC) >> 20);
345 }
346
347 /**
348 * @brief Get Qdecoder phase status.
349 * @param QDec: selected Qdec peripheral.
350 * @retval current phase status of PHA&PHB.
351 */
QDEC_GetPhase(QDEC_TypeDef * QDec)352 u32 QDEC_GetPhase(QDEC_TypeDef *QDec)
353 {
354 assert_param(IS_QDEC_ALL_PERIPH(QDec));
355
356 return (((QDec->QDEC_PC) & QD_PHASE_STATE) >> 18);
357 }
358
359 /**
360 * @brief Get Qdecoder movement direction.
361 * @param QDec: selected Qdec peripheral.
362 * @retval movement direction: 0 for decrease, 1 for increase.
363 */
QDEC_GetDir(QDEC_TypeDef * QDec)364 u32 QDEC_GetDir(QDEC_TypeDef *QDec)
365 {
366 assert_param(IS_QDEC_ALL_PERIPH(QDec));
367
368 return (((QDec->QDEC_PC) & QD_DIR_STATE) >> 16);
369 }
370
371 /**
372 * @brief Get Qdecoder position counter.
373 * @param QDec: selected Qdec peripheral.
374 * @retval Qdecoder current position counter.
375 */
QDEC_GetPC(QDEC_TypeDef * QDec)376 u32 QDEC_GetPC(QDEC_TypeDef *QDec)
377 {
378 assert_param(IS_QDEC_ALL_PERIPH(QDec));
379
380 return ((QDec->QDEC_PC) & QD_PC);
381
382 }
383
384 /**
385 * @brief Enables or disables the index pulse detection.
386 * @param QDec: selected Qdec peripheral.
387 * @param NewState: new state of the Qdecoder index detection.
388 * This parameter can be: ENABLE or DISABLE.
389 * @retval None.
390 */
QDEC_Idx_Cmd(QDEC_TypeDef * QDec,u32 NewState)391 void QDEC_Idx_Cmd(QDEC_TypeDef *QDec, u32 NewState)
392 {
393 assert_param(IS_QDEC_ALL_PERIPH(QDec));
394
395 if (NewState == ENABLE)
396 QDec->QDEC_ISC |= QD_IDX_EN;
397 else if (NewState == DISABLE)
398 QDec->QDEC_ISC &= ~QD_IDX_EN;
399 }
400
401 /**
402 * @brief QDec set position counter reset mode.
403 * @param QDec: selected Qdec peripheral.
404 * @param mode: reset function work mode,This parameter can be:
405 * QD_PC_RST_DISABLE: disable reset function.
406 * QD_PC_RST_ONCE : only reset on the 1st index pluse .
407 * QD_PC_RST_ALWAYS : always reset on the index pluse.
408 * @param phase: reset phase,This parameter can be:
409 * QD_PC_RST_AUTO_IDX: reset on the idx pluse edge.
410 * QD_PC_RST_PHASE_00: reset on phase 00 during index pluse.
411 * QD_PC_RST_PHASE_01: reset on phase 01 during index pluse.
412 * QD_PC_RST_PHASE_10: reset on phase 10 during index pluse.
413 * QD_PC_RST_PHASE_11: reset on phase 11 during index pluse.
414 * @retval None.
415 */
QDEC_SetRstMod(QDEC_TypeDef * QDec,u32 mode,u32 phase)416 void QDEC_SetRstMod(QDEC_TypeDef *QDec, u32 mode, u32 phase)
417 {
418 u32 reg_isc;
419
420 assert_param(IS_QDEC_ALL_PERIPH(QDec));
421 assert_param(IS_QD_PC_RST_MODE(mode));
422 assert_param(IS_QD_PC_RST_PHASE(phase));
423
424 reg_isc = QDec->QDEC_ISC;
425
426 reg_isc &= ~0x0000005B;
427 reg_isc |= mode;
428 reg_isc |= phase;
429
430 QDec->QDEC_ISC = reg_isc;
431 }
432
433 /**
434 * @brief Set velocity Timer duration.
435 * @param QDec: selected Qdec peripheral.
436 * @param duration: duration of one velocity measure unit.
437 * after the duration VC will be captured to VCCAP.
438 * @retval None.
439 */
QDEC_SetVTmr(QDEC_TypeDef * QDec,u32 duration)440 void QDEC_SetVTmr(QDEC_TypeDef *QDec, u32 duration)
441 {
442 u32 vt_div = 0;
443 u32 Temp = 0;
444 u32 vt_rld,sysclk;
445 assert_param(IS_QDEC_ALL_PERIPH(QDec));
446
447 Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_CLK_CTRL1);
448 if (Temp &= BIT_LSYS_QDEC0_CKSL32K) {
449 sysclk = QD_SYS_CLK_32K;
450 } else {
451 sysclk = QD_SYS_CLK_2M;
452 }
453
454 /*to avoid overflow*/
455 /*VTmr_rld =VTmr /(1000/SysClk) = VTmr*SysClk/1000 = Vtmr *(sysclk/1024)*/
456 vt_rld = duration *(sysclk/1000);
457 assert_param(vt_rld <= 0xFFFFFF);
458 while((vt_rld / (1+vt_div)) > 0xFFFF){
459 vt_div++;
460 }
461 vt_rld /= (vt_div+1);
462
463 QDec->QDEC_VCTRL &= ~QD_VT_DIV;
464 QDec->QDEC_VCTRL |= vt_div << 16;
465
466 QDec->QDEC_VTRLD = vt_rld;
467 }
468
469 /**
470 * @brief Set velocity counter mode.
471 * @param QDec: selected Qdec peripheral.
472 * @param mode: This parameter can be one of the following values:
473 * @arg QD_VC_MOD_ABS: velocity conter use absolute value of position counter.
474 * @arg QD_VC_MOD_PC: velocity counter use same vaule of position counter.
475 * @retval None.
476 */
QDEC_SetVcMod(QDEC_TypeDef * QDec,u32 mode)477 void QDEC_SetVcMod(QDEC_TypeDef *QDec, u32 mode)
478 {
479 assert_param(IS_QDEC_ALL_PERIPH(QDec));
480 assert_param(IS_QD_VC_MODE(mode));
481
482 QDec->QDEC_VCTRL &= ~QD_VMUC_MOD;
483 QDec->QDEC_VCTRL |= mode;
484 }
485
486 /**
487 * @brief Enables or disables the specified Qdecoder velocity function.
488 * @param QDec: selected Qdec peripheral.
489 * @param NewState: new state of the Qdecoder velocity function.
490 * This parameter can be: ENABLE or DISABLE.
491 * @retval None.
492 */
QDEC_VT_Cmd(QDEC_TypeDef * QDec,u32 NewState)493 void QDEC_VT_Cmd(QDEC_TypeDef *QDec, u32 NewState)
494 {
495 assert_param(IS_QDEC_ALL_PERIPH(QDec));
496
497 if (NewState == ENABLE)
498 QDec->QDEC_VCTRL |= QD_VMUC_EN;
499 else if (NewState == DISABLE)
500 QDec->QDEC_VCTRL &= ~QD_VMUC_EN;
501 }
502
503 /**
504 * @brief Reset velocity timer and.
505 * @param QDec: selected Qdec peripheral.
506 * @retval None.
507 */
QDEC_VtRst(QDEC_TypeDef * QDec)508 void QDEC_VtRst(QDEC_TypeDef *QDec)
509 {
510 u32 reg_vctrl;
511 assert_param(IS_QDEC_ALL_PERIPH(QDec));
512
513 reg_vctrl = QDec->QDEC_VCTRL;
514 QDec->QDEC_VCTRL &= ~QD_VMUC_EN;
515 /*hw clock issue ,may can not sample VMUC Disable*/
516 DelayUs(500);
517
518 QDec->QDEC_VCTRL |= QD_VMUC_RST;
519 QDec->QDEC_VCTRL &= ~QD_VMUC_RST;
520
521 QDec->QDEC_VCTRL = reg_vctrl;
522
523 }
524
525 /**
526 * @brief Set Qdec velocity counter up limit value.
527 * @param QDec: selected Qdec peripheral.
528 * @param limt: the limited value to be setting.
529 * @retval None.
530 */
QDEC_SetVcUpLmt(QDEC_TypeDef * QDec,u32 limt)531 void QDEC_SetVcUpLmt(QDEC_TypeDef *QDec, u32 limt)
532 {
533 assert_param(IS_QDEC_ALL_PERIPH(QDec));
534 assert_param(limt <= 0xffff);
535
536 QDec->QDEC_VCOMP &= ~QD_VUP_LMT;
537 QDec->QDEC_VCOMP |= limt << 16;
538 }
539
540 /**
541 * @brief Set Qdec velocity counter low limit value.
542 * @param QDec: selected Qdec peripheral.
543 * @param limt: the limited value to be setting.
544 * @retval None.
545 */
QDEC_SetVcLowLmt(QDEC_TypeDef * QDec,u32 limt)546 void QDEC_SetVcLowLmt(QDEC_TypeDef *QDec, u32 limt)
547 {
548 assert_param(IS_QDEC_ALL_PERIPH(QDec));
549 assert_param(limt <= 0xffff);
550
551 QDec->QDEC_VCOMP &= ~QD_VLOW_LMT;
552 QDec->QDEC_VCOMP |= limt;
553 }
554
555 /**
556 * @brief Get Qdec velocity Timer value.
557 * @param QDec: selected Qdec peripheral.
558 * @retval velocity timerr value.
559 */
QDEC_GetVT(QDEC_TypeDef * QDec)560 u32 QDEC_GetVT(QDEC_TypeDef *QDec)
561 {
562 assert_param(IS_QDEC_ALL_PERIPH(QDec));
563
564 return QDec->QDEC_VT;
565 }
566
567 /**
568 * @brief Get Qdec velocity counter value.
569 * @param QDec: selected Qdec peripheral.
570 * @retval velocity counter value.
571 */
QDEC_GetVC(QDEC_TypeDef * QDec)572 u32 QDEC_GetVC(QDEC_TypeDef *QDec)
573 {
574 assert_param(IS_QDEC_ALL_PERIPH(QDec));
575
576 return QDec->QDEC_VC;
577 }
578
579 /**
580 * @brief Get Qdec velocity counter capture value.
581 * @param QDec: selected Qdec peripheral.
582 * @retval velocity counter capture value.
583 */
QDEC_GetVCCAP(QDEC_TypeDef * QDec)584 u32 QDEC_GetVCCAP(QDEC_TypeDef *QDec)
585 {
586 assert_param(IS_QDEC_ALL_PERIPH(QDec));
587
588 return QDec->QDEC_VCCAP;
589 }
590
591 /**
592 * @brief Get Qdec position counter capture value.
593 * @param QDec: selected Qdec peripheral.
594 * @retval positon counter capture value.
595 */
QDEC_GetPCCAP(QDEC_TypeDef * QDec)596 u32 QDEC_GetPCCAP(QDEC_TypeDef *QDec)
597 {
598 assert_param(IS_QDEC_ALL_PERIPH(QDec));
599
600 return QDec->QDEC_PCCAP;
601 }
602
603
604 /**
605 * @brief Enables or disables the specified QDec interrupts.
606 * @param QDec: selected Qdec peripheral.
607 * @param INT: specifies the QDec interrupts sources to be enabled or disabled.
608 * This parameter can be the following values:
609 * @arg QD_RC_CMP_INT_EN: Qdecoder rotation counter compare INT enable.
610 * @arg QD_VUPLMT_INT_EN: Qdecoder Velocity up limit interrupt enable.
611 * @arg QD_VLOWLMT_INT_EN: Qdecoder Velocity low limit interrupt enable.
612 * @arg QD_VCCAP_INT_EN: Qdecoder Velocity counter capture interrupt enable.
613 * @arg QD_PC_ERR_INT_EN: Qdecoder position counter error INT enable.
614 * @arg QD_IDX_PULSE_INT_EN: Qdecoder index pulse INT enable.
615 * @arg QD_RC_UF_INT_EN: Qdecoder rotation counter underflow INT enable.
616 * @arg QD_RC_OF_INT_EN: Qdecoder rotation counter overflow INT enable.
617 * @arg QD_PC_CMP_INT_EN: Qdecoder position counter compare INT enable.
618 * @arg QD_DR_CH_INT_EN: Qdecoder direction changed INT enable.
619 * @arg QD_PHASE_ILL_INT_EN: Qdecoder phase changed illegal INT enable.
620 * @arg QD_PC_UF_INT_EN: Qdecoder position counter underflow INT enable.
621 * @arg QD_PC_OF_INT_EN: Qdecoder position counter overflow INT enable.
622 * @arg QD_PC_CHG_INT_EN: Qdecoder position counter changed INT enable.
623 * @param NewState: new state of the specified QDecinterrupts.
624 * This parameter can be: ENABLE or DISABLE.
625 * @retval None.
626 */
QDEC_INTConfig(QDEC_TypeDef * QDec,u32 INT,u32 newState)627 void QDEC_INTConfig(QDEC_TypeDef *QDec, u32 INT, u32 newState)
628 {
629 u32 velocity_int,counter_int;
630
631 assert_param(IS_QDEC_ALL_PERIPH(QDec));
632
633 counter_int = INT & QD_COUNTER_INT;
634 velocity_int = INT & QD_VELOCITY_INT;
635
636 if (newState == ENABLE) {
637 QDec->QDEC_CTRL |= counter_int;
638 QDec->QDEC_VCTRL |= velocity_int;
639 }else if (newState == DISABLE) {
640 QDec->QDEC_CTRL &= ~counter_int;
641 QDec->QDEC_VCTRL &= ~velocity_int;
642 }
643 }
644
645 /**
646 * @brief Mask or unmask the specified QDec interrupts.
647 * @param QDec: selected Qdec peripheral.
648 * @param mask: specifies the Qdec interrupts sources to be mask or unmask.
649 * This parameter can be one or combinations of the following values:
650 * @arg QD_RC_COMP_INT_MASK: Qdecoder rotation counter compare INT mask.
651 * @arg QD_VUPLMT_INT_MASK: Qdecoder Velocity up limit interrupt mask.
652 * @arg QD_VLOWLMT_INT_MASK: Qdecoder Velocity low limit interrupt mask.
653 * @arg QD_VCCAP_INT_MASK: Qdecoder Velocity counter capture interrupt mask.
654 * @arg QD_PC_ERR_INT_MASK: Qdecoder position counter error INT mask.
655 * @arg QD_IDX_PULSE_INT_MASK: Qdecoder index pulse INT mask.
656 * @arg QD_RC_UF_INT_MASK: Qdecoder rotation counter underflow INT mask.
657 * @arg QD_RC_OF_INT_MASK: Qdecoder rotation counter overflow INT mask.
658 * @arg QD_PC_CMP_INT_MASK: Qdecoder position counter compare INT mask.
659 * @arg QD_DR_CH_INT_MASK: Qdecoder direction changed INT mask.
660 * @arg QD_PHASE_ILL_INT_MASK: Qdecoder phase changed illegal INT mask.
661 * @arg QD_PC_UF_INT_MASK: Qdecoder position counter underflow INT mask.
662 * @arg QD_PC_OF_INT_MASK: Qdecoder position counter overflow INT mask.
663 * @arg QD_PC_CHG_INT_MASK: Qdecoder position counter changed INT mask.
664 * @param NewState: new state of the specified QDec interrupts.
665 * This parameter can be: ENABLE or DISABLE.
666 * @retval None.
667 */
QDEC_INTMask(QDEC_TypeDef * QDec,u32 mask,u32 newState)668 void QDEC_INTMask(QDEC_TypeDef *QDec, u32 mask, u32 newState)
669 {
670
671 assert_param(IS_QDEC_ALL_PERIPH(QDec));
672 assert_param((mask & (~QD_ALL_INT_MASK)) == 0);
673
674 if (newState == ENABLE)
675 QDec->QDEC_IMR |= mask;
676 else if (newState == DISABLE)
677 QDec->QDEC_IMR &= ~mask;
678 }
679
680 /**
681 * @brief Clear the specified QDec interrupts.
682 * @param QDec: selected Qdec peripheral.
683 * @param INT: specifies the Qdec interrupts sources to be clear.
684 * This parameter can be one or combinations of the following values:
685 * @arg QD_RC_COMP_INT_STATUS: Qdecoder rotation counter compare INT status.
686 * @arg QD_VUPLMT_INT_STATUS: Qdecoder Velocity up limit interrupt status.
687 * @arg QD_VLOWLMT_INT_STATUS: Qdecoder Velocity low limit interrupt status.
688 * @arg QD_VCCAP_INT_STATUS: Qdecoder Velocity counter capture interrupt status.
689 * @arg QD_PC_ERR_INT_STATUS: Qdecoder position counter error INT status.
690 * @arg QD_IDX_PULSE_INT_STATUS: Qdecoder index pulse INT status.
691 * @arg QD_RC_UF_INT_STATUS: Qdecoder rotation counter underflow INT status.
692 * @arg QD_RC_OF_INT_STATUS: Qdecoder rotation counter overflow INT status.
693 * @arg QD_PC_CMP_INT_STATUS: Qdecoder position counter compare INT status.
694 * @arg QD_DR_CH_INT_STATUS: Qdecoder direction changed INT status.
695 * @arg QD_PHASE_ILL_INT_STATUS: Qdecoder phase changed illegal INT status.
696 * @arg QD_PC_UF_INT_STATUS: Qdecoder position counter underflow INT status.
697 * @arg QD_PC_OF_INT_STATUS: Qdecoder position counter overflow INT status.
698 * @arg QD_PC_CHG_INT_STATUS: Qdecoder position counter changed INT status.
699 * @retval None
700 */
QDEC_ClearINT(QDEC_TypeDef * QDec,u32 INT)701 void QDEC_ClearINT(QDEC_TypeDef *QDec, u32 INT)
702 {
703
704 assert_param(IS_QDEC_ALL_PERIPH(QDec));
705 assert_param((INT & (~QD_ALL_INT_STATUS)) == 0);
706
707 QDec->QDEC_ISR |= INT;
708 }
709
710 /**
711 * @brief Get the specified QDec interrupt status.
712 * @param QDec: selected Qdec peripheral.
713 * @retval The new state of IR_INT (SET or RESET).
714 */
QDEC_GetRawINT(QDEC_TypeDef * QDec)715 u32 QDEC_GetRawINT(QDEC_TypeDef *QDec)
716 {
717 assert_param(IS_QDEC_ALL_PERIPH(QDec));
718
719 return QDec->QDEC_ISR;
720 }
721
722 /**
723 * @brief Get the specified QDec interrupt mask status.
724 * @param QDec: selected Qdec peripheral.
725 * @retval The mask state of IR_INT (SET or RESET).
726 */
QDEC_GetIMR(QDEC_TypeDef * QDec)727 u32 QDEC_GetIMR(QDEC_TypeDef *QDec)
728 {
729 assert_param(IS_QDEC_ALL_PERIPH(QDec));
730
731 return QDec->QDEC_IMR;
732 }
733
734 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor Corporation *****END OF FILE****/
735