1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2016, GlobalLogic 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef PLATFORM_CONFIG_H 30 #define PLATFORM_CONFIG_H 31 32 #include <mm/generic_ram_layout.h> 33 34 #define RCAR_CACHE_LINE_SZ 64 35 36 /* Make stacks aligned to data cache line length */ 37 #define STACK_ALIGNMENT RCAR_CACHE_LINE_SZ 38 39 #if defined(CFG_RCAR_GEN3) 40 41 #define GIC_BASE 0xF1000000 42 #define GICC_BASE 0xF1020000 43 #define GICD_BASE 0xF1010000 44 45 #define CONSOLE_UART_BASE 0xE6E88000 46 47 #define PRR_BASE 0xFFF00000 48 49 #elif defined(CFG_RCAR_GEN4) 50 51 #define GICC_BASE 0xF1060000 52 #define GICD_BASE 0xF1000000 53 54 #if CFG_RCAR_UART == 103 /* SCIF3 */ 55 #define CONSOLE_UART_BASE 0xE6C50000 56 #elif CFG_RCAR_UART == 200 /* HSCIF0 */ 57 #define CONSOLE_UART_BASE 0xE6540000 58 #endif 59 60 #endif /* CFG_RCAR_GENx */ 61 62 #if defined(PLATFORM_FLAVOR_salvator_h3) 63 #define NSEC_DDR_0_BASE 0x47E00000 64 #define NSEC_DDR_0_SIZE 0x38200000 65 #define NSEC_DDR_1_BASE 0x500000000U 66 #define NSEC_DDR_1_SIZE 0x40000000 67 #define NSEC_DDR_2_BASE 0x600000000U 68 #define NSEC_DDR_2_SIZE 0x40000000 69 #define NSEC_DDR_3_BASE 0x700000000U 70 #define NSEC_DDR_3_SIZE 0x40000000 71 72 #elif defined(PLATFORM_FLAVOR_salvator_h3_4x2g) 73 #define NSEC_DDR_0_BASE 0x47E00000 74 #define NSEC_DDR_0_SIZE 0x78200000 75 #define NSEC_DDR_1_BASE 0x500000000U 76 #define NSEC_DDR_1_SIZE 0x80000000 77 #define NSEC_DDR_2_BASE 0x600000000U 78 #define NSEC_DDR_2_SIZE 0x80000000 79 #define NSEC_DDR_3_BASE 0x700000000U 80 #define NSEC_DDR_3_SIZE 0x80000000 81 82 #elif defined(PLATFORM_FLAVOR_salvator_m3) 83 #define NSEC_DDR_0_BASE 0x47E00000 84 #define NSEC_DDR_0_SIZE 0x78200000 85 #define NSEC_DDR_1_BASE 0x600000000U 86 #define NSEC_DDR_1_SIZE 0x80000000 87 88 #elif defined(PLATFORM_FLAVOR_salvator_m3_2x4g) 89 #define NSEC_DDR_0_BASE 0x47E00000 90 #define NSEC_DDR_0_SIZE 0x78200000 91 #define NSEC_DDR_1_BASE 0x480000000U 92 #define NSEC_DDR_1_SIZE 0x80000000 93 #define NSEC_DDR_2_BASE 0x600000000U 94 #define NSEC_DDR_2_SIZE 0x100000000U 95 96 #elif defined(PLATFORM_FLAVOR_spider_s4) 97 #define NSEC_DDR_0_BASE 0x48000000 98 #define NSEC_DDR_0_SIZE 0x78000000 99 #define NSEC_DDR_1_BASE 0x480000000U 100 #define NSEC_DDR_1_SIZE 0x80000000U 101 102 #else 103 104 /* Generic DT-based platform */ 105 106 #endif 107 108 /* Full GlobalPlatform test suite requires TEE_SHMEM_SIZE to be at least 2MB */ 109 #define TEE_SHMEM_START (TZDRAM_BASE + TZDRAM_SIZE) 110 #define TEE_SHMEM_SIZE 0x100000 111 112 #endif /*PLATFORM_CONFIG_H*/ 113