1 /* 2 * Renesas SCP/MCP Software 3 * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights 4 * reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef RCAR_DEF_H 10 #define RCAR_DEF_H 11 12 /* Reset */ 13 #define RCAR_CPGWPR UINT32_C(0xE6150900) /* CPG write protect */ 14 #define RCAR_MODEMR UINT32_C(0xE6160060) /* Mode pin */ 15 #define RCAR_CA57RESCNT UINT32_C(0xE6160040) /* Reset control A57 */ 16 #define RCAR_CA53RESCNT UINT32_C(0xE6160044) /* Reset control A53 */ 17 #define RCAR_SRESCR UINT32_C(0xE6160110) /* Soft Power On Reset */ 18 #define RCAR_CA53WUPCR UINT32_C(0xE6151010) /* Wake-up control A53 */ 19 #define RCAR_CA57WUPCR UINT32_C(0xE6152010) /* Wake-up control A57 */ 20 #define RCAR_CA53PSTR UINT32_C(0xE6151040) /* Power status A53 */ 21 #define RCAR_CA57PSTR UINT32_C(0xE6152040) /* Power status A57 */ 22 #define RCAR_CA53CPU0CR UINT32_C(0xE6151100) /* CPU control A53 */ 23 #define RCAR_CA57CPU0CR UINT32_C(0xE6152100) /* CPU control A57 */ 24 #define RCAR_CA53CPUCMCR UINT32_C(0xE6151184) /* Common power A53 */ 25 #define RCAR_CA57CPUCMCR UINT32_C(0xE6152184) /* Common power A57 */ 26 #define RCAR_WUPMSKCA57 UINT32_C(0xE6180014) /* Wake-up mask A57 */ 27 #define RCAR_WUPMSKCA53 UINT32_C(0xE6180018) /* Wake-up mask A53 */ 28 29 /* SYSC */ 30 #define RCAR_PWRSR3 UINT32_C(0xE6180140) /* Power stat A53-SCU */ 31 #define RCAR_PWRSR5 UINT32_C(0xE61801C0) /* Power stat A57-SCU */ 32 #define RCAR_SYSCIER UINT32_C(0xE618000C) /* Interrupt enable */ 33 #define RCAR_SYSCIMR UINT32_C(0xE6180010) /* Interrupt mask */ 34 #define RCAR_SYSCSR UINT32_C(0xE6180000) /* SYSC status */ 35 #define RCAR_PWRONCR3 UINT32_C(0xE618014C) /* Power resume A53-SCU */ 36 #define RCAR_PWRONCR5 UINT32_C(0xE61801CC) /* Power resume A57-SCU */ 37 #define RCAR_PWROFFCR3 UINT32_C(0xE6180144) /* Power shutof A53-SCU */ 38 #define RCAR_PWROFFCR5 UINT32_C(0xE61801C4) /* Power shutof A57-SCU */ 39 #define RCAR_PWRER3 UINT32_C(0xE6180154) /* shutoff/resume error */ 40 #define RCAR_PWRER5 UINT32_C(0xE61801D4) /* shutoff/resume error */ 41 #define RCAR_SYSCISR UINT32_C(0xE6180004) /* Interrupt status */ 42 #define RCAR_SYSCISCR UINT32_C(0xE6180008) /* Interrupt stat clear */ 43 44 /* Product register */ 45 #define RCAR_PRR UINT32_C(0xFFF00044) 46 #define RCAR_PRODUCT_MASK UINT32_C(0x00007F00) 47 #define RCAR_CUT_MASK UINT32_C(0x000000FF) 48 #define RCAR_PRODUCT_H3 UINT32_C(0x00004F00) 49 #define RCAR_PRODUCT_M3 UINT32_C(0x00005200) 50 #define RCAR_PRODUCT_M3N UINT32_C(0x00005500) 51 #define RCAR_PRODUCT_E3 UINT32_C(0x00005700) 52 #define RCAR_CUT_VER10 UINT32_C(0x00000000) 53 #define RCAR_CUT_VER11 UINT32_C(0x00000001) /* H3/M3N/E3 Ver.1.1 */ 54 #define RCAR_M3_CUT_VER11 UINT32_C(0x00000010) /* M3 Ver.1.1/Ver.1.2 */ 55 #define RCAR_CUT_VER20 UINT32_C(0x00000010) 56 #define RCAR_CUT_VER30 UINT32_C(0x00000020) 57 #define RCAR_MAJOR_MASK UINT32_C(0x000000F0) 58 #define RCAR_MINOR_MASK UINT32_C(0x0000000F) 59 #define RCAR_PRODUCT_SHIFT UINT32_C(8) 60 #define RCAR_MAJOR_SHIFT UINT32_C(4) 61 #define RCAR_MINOR_SHIFT UINT32_C(0) 62 #define RCAR_MAJOR_OFFSET UINT32_C(1) 63 #define RCAR_M3_MINOR_OFFSET UINT32_C(2) 64 #define RCAR_PRODUCT_H3_CUT10 (RCAR_PRODUCT_H3 | UINT32_C(0x00)) /* 1.0 */ 65 #define RCAR_PRODUCT_H3_CUT11 (RCAR_PRODUCT_H3 | UINT32_C(0x01)) /* 1.1 */ 66 #define RCAR_PRODUCT_H3_CUT20 (RCAR_PRODUCT_H3 | UINT32_C(0x10)) /* 2.0 */ 67 #define RCAR_PRODUCT_M3_CUT10 (RCAR_PRODUCT_M3 | UINT32_C(0x00)) /* 1.0 */ 68 #define RCAR_PRODUCT_M3_CUT11 (RCAR_PRODUCT_M3 | UINT32_C(0x10)) 69 #define RCAR_CPU_MASK_CA57 UINT32_C(0x80000000) 70 #define RCAR_CPU_MASK_CA53 UINT32_C(0x04000000) 71 #define RCAR_CPU_HAVE_CA57 UINT32_C(0x00000000) 72 #define RCAR_CPU_HAVE_CA53 UINT32_C(0x00000000) 73 #define RCAR_SSCG_MASK UINT32_C(0x1000) /* MD12 */ 74 #define RCAR_SSCG_ENABLE UINT32_C(0x1000) 75 76 /* MD pin information */ 77 #define MODEMR_BOOT_PLL_MASK UINT32_C(0x00006000) 78 #define MODEMR_BOOT_PLL_SHIFT UINT32_C(13) 79 /* MODEMR PLL masks and bitfield values */ 80 #define CHECK_MD13_MD14 UINT32_C(0x6000) 81 #define MD14_MD13_TYPE_0 UINT32_C(0x0000) /* MD14=0 MD13=0 */ 82 #define MD14_MD13_TYPE_1 UINT32_C(0x2000) /* MD14=0 MD13=1 */ 83 #define MD14_MD13_TYPE_2 UINT32_C(0x4000) /* MD14=1 MD13=0 */ 84 #define MD14_MD13_TYPE_3 UINT32_C(0x6000) /* MD14=1 MD13=1 */ 85 /* Frequency of EXTAL(Hz) */ 86 #define EXTAL_MD14_MD13_TYPE_0 UINT32_C(8333300) /* MD14=0 MD13=0 */ 87 #define EXTAL_MD14_MD13_TYPE_1 UINT32_C(10000000) /* MD14=0 MD13=1 */ 88 #define EXTAL_MD14_MD13_TYPE_2 UINT32_C(12500000) /* MD14=1 MD13=0 */ 89 #define EXTAL_MD14_MD13_TYPE_3 UINT32_C(16666600) /* MD14=1 MD13=1 */ 90 #define EXTAL_SALVATOR_XS UINT32_C(8320000) /* Salvator-XS */ 91 #define EXTAL_EBISU UINT32_C(24000000) /* Ebisu */ 92 93 /* CPG Secure Module Stop Control Register 9 */ 94 #define SCMSTPCR9 (CPG_BASE + 0x0B44U) 95 /* CPG stop status 9 */ 96 #define CPG_MSTPSR9 (CPG_BASE + 0x09A4U) 97 98 #endif /* RCAR_DEF_H */ 99