1 /******************************************************************************
2 * Filename: aon_wuc.h
3 * Revised: 2015-07-16 12:12:04 +0200 (Thu, 16 Jul 2015)
4 * Revision: 44151
5 *
6 * Description: Defines and prototypes for the AON Wake-Up Controller
7 *
8 * Copyright (c) 2015, Texas Instruments Incorporated
9 * All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions are met:
13 *
14 * 1) Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 *
17 * 2) Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 *
21 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may
22 * be used to endorse or promote products derived from this software without
23 * specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 *
37 ******************************************************************************/
38
39 //*****************************************************************************
40 //
41 //! \addtogroup aon_group
42 //! @{
43 //! \addtogroup aonwuc_api
44 //! @{
45 //
46 //*****************************************************************************
47
48 #ifndef __AON_WUC_H__
49 #define __AON_WUC_H__
50
51 //*****************************************************************************
52 //
53 // If building with a C++ compiler, make all of the definitions in this header
54 // have a C binding.
55 //
56 //*****************************************************************************
57 #ifdef __cplusplus
58 extern "C"
59 {
60 #endif
61
62 #include <stdbool.h>
63 #include <stdint.h>
64 #include <inc/hw_types.h>
65 #include <inc/hw_memmap.h>
66 #include <inc/hw_ints.h>
67 #include <inc/hw_aon_wuc.h>
68 #include <inc/hw_aon_rtc.h>
69 #include <driverlib/interrupt.h>
70 #include <driverlib/debug.h>
71
72 //*****************************************************************************
73 //
74 // Support for DriverLib in ROM:
75 // This section renames all functions that are not "static inline", so that
76 // calling these functions will default to implementation in flash. At the end
77 // of this file a second renaming will change the defaults to implementation in
78 // ROM for available functions.
79 //
80 // To force use of the implementation in flash, e.g. for debugging:
81 // - Globally: Define DRIVERLIB_NOROM at project level
82 // - Per function: Use prefix "NOROM_" when calling the function
83 //
84 //*****************************************************************************
85 #if !defined(DOXYGEN)
86 #define AONWUCAuxReset NOROM_AONWUCAuxReset
87 #define AONWUCRechargeCtrlConfigSet NOROM_AONWUCRechargeCtrlConfigSet
88 #define AONWUCOscConfig NOROM_AONWUCOscConfig
89 #endif
90
91 //*****************************************************************************
92 //
93 // Defines the possible clock source for the MCU and AUX domain.
94 //
95 //*****************************************************************************
96 #define AONWUC_CLOCK_SRC_HF 0x00000003 // System clock high frequency -
97 // 48 MHz.
98 #define AONWUC_CLOCK_SRC_LF 0x00000001 // System clock low frequency -
99 // 32 kHz.
100 #define AONWUC_NO_CLOCK 0x00000000 // System clock low frequency -
101 // 32 kHz.
102
103 //*****************************************************************************
104 //
105 // Defines the possible clock division factors for the AUX domain.
106 //
107 //*****************************************************************************
108 #define AUX_CLOCK_DIV_2 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV2 )
109 #define AUX_CLOCK_DIV_4 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV4 )
110 #define AUX_CLOCK_DIV_8 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV8 )
111 #define AUX_CLOCK_DIV_16 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV16 )
112 #define AUX_CLOCK_DIV_32 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV32 )
113 #define AUX_CLOCK_DIV_64 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV64 )
114 #define AUX_CLOCK_DIV_128 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV128 )
115 #define AUX_CLOCK_DIV_256 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV256 )
116 #define AUX_CLOCK_DIV_UNUSED ( AON_WUC_AUXCLK_SCLK_HF_DIV_M + ( 1 << AON_WUC_AUXCLK_SCLK_HF_DIV_S ))
117 #define AUX_CLOCK_DIV_M ( AON_WUC_AUXCLK_SCLK_HF_DIV_M )
118
119 //*****************************************************************************
120 //
121 // Defines used for configuring the power-off and wake up procedure.
122 //
123 //*****************************************************************************
124 #define MCU_VIRT_PWOFF_DISABLE 0x00000000
125 #define MCU_VIRT_PWOFF_ENABLE 0x00020000
126 #define MCU_IMM_WAKE_UP 0x00000000
127 #define MCU_FIXED_WAKE_UP 0x00010000
128 #define AUX_VIRT_PWOFF_DISABLE 0x00000000
129 #define AUX_VIRT_PWOFF_ENABLE 0x00020000
130 #define AUX_IMM_WAKE_UP 0x00000000
131 #define AUX_FIXED_WAKE_UP 0x00010000
132
133 //*****************************************************************************
134 //
135 // Defines that can be be used to enable/disable the entire SRAM and the
136 // retention on the SRAM in both the MCU and the AUX domain.
137 //
138 //*****************************************************************************
139 #define MCU_RAM0_RETENTION 0x00000001
140 #define MCU_RAM1_RETENTION 0x00000002
141 #define MCU_RAM2_RETENTION 0x00000004
142 #define MCU_RAM3_RETENTION 0x00000008
143 #define MCU_RAM_BLOCK_RETENTION 0x0000000F
144 #define MCU_AUX_RET_ENABLE 0x00000001
145
146 //*****************************************************************************
147 //
148 // Defines for different wake up modes for AUX domain which can be set using
149 // AONWUCAuxWakeUpEvent() .
150 //
151 //*****************************************************************************
152 #define AONWUC_AUX_WAKEUP 0x00000001
153 #define AONWUC_AUX_ALLOW_SLEEP 0x00000000
154
155 //*****************************************************************************
156 //
157 // Defines for all the different power modes available through
158 // AONWUCPowerStatusGet() .
159 //
160 //*****************************************************************************
161 #define AONWUC_OSC_GBIAS_REQ 0x00400000 // OSC is requesting GBias
162 #define AONWUC_AUX_GBIAS_REQ 0x00200000 // AUX is requesting GBias
163 #define AONWUC_MCU_GBIAS_REQ 0x00100000 // MCU is requesting GBias
164 #define AONWUC_OSC_BGAP_REQ 0x00040000 // OSC is requesting BGap
165 #define AONWUC_AUX_BGAP_REQ 0x00020000 // AUX is requesting BGap
166 #define AONWUC_MCU_BGAP_REQ 0x00010000 // MCU is requesting BGap
167 #define AONWUC_GBIAS_ON 0x00002000 // Global Bias is on
168 #define AONWUC_BGAP_ON 0x00001000 // Band Gap is on
169 #define AONWUC_AUX_POWER_DOWN 0x00000200 // AUX is in powerdown mode
170 #define AONWUC_MCU_POWER_DOWN 0x00000100 // MCU is in powerdown mode
171 #define AONWUC_JTAG_POWER_ON 0x00000040 // JTAG is powered on
172 #define AONWUC_AUX_POWER_ON 0x00000020 // AUX is powered on
173 #define AONWUC_MCU_POWER_ON 0x00000010 // MCU is powered on
174 #define AONWUC_SPLY_POWER_DOWN 0x00000001 // Power supply is in power down
175
176
177 //*****************************************************************************
178 //
179 // RAM repair status bits. Values are returned by AOXWUCRamRepairStatusGet() .
180 //
181 //*****************************************************************************
182 #define MCU_RAMREPAIR_DONE 0x00000001
183 #define AUX_RAMREPAIR_DONE 0x00000002
184
185 //*****************************************************************************
186
187 //*****************************************************************************
188 #define RC_RATE_MAX 768 // Maximum recharge rate for the
189 // recharge controller.
190 #define RC_RATE_MIN 2 // Minimum recharge rate for the
191 // recharge controller.
192
193 //*****************************************************************************
194 #define AONWUC_MCU_RESET_SRC 0x00000002 // MCU reset source can be SW or
195 // JTAG
196 #define AONWUC_MCU_WARM_RESET 0x00000001 // MCU reset type and can be warm
197 // or not warm.
198
199 //*****************************************************************************
200 //
201 // API Functions and prototypes
202 //
203 //*****************************************************************************
204
205 //*****************************************************************************
206 //
207 //! \brief Configure the power down clock for the MCU domain.
208 //!
209 //! Use this function to control which one of the clock sources that
210 //! is fed into the MCU domain when the system is in standby mode. When the
211 //! power is back in Active mode the clock source will automatically switch to
212 //! \ref AONWUC_CLOCK_SRC_HF.
213 //!
214 //! Each clock is fed 'as is' into the MCU domain, since the MCU domain
215 //! contains internal clock dividers controllable through the PRCM.
216 //!
217 //! \param ui32ClkSrc is the clock source for the MCU domain when in power
218 //! down. Values available as clock source:
219 //! - \ref AONWUC_NO_CLOCK
220 //! - \ref AONWUC_CLOCK_SRC_LF
221 //!
222 //! \return None
223 //
224 //*****************************************************************************
225 __STATIC_INLINE void
AONWUCMcuPowerDownConfig(uint32_t ui32ClkSrc)226 AONWUCMcuPowerDownConfig(uint32_t ui32ClkSrc)
227 {
228 uint32_t ui32Reg;
229
230 //
231 // Check the arguments.
232 //
233 ASSERT((ui32ClkSrc == AONWUC_NO_CLOCK) ||
234 (ui32ClkSrc == AONWUC_CLOCK_SRC_LF));
235
236 //
237 // Set the clock source for the MCU domain when in power down.
238 //
239 ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_MCUCLK);
240 ui32Reg &= ~AON_WUC_MCUCLK_PWR_DWN_SRC_M;
241 HWREG(AON_WUC_BASE + AON_WUC_O_MCUCLK) = ui32Reg |
242 (ui32ClkSrc <<
243 AON_WUC_MCUCLK_PWR_DWN_SRC_S);
244 }
245
246 //*****************************************************************************
247 //
248 //! \brief Configure the power down mode for the MCU domain.
249 //!
250 //! The parameter \c ui32Mode determines the power down mode of the MCU Voltage
251 //! Domain. When the AON WUC receives a request to power off the MCU domain it
252 //! can choose to power off completely or use a virtual power-off. In a virtual
253 //! power-off, reset is asserted and the clock is stopped but the power to the
254 //! domain is kept on.
255 //!
256 //! \param ui32Mode defines the power down mode of the MCU domain.
257 //! Allowed values for setting the virtual power-off are:
258 //! - \ref MCU_VIRT_PWOFF_DISABLE
259 //! - \ref MCU_VIRT_PWOFF_ENABLE
260 //!
261 //! \return None
262 //
263 //*****************************************************************************
264 __STATIC_INLINE void
AONWUCMcuPowerOffConfig(uint32_t ui32Mode)265 AONWUCMcuPowerOffConfig(uint32_t ui32Mode)
266 {
267 // Check the arguments.
268 ASSERT((ui32Mode == MCU_VIRT_PWOFF_ENABLE) ||
269 (ui32Mode == MCU_VIRT_PWOFF_DISABLE));
270
271 // Set the powerdown mode.
272 HWREGBITW(AON_WUC_BASE + AON_WUC_O_MCUCFG, AON_WUC_MCUCFG_VIRT_OFF_BITN) = (ui32Mode != 0);
273 }
274
275 //*****************************************************************************
276 //
277 //! \brief Configure the wake-up procedure for the MCU domain.
278 //!
279 //! The MCU domain can wake up using two different procedures. Either it wakes
280 //! up immediately following the triggering event or wake-up is forced to
281 //! happen a fixed number of 32 KHz clocks following the triggering
282 //! event. The last can be used to compensate for any variable delays caused
283 //! by other activities going on at the time of wakeup (such as a recharge
284 //! event, etc.).
285 //!
286 //! \param ui32WakeUp determines the timing of the MCU wake up procedure.
287 //! - \ref MCU_IMM_WAKE_UP
288 //! - \ref MCU_FIXED_WAKE_UP
289 //!
290 //! \return None
291 //
292 //*****************************************************************************
293 __STATIC_INLINE void
AONWUCMcuWakeUpConfig(uint32_t ui32WakeUp)294 AONWUCMcuWakeUpConfig(uint32_t ui32WakeUp)
295 {
296 // Check the arguments.
297 ASSERT((ui32WakeUp == MCU_IMM_WAKE_UP) ||
298 (ui32WakeUp == MCU_FIXED_WAKE_UP));
299
300 // Configure the wake up procedure.
301 HWREGBITW(AON_WUC_BASE + AON_WUC_O_MCUCFG, AON_WUC_MCUCFG_FIXED_WU_EN_BITN) = (ui32WakeUp != 0);
302 }
303
304 //*****************************************************************************
305 //
306 //! \brief Configure the retention on the block RAM in the MCU domain.
307 //!
308 //! MCU SRAM is partitioned into 4 banks of 1k x 32 each. The SRAM supports
309 //! retention on all 4 blocks. The retention on the SRAM can be turned on and
310 //! off. Use this function to enable the retention on the individual blocks.
311 //!
312 //! If a block is not represented in the parameter \c ui32Retention then the
313 //! the retention will be disabled for that block.
314 //!
315 //! \note Retention on the SRAM is not enabled by default. If retention is
316 //! turned off on all RAM blocks then the SRAM is powered off when it would
317 //! otherwise be put in retention mode.
318 //!
319 //! \param ui32Retention defines which RAM blocks to enable/disable retention on.
320 //! To enable retention on individual parts of the RAM use a bitwise OR'ed
321 //! combination of:
322 //! - \ref MCU_RAM0_RETENTION
323 //! - \ref MCU_RAM1_RETENTION
324 //! - \ref MCU_RAM2_RETENTION
325 //! - \ref MCU_RAM3_RETENTION
326 //!
327 //! \return None
328 //
329 //*****************************************************************************
330 __STATIC_INLINE void
AONWUCMcuSRamConfig(uint32_t ui32Retention)331 AONWUCMcuSRamConfig(uint32_t ui32Retention)
332 {
333 uint32_t ui32Reg;
334
335 //
336 // Check the arguments.
337 //
338 ASSERT(ui32Retention & MCU_RAM_BLOCK_RETENTION);
339 ASSERT(!(ui32Retention & ~MCU_RAM_BLOCK_RETENTION));
340
341 //
342 // Configure the retention.
343 //
344 ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_MCUCFG) & ~MCU_RAM_BLOCK_RETENTION;
345 ui32Reg |= ui32Retention;
346 HWREG(AON_WUC_BASE + AON_WUC_O_MCUCFG) = ui32Reg;
347 }
348
349
350 //*****************************************************************************
351 //
352 //! \brief Return the clock configuration for the AUX domain.
353 //!
354 //! The AUX domain does not have a local clock divider, so the AON WUC contains
355 //! a dedicated clock divider for AUX domain. Use this function to
356 //! get the setting of the clock divider.
357 //!
358 //! \return Return the clock configuration. Enumerated return values are:
359 //! - \ref AUX_CLOCK_DIV_2
360 //! - \ref AUX_CLOCK_DIV_4
361 //! - \ref AUX_CLOCK_DIV_8
362 //! - \ref AUX_CLOCK_DIV_16
363 //! - \ref AUX_CLOCK_DIV_32
364 //! - \ref AUX_CLOCK_DIV_64
365 //! - \ref AUX_CLOCK_DIV_128
366 //! - \ref AUX_CLOCK_DIV_256
367 //!
368 //
369 //*****************************************************************************
370 __STATIC_INLINE uint32_t
AONWUCAuxClockConfigGet(void)371 AONWUCAuxClockConfigGet(void)
372 {
373 //
374 // Return the clock divider value.
375 //
376 return ((HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK) &
377 AON_WUC_AUXCLK_SCLK_HF_DIV_M) >>
378 AON_WUC_AUXCLK_SCLK_HF_DIV_S);
379 }
380
381 //*****************************************************************************
382 //
383 //! \brief Configure the power down mode for the AUX domain.
384 //!
385 //! Use this function to control which one of the clock sources that
386 //! is fed into the MCU domain when it is in Power Down mode. When the Power
387 //! is back in active mode the clock source will automatically switch to
388 //! \ref AONWUC_CLOCK_SRC_HF.
389 //!
390 //! Each clock is fed 'as is' into the AUX domain, since the AUX domain
391 //! contains internal clock dividers controllable through the PRCM.
392 //!
393 //! \param ui32ClkSrc is the clock source for the AUX domain when in power down.
394 //! - \ref AONWUC_NO_CLOCK
395 //! - \ref AONWUC_CLOCK_SRC_LF
396 //! \return None
397 //
398 //*****************************************************************************
399 __STATIC_INLINE void
AONWUCAuxPowerDownConfig(uint32_t ui32ClkSrc)400 AONWUCAuxPowerDownConfig(uint32_t ui32ClkSrc)
401 {
402 uint32_t ui32Reg;
403
404 //
405 // Check the arguments.
406 //
407 ASSERT((ui32ClkSrc == AONWUC_NO_CLOCK) ||
408 (ui32ClkSrc == AONWUC_CLOCK_SRC_LF));
409
410 //
411 // Set the clock source for the AUX domain when in power down.
412 //
413 ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK);
414 ui32Reg &= ~AON_WUC_AUXCLK_PWR_DWN_SRC_M;
415 HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK) = ui32Reg |
416 (ui32ClkSrc <<
417 AON_WUC_AUXCLK_PWR_DWN_SRC_S);
418 }
419
420
421 //*****************************************************************************
422 //
423 //! \brief Configure the retention on the AUX SRAM.
424 //!
425 //! The AUX SRAM contains only one block which supports retention. The retention
426 //! on the SRAM can be turned on and off. Use this function to enable/disable
427 //! the retention on the entire RAM.
428 //!
429 //! \param ui32Retention either enables or disables AUX SRAM retention.
430 //! - 0 : Disable retention.
431 //! - 1 : Enable retention.
432 //!
433 //! \note Retention on the SRAM is not enabled by default. If retention is
434 //! turned off then the SRAM is powered off when it would otherwise be put in
435 //! retention mode.
436 //!
437 //! \return None
438 //
439 //*****************************************************************************
440 __STATIC_INLINE void
AONWUCAuxSRamConfig(uint32_t ui32Retention)441 AONWUCAuxSRamConfig(uint32_t ui32Retention)
442 {
443 // Enable/disable the retention.
444 HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCFG, AON_WUC_AUXCFG_RAM_RET_EN_BITN) = ui32Retention;
445 }
446
447 //*****************************************************************************
448 //
449 //! \brief Control the wake up procedure of the AUX domain.
450 //!
451 //! The AUX domain can be woken in two different modes. In both modes power
452 //! is turned on. In one mode a software event is generated for the
453 //! Sensor Controller and it is allowed to start processing. The second mode will
454 //! just force power on the Sensor Controller. If System CPU requires exclusive access
455 //! to the AUX domain resources, it is advised to ensure that the image in
456 //! the Sensor Controller memory is declared invalid. This can be achieved by
457 //! calling AONWUCAuxImageInvalid().
458 //!
459 //! \note Any writes to the AON interface must pass a 32 kHz clock boundary,
460 //! and is therefore relatively slow. To ensure that a given write is
461 //! complete the value of the register can be read back after write.
462 //
463 //! \note When accessing the AUX domain from the System CPU, it is advised always to
464 //! have set the AUX in at least \ref AONWUC_AUX_WAKEUP. This overwrites any
465 //! instruction from the Sensor Controller and ensures that the AUX domain
466 //! is on so it won't leave the System CPU hanging.
467 //!
468 //! \param ui32Mode is the wake up mode for the AUX domain.
469 //! - \ref AONWUC_AUX_WAKEUP
470 //! - \ref AONWUC_AUX_ALLOW_SLEEP
471 //!
472 //! \return None
473 //
474 //*****************************************************************************
475 __STATIC_INLINE void
AONWUCAuxWakeupEvent(uint32_t ui32Mode)476 AONWUCAuxWakeupEvent(uint32_t ui32Mode)
477 {
478 // Check the arguments.
479 ASSERT((ui32Mode == AONWUC_AUX_WAKEUP) ||
480 (ui32Mode == AONWUC_AUX_ALLOW_SLEEP));
481
482 // Wake up the AUX domain.
483 HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCTL, AON_WUC_AUXCTL_AUX_FORCE_ON_BITN) = ui32Mode;
484 }
485
486 //*****************************************************************************
487 //
488 //! \brief Reset the AUX domain.
489 //!
490 //! Use this function to reset the entire AUX domain. The write to the AON_WUC
491 //! module must pass an 32 kHz clock boundary. By reading the
492 //! AON_RTC_O_SYNC register after each write, it is guaranteed that the AON
493 //! interface will be in sync and that both the assert and the de-assert of the
494 //! reset signal to AUX will propagate.
495 //!
496 //! \note This requires two writes and two reads on a 32 kHz clock boundary.
497 //!
498 //! \return None
499 //
500 //*****************************************************************************
501 extern void AONWUCAuxReset(void);
502
503 //*****************************************************************************
504 //
505 //! \brief Tells the Sensor Controller that the image in memory is valid.
506 //!
507 //! Use this function to tell the sensor controller that the image in memory is
508 //! valid, and it is allowed to start executing the program.
509 //!
510 //! \return None
511 //
512 //*****************************************************************************
513 __STATIC_INLINE void
AONWUCAuxImageValid(void)514 AONWUCAuxImageValid(void)
515 {
516 // Tell the Sensor Controller that the image in memory is valid.
517 HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCTL, AON_WUC_AUXCTL_SCE_RUN_EN_BITN) = 1;
518 }
519
520 //*****************************************************************************
521 //
522 //! \brief Tells the Sensor Controller that the image in memory is invalid.
523 //!
524 //! Use this function to tell the sensor controller that the image in memory is
525 //! invalid. Sensor Controller might wake up, but it will stay idle.
526 //!
527 //! \return None
528 //
529 //*****************************************************************************
530 __STATIC_INLINE void
AONWUCAuxImageInvalid(void)531 AONWUCAuxImageInvalid(void)
532 {
533 // Tell the Sensor Controller that the image in memory is invalid.
534 HWREGBITW(AON_WUC_BASE + AON_WUC_O_AUXCTL, AON_WUC_AUXCTL_SCE_RUN_EN_BITN) = 0;
535 }
536
537 //*****************************************************************************
538 //
539 //! \brief Get the power status of the device.
540 //!
541 //! The Always On (AON) domain is the only part of the device which is truly
542 //! "ALWAYS ON". The power status for the other device can always be read from
543 //! this status register.
544 //!
545 //! Possible power modes for the different parts of the device are:
546 //!
547 //! \return Returns the current power status of the device as a bitwise OR'ed
548 //! combination of these values:
549 //! - \ref AONWUC_AUX_POWER_DOWN
550 //! - \ref AONWUC_AUX_POWER_ON
551 //! - \ref AONWUC_JTAG_POWER_ON
552 //! - \ref AONWUC_MCU_POWER_ON
553 //
554 //*****************************************************************************
555 __STATIC_INLINE uint32_t
AONWUCPowerStatusGet(void)556 AONWUCPowerStatusGet(void)
557 {
558 //
559 // Return the power status.
560 //
561 return (HWREG(AON_WUC_BASE + AON_WUC_O_PWRSTAT));
562 }
563
564 //*****************************************************************************
565 //
566 //! \brief Enable shut-down of the device.
567 //!
568 //! Use this function to enable shut-down of the device. This will force all I/O values to
569 //! be latched - possibly enabling I/O wakeup - then all internal power
570 //! supplies are turned off, effectively putting the device into shut-down mode.
571 //!
572 //! \note No action will take place before the System CPU is put to deep sleep.
573 //!
574 //! \note The shut-down command is ignored if the JTAG interface has been
575 //! activated.
576 //!
577 //! \return None
578 //
579 //*****************************************************************************
580 __STATIC_INLINE void
AONWUCShutDownEnable(void)581 AONWUCShutDownEnable(void)
582 {
583 // Ensure the JTAG domain is turned off;
584 // otherwise MCU domain can't be turned off.
585 HWREG(AON_WUC_BASE + AON_WUC_O_JTAGCFG) = 0;
586
587 // Enable shutdown of the device.
588 HWREGBITW(AON_WUC_BASE + AON_WUC_O_CTL0, AON_WUC_CTL0_PWR_DWN_DIS_BITN) = 0;
589 HWREG(AON_WUC_BASE + AON_WUC_O_SHUTDOWN) = AON_WUC_SHUTDOWN_EN;
590 }
591
592 //*****************************************************************************
593 //
594 //! \brief Enable power down mode on AUX and MCU domain.
595 //!
596 //! Use this function to enable powerdown on the AUX and MCU domain.
597 //!
598 //! \note The powerdown command is ignored if the JTAG interface has been
599 //! activated.
600 //!
601 //! \return None
602 //
603 //*****************************************************************************
604 __STATIC_INLINE void
AONWUCDomainPowerDownEnable(void)605 AONWUCDomainPowerDownEnable(void)
606 {
607 // Ensure the JTAG domain is turned off;
608 // otherwise MCU domain can't be turned off.
609 HWREG(AON_WUC_BASE + AON_WUC_O_JTAGCFG) = 0;
610
611 // Enable power down mode.
612 HWREGBITW(AON_WUC_BASE + AON_WUC_O_CTL0, AON_WUC_CTL0_PWR_DWN_DIS_BITN) = 0;
613 }
614
615 //*****************************************************************************
616 //
617 //! \brief Use this function to disable power down mode of the MCU and AUX domain.
618 //!
619 //! Disabling powerdown on the MCU and/or AUX will put the domains in a
620 //! virtual power down when requesting to be powered down. Logic is the same
621 //! but power is kept on.
622 //!
623 //! \return None.
624 //
625 //*****************************************************************************
626 __STATIC_INLINE void
AONWUCDomainPowerDownDisable(void)627 AONWUCDomainPowerDownDisable(void)
628 {
629 // Disable power down mode.
630 HWREGBITW(AON_WUC_BASE + AON_WUC_O_CTL0, AON_WUC_CTL0_PWR_DWN_DIS_BITN) = 1;
631 }
632
633 //*****************************************************************************
634 //
635 //! \brief Use this function to clear specific status bits.
636 //!
637 //! Use this function to clear the bits that are set in the AON WUC status
638 //! register. This register requires a write 1 to clear.
639 //!
640 //! AON Wake Up Controller TAP can request a total/full Flash erase. If so,
641 //! the corresponding status bits will be set in the status register and can
642 //! be read using \ref AONWUCMcuResetStatusGet() or cleared using this function. The reset
643 //! source and type give information about what and how the latest reset
644 //! was performed. Access to these bits are identical to the flash erase
645 //! bits.
646 //!
647 //! \param ui32Status defines in a one-hot encoding which bits to clear in the
648 //! status register. Use OR'ed combinations of the following:
649 //! - \ref AONWUC_MCU_RESET_SRC
650 //! - \ref AONWUC_MCU_WARM_RESET
651 //!
652 //! \return None
653 //
654 //*****************************************************************************
655 __STATIC_INLINE void
AONWUCMcuResetClear(uint32_t ui32Status)656 AONWUCMcuResetClear(uint32_t ui32Status)
657 {
658 //
659 // Check the arguments.
660 //
661 ASSERT((ui32Status & AONWUC_MCU_RESET_SRC) ||
662 (ui32Status & AONWUC_MCU_WARM_RESET));
663
664 //
665 // Clear the status bits.
666 //
667 HWREG(AON_WUC_BASE + AON_WUC_O_CTL1) = ui32Status;
668 }
669
670 //*****************************************************************************
671 //
672 //! \brief Return the reset status.
673 //!
674 //! This function returns the value of the AON_WUC_O_CTL1 register.
675 //!
676 //! \return Returns the status from the AON WUC.
677 //
678 //*****************************************************************************
679 __STATIC_INLINE uint32_t
AONWUCMcuResetStatusGet(void)680 AONWUCMcuResetStatusGet(void)
681 {
682 //
683 // Return the current status.
684 //
685 return (HWREG(AON_WUC_BASE + AON_WUC_O_CTL1));
686 }
687
688 //*****************************************************************************
689 //
690 //! \brief Configure the recharge controller.
691 //!
692 //! The parameter \c bAdaptEnable is used to enable or disable the adaptive
693 //! algorithm for the recharge controller.
694 //! The adaptive algorithm for the recharge controller is defined as
695 //!
696 /*!
697 \verbatim
698
699 New_Period = Period * (1 + (AdaptRate / 1024) )
700
701 AdaptRate
702 ----------- = ( 2^(-C1) + 2^(-C2) )
703 1024
704
705 \endverbatim
706 */
707 //!
708 //! Where C1 is between 1 and 10 and C2 is between 2 and 10. The \c ui32AdaptRate
709 //! must be a number between 2 and 768 (\ref RC_RATE_MIN and \ref RC_RATE_MAX)
710 //! resulting in an adaptive rate between 0.2% and 75%.
711 //!
712 //! The \c ui32Period is the number of 32 KHz clocks between two recharges. The
713 //! length of the interval is defined by the formula:
714 //!
715 /*!
716 \verbatim
717
718 Period = ({ulMantissa,5'b1111} << ui32Exponent)
719
720 \endverbatim
721 */
722 //!
723 //! \note The maximum number of recharge cycles is required when enabling the
724 //! adaptive recharge algorithm.
725 //!
726 //! \note The maximum period between two recharges should never exceed the
727 //! period between two oscillator amplitude calibrations which is configured
728 //! using AONWUCOscConfig().
729 //!
730 //! \param bAdaptEnable enables the adaptation algorithm for the controller.
731 //! \param ui32AdaptRate determines the adjustment value for the adoption
732 //! algorithm.
733 //! \param ui32Period determines the number of clock cycles between each
734 //! activation of the recharge controller.
735 //! \param ui32MaxPeriod determines the maximum number of clock cycles between
736 //! each activation of the recharge controller.
737 //!
738 //! \return None
739 //
740 //*****************************************************************************
741 extern void AONWUCRechargeCtrlConfigSet(bool bAdaptEnable,
742 uint32_t ui32AdaptRate,
743 uint32_t ui32Period,
744 uint32_t ui32MaxPeriod);
745
746 //*****************************************************************************
747 //
748 //! \brief Get the current configuration of the recharge controller.
749 //!
750 //! This function returns the value of the register AON_WUC_O_RECHARGECFG.
751 //!
752 //! \return Returns the current configuration of the recharge controller.
753 //
754 //*****************************************************************************
755 __STATIC_INLINE uint32_t
AONWUCRechargeCtrlConfigGet(void)756 AONWUCRechargeCtrlConfigGet(void)
757 {
758 //
759 // Return the current configuration.
760 //
761 return(HWREG(AON_WUC_BASE + AON_WUC_O_RECHARGECFG));
762 }
763
764 //*****************************************************************************
765 //
766 //! \brief Configure the interval for oscillator amplitude calibration.
767 //!
768 //! Use this function to set the number of 32 kHz clocks between oscillator
769 //! amplitude calibrations.
770 //!
771 //! The value of the interval is defined by the formula:
772 //!
773 /*!
774 \verbatim
775
776 Period = ({ulMantissa,5'b1111} << ui32Exponent)
777
778 \endverbatim
779 */
780 //!
781 //! \note When this counter expires an oscillator amplitude calibration is
782 //! triggered immediately in Active mode. When this counter expires in
783 //! Powerdown mode an internal flag is set that causes GBIAS to turn on
784 //! together with BGAP when the next recharge occurs, at the same time
785 //! triggering the oscillator amplitude calibration as well as a recharge of
786 //! the uLDO reference voltage.
787 //!
788 //! \note The oscillator amplitude calibration is performed at the same time
789 //! as the recharge for the uLDO reference voltage. So the maximum period
790 //! between each recharge operation should not exceed the number of clock
791 //! cycles for the amplitude calibration.
792 //!
793 //! \param ui32Period is the number of 32 kHz clock cycles in each interval.
794 //!
795 //! \return None
796 //
797 //*****************************************************************************
798 extern void AONWUCOscConfig(uint32_t ui32Period);
799
800 //*****************************************************************************
801 //
802 //! \brief Request power off of the JTAG domain.
803 //!
804 //! The JTAG domain is automatically powered up on if a debugger is connected.
805 //! If a debugger is not connected this function can be used to power off the
806 //! JTAG domain.
807 //!
808 //! \note Achieving the lowest power modes (shutdown/powerdown) requires the
809 //! JTAG domain to be turned off. In general the JTAG domain should never be
810 //! powered in production code.
811 //!
812 //! \return None
813 //
814 //*****************************************************************************
815 __STATIC_INLINE void
AONWUCJtagPowerOff(void)816 AONWUCJtagPowerOff(void)
817 {
818 //
819 // Request the power off of the Jtag domain
820 //
821 HWREG(AON_WUC_BASE + AON_WUC_O_JTAGCFG) = 0;
822 }
823
824
825 //*****************************************************************************
826 //
827 // Support for DriverLib in ROM:
828 // Redirect to implementation in ROM when available.
829 //
830 //*****************************************************************************
831 #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
832 #include <driverlib/rom.h>
833 #ifdef ROM_AONWUCAuxReset
834 #undef AONWUCAuxReset
835 #define AONWUCAuxReset ROM_AONWUCAuxReset
836 #endif
837 #ifdef ROM_AONWUCRechargeCtrlConfigSet
838 #undef AONWUCRechargeCtrlConfigSet
839 #define AONWUCRechargeCtrlConfigSet ROM_AONWUCRechargeCtrlConfigSet
840 #endif
841 #ifdef ROM_AONWUCOscConfig
842 #undef AONWUCOscConfig
843 #define AONWUCOscConfig ROM_AONWUCOscConfig
844 #endif
845 #endif
846
847 //*****************************************************************************
848 //
849 // Mark the end of the C bindings section for C++ compilers.
850 //
851 //*****************************************************************************
852 #ifdef __cplusplus
853 }
854 #endif
855
856 #endif // __AON_WUC_H__
857
858 //*****************************************************************************
859 //
860 //! Close the Doxygen group.
861 //! @}
862 //! @}
863 //
864 //*****************************************************************************
865