1 /****************************************************************************** 2 * config.h 3 * 4 * A Linux-style configuration list. 5 */ 6 7 #ifndef __X86_CONFIG_H__ 8 #define __X86_CONFIG_H__ 9 10 #define LONG_BYTEORDER 3 11 #define CONFIG_PAGING_LEVELS 4 12 13 #define BYTES_PER_LONG (1 << LONG_BYTEORDER) 14 #define BITS_PER_LONG (BYTES_PER_LONG << 3) 15 #define BITS_PER_BYTE 8 16 #define POINTER_ALIGN BYTES_PER_LONG 17 18 #define BITS_PER_LLONG 64 19 20 #define BITS_PER_XEN_ULONG BITS_PER_LONG 21 22 #define CONFIG_X86_PM_TIMER 1 23 #define CONFIG_HPET_TIMER 1 24 #define CONFIG_X86_MCE_THERMAL 1 25 #define CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1 26 #define CONFIG_DISCONTIGMEM 1 27 #define CONFIG_NUMA_EMU 1 28 #define CONFIG_DOMAIN_PAGE 1 29 30 #define CONFIG_PAGEALLOC_MAX_ORDER (2 * PAGETABLE_ORDER) 31 #define CONFIG_DOMU_MAX_ORDER PAGETABLE_ORDER 32 #define CONFIG_HWDOM_MAX_ORDER 12 33 34 /* Intel P4 currently has largest cache line (L2 line size is 128 bytes). */ 35 #define CONFIG_X86_L1_CACHE_SHIFT 7 36 37 #define CONFIG_ACPI_SLEEP 1 38 #define CONFIG_ACPI_NUMA 1 39 #define CONFIG_ACPI_SRAT 1 40 #define CONFIG_ACPI_CSTATE 1 41 42 #define CONFIG_WATCHDOG 1 43 44 #define CONFIG_MULTIBOOT 1 45 46 #define HZ 100 47 48 #define OPT_CONSOLE_STR "vga" 49 50 /* Linkage for x86 */ 51 #ifdef __ASSEMBLY__ 52 #define ALIGN .align 16,0x90 53 #define ENTRY(name) \ 54 .globl name; \ 55 ALIGN; \ 56 name: 57 #define GLOBAL(name) \ 58 .globl name; \ 59 name: 60 #endif 61 62 #define NR_hypercalls 64 63 64 #ifndef NDEBUG 65 #define MEMORY_GUARD 66 #endif 67 68 #define STACK_ORDER 3 69 #define STACK_SIZE (PAGE_SIZE << STACK_ORDER) 70 71 #define TRAMPOLINE_STACK_SPACE PAGE_SIZE 72 #define TRAMPOLINE_SPACE (KB(64) - TRAMPOLINE_STACK_SPACE) 73 #define WAKEUP_STACK_MIN 3072 74 75 #define MBI_SPACE_MIN (2 * PAGE_SIZE) 76 77 /* Primary stack is restricted to 8kB by guard pages. */ 78 #define PRIMARY_STACK_SIZE 8192 79 80 /* Total size of syscall and emulation stubs. */ 81 #define STUB_BUF_SHIFT (L1_CACHE_SHIFT > 7 ? L1_CACHE_SHIFT : 7) 82 #define STUB_BUF_SIZE (1 << STUB_BUF_SHIFT) 83 84 /* Return value for zero-size _xmalloc(), distinguished from NULL. */ 85 #define ZERO_BLOCK_PTR ((void *)0xBAD0BAD0BAD0BAD0UL) 86 87 /* Override include/xen/list.h to make these non-canonical addresses. */ 88 #define LIST_POISON1 ((void *)0x0100100100100100UL) 89 #define LIST_POISON2 ((void *)0x0200200200200200UL) 90 91 #ifndef __ASSEMBLY__ 92 extern unsigned long trampoline_phys; 93 #define bootsym_phys(sym) \ 94 (((unsigned long)&(sym)-(unsigned long)&trampoline_start)+trampoline_phys) 95 #define bootsym(sym) \ 96 (*RELOC_HIDE((typeof(&(sym)))__va(__pa(&(sym))), \ 97 trampoline_phys-__pa(trampoline_start))) 98 extern char trampoline_start[], trampoline_end[]; 99 extern char trampoline_realmode_entry[]; 100 extern unsigned int trampoline_xen_phys_start; 101 extern unsigned char trampoline_cpu_started; 102 extern char wakeup_start[]; 103 extern unsigned int video_mode, video_flags; 104 extern unsigned short boot_edid_caps; 105 extern unsigned char boot_edid_info[128]; 106 #endif 107 108 #include <xen/const.h> 109 110 #define PML4_ENTRY_BITS 39 111 #define PML4_ENTRY_BYTES (_AC(1,UL) << PML4_ENTRY_BITS) 112 #define PML4_ADDR(_slot) \ 113 (((_AC(_slot, UL) >> 8) * _AC(0xffff000000000000,UL)) | \ 114 (_AC(_slot, UL) << PML4_ENTRY_BITS)) 115 116 /* 117 * Memory layout: 118 * 0x0000000000000000 - 0x00007fffffffffff [128TB, 2^47 bytes, PML4:0-255] 119 * Guest-defined use (see below for compatibility mode guests). 120 * 0x0000800000000000 - 0xffff7fffffffffff [16EB] 121 * Inaccessible: current arch only supports 48-bit sign-extended VAs. 122 * 0xffff800000000000 - 0xffff803fffffffff [256GB, 2^38 bytes, PML4:256] 123 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE). 124 * 0xffff804000000000 - 0xffff807fffffffff [256GB, 2^38 bytes, PML4:256] 125 * Reserved for future shared info with the guest OS (GUEST ACCESSIBLE). 126 * 0xffff808000000000 - 0xffff80ffffffffff [512GB, 2^39 bytes, PML4:257] 127 * ioremap for PCI mmconfig space 128 * 0xffff810000000000 - 0xffff817fffffffff [512GB, 2^39 bytes, PML4:258] 129 * Guest linear page table. 130 * 0xffff818000000000 - 0xffff81ffffffffff [512GB, 2^39 bytes, PML4:259] 131 * Shadow linear page table. 132 * 0xffff820000000000 - 0xffff827fffffffff [512GB, 2^39 bytes, PML4:260] 133 * Per-domain mappings (e.g., GDT, LDT). 134 * 0xffff828000000000 - 0xffff82bfffffffff [256GB, 2^38 bytes, PML4:261] 135 * Machine-to-phys translation table. 136 * 0xffff82c000000000 - 0xffff82cfffffffff [64GB, 2^36 bytes, PML4:261] 137 * vmap()/ioremap()/fixmap area. 138 * 0xffff82d000000000 - 0xffff82d03fffffff [1GB, 2^30 bytes, PML4:261] 139 * Compatibility machine-to-phys translation table. 140 * 0xffff82d040000000 - 0xffff82d07fffffff [1GB, 2^30 bytes, PML4:261] 141 * High read-only compatibility machine-to-phys translation table. 142 * 0xffff82d080000000 - 0xffff82d0bfffffff [1GB, 2^30 bytes, PML4:261] 143 * Xen text, static data, bss. 144 #ifndef CONFIG_BIGMEM 145 * 0xffff82d0c0000000 - 0xffff82dfffffffff [61GB, PML4:261] 146 * Reserved for future use. 147 * 0xffff82e000000000 - 0xffff82ffffffffff [128GB, 2^37 bytes, PML4:261] 148 * Page-frame information array. 149 * 0xffff830000000000 - 0xffff87ffffffffff [5TB, 5*2^40 bytes, PML4:262-271] 150 * 1:1 direct mapping of all physical memory. 151 #else 152 * 0xffff82d0c0000000 - 0xffff82ffffffffff [189GB, PML4:261] 153 * Reserved for future use. 154 * 0xffff830000000000 - 0xffff847fffffffff [1.5TB, 3*2^39 bytes, PML4:262-264] 155 * Page-frame information array. 156 * 0xffff848000000000 - 0xffff87ffffffffff [3.5TB, 7*2^39 bytes, PML4:265-271] 157 * 1:1 direct mapping of all physical memory. 158 #endif 159 * 0xffff880000000000 - 0xffffffffffffffff [120TB, PML4:272-511] 160 * PV: Guest-defined use. 161 * 0xffff880000000000 - 0xffffff7fffffffff [119.5TB, PML4:272-510] 162 * HVM/idle: continuation of 1:1 mapping 163 * 0xffffff8000000000 - 0xffffffffffffffff [512GB, 2^39 bytes PML4:511] 164 * HVM/idle: unused 165 * 166 * Compatibility guest area layout: 167 * 0x0000000000000000 - 0x00000000f57fffff [3928MB, PML4:0] 168 * Guest-defined use. 169 * 0x00000000f5800000 - 0x00000000ffffffff [168MB, PML4:0] 170 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE). 171 * 0x0000000100000000 - 0x00007fffffffffff [128TB-4GB, PML4:0-255] 172 * Unused / Reserved for future use. 173 */ 174 175 176 #define ROOT_PAGETABLE_FIRST_XEN_SLOT 256 177 #define ROOT_PAGETABLE_LAST_XEN_SLOT 271 178 #define ROOT_PAGETABLE_XEN_SLOTS \ 179 (L4_PAGETABLE_ENTRIES - ROOT_PAGETABLE_FIRST_XEN_SLOT - 1) 180 #define ROOT_PAGETABLE_PV_XEN_SLOTS \ 181 (ROOT_PAGETABLE_LAST_XEN_SLOT - ROOT_PAGETABLE_FIRST_XEN_SLOT + 1) 182 183 /* Hypervisor reserves PML4 slots 256 to 271 inclusive. */ 184 #define HYPERVISOR_VIRT_START (PML4_ADDR(256)) 185 #define HYPERVISOR_VIRT_END (HYPERVISOR_VIRT_START + PML4_ENTRY_BYTES*16) 186 /* Slot 256: read-only guest-accessible machine-to-phys translation table. */ 187 #define RO_MPT_VIRT_START (PML4_ADDR(256)) 188 #define MPT_VIRT_SIZE (PML4_ENTRY_BYTES / 2) 189 #define RO_MPT_VIRT_END (RO_MPT_VIRT_START + MPT_VIRT_SIZE) 190 /* Slot 257: ioremap for PCI mmconfig space for 2048 segments (512GB) 191 * - full 16-bit segment support needs 44 bits 192 * - since PML4 slot has 39 bits, we limit segments to 2048 (11-bits) 193 */ 194 #define PCI_MCFG_VIRT_START (PML4_ADDR(257)) 195 #define PCI_MCFG_VIRT_END (PCI_MCFG_VIRT_START + PML4_ENTRY_BYTES) 196 /* Slot 258: linear page table (guest table). */ 197 #define LINEAR_PT_VIRT_START (PML4_ADDR(258)) 198 #define LINEAR_PT_VIRT_END (LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES) 199 /* Slot 259: linear page table (shadow table). */ 200 #define SH_LINEAR_PT_VIRT_START (PML4_ADDR(259)) 201 #define SH_LINEAR_PT_VIRT_END (SH_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES) 202 /* Slot 260: per-domain mappings (including map cache). */ 203 #define PERDOMAIN_VIRT_START (PML4_ADDR(260)) 204 #define PERDOMAIN_SLOT_MBYTES (PML4_ENTRY_BYTES >> (20 + PAGETABLE_ORDER)) 205 #define PERDOMAIN_SLOTS 3 206 #define PERDOMAIN_VIRT_SLOT(s) (PERDOMAIN_VIRT_START + (s) * \ 207 (PERDOMAIN_SLOT_MBYTES << 20)) 208 /* Slot 261: machine-to-phys conversion table (256GB). */ 209 #define RDWR_MPT_VIRT_START (PML4_ADDR(261)) 210 #define RDWR_MPT_VIRT_END (RDWR_MPT_VIRT_START + MPT_VIRT_SIZE) 211 /* Slot 261: vmap()/ioremap()/fixmap area (64GB). */ 212 #define VMAP_VIRT_START RDWR_MPT_VIRT_END 213 #define VMAP_VIRT_END (VMAP_VIRT_START + GB(64)) 214 /* Slot 261: compatibility machine-to-phys conversion table (1GB). */ 215 #define RDWR_COMPAT_MPT_VIRT_START VMAP_VIRT_END 216 #define RDWR_COMPAT_MPT_VIRT_END (RDWR_COMPAT_MPT_VIRT_START + GB(1)) 217 /* Slot 261: high read-only compat machine-to-phys conversion table (1GB). */ 218 #define HIRO_COMPAT_MPT_VIRT_START RDWR_COMPAT_MPT_VIRT_END 219 #define HIRO_COMPAT_MPT_VIRT_END (HIRO_COMPAT_MPT_VIRT_START + GB(1)) 220 /* Slot 261: xen text, static data and bss (1GB). */ 221 #define XEN_VIRT_START (HIRO_COMPAT_MPT_VIRT_END) 222 #define XEN_VIRT_END (XEN_VIRT_START + GB(1)) 223 224 #ifndef CONFIG_BIGMEM 225 /* Slot 261: page-frame information array (128GB). */ 226 #define FRAMETABLE_SIZE GB(128) 227 #else 228 /* Slot 262-264: page-frame information array (1.5TB). */ 229 #define FRAMETABLE_SIZE GB(1536) 230 #endif 231 #define FRAMETABLE_VIRT_END DIRECTMAP_VIRT_START 232 #define FRAMETABLE_NR (FRAMETABLE_SIZE / sizeof(*frame_table)) 233 #define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - FRAMETABLE_SIZE) 234 235 #ifndef CONFIG_BIGMEM 236 /* Slot 262-271/510: A direct 1:1 mapping of all of physical memory. */ 237 #define DIRECTMAP_VIRT_START (PML4_ADDR(262)) 238 #define DIRECTMAP_SIZE (PML4_ENTRY_BYTES * (511 - 262)) 239 #else 240 /* Slot 265-271/510: A direct 1:1 mapping of all of physical memory. */ 241 #define DIRECTMAP_VIRT_START (PML4_ADDR(265)) 242 #define DIRECTMAP_SIZE (PML4_ENTRY_BYTES * (511 - 265)) 243 #endif 244 #define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + DIRECTMAP_SIZE) 245 246 #ifndef __ASSEMBLY__ 247 248 /* This is not a fixed value, just a lower limit. */ 249 #define __HYPERVISOR_COMPAT_VIRT_START 0xF5800000 250 #define HYPERVISOR_COMPAT_VIRT_START(d) ((d)->arch.hv_compat_vstart) 251 #define MACH2PHYS_COMPAT_VIRT_START HYPERVISOR_COMPAT_VIRT_START 252 #define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000 253 #define MACH2PHYS_COMPAT_NR_ENTRIES(d) \ 254 ((MACH2PHYS_COMPAT_VIRT_END-MACH2PHYS_COMPAT_VIRT_START(d))>>2) 255 256 #define COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) \ 257 l2_table_offset(HYPERVISOR_COMPAT_VIRT_START(d)) 258 #define COMPAT_L2_PAGETABLE_LAST_XEN_SLOT l2_table_offset(~0U) 259 #define COMPAT_L2_PAGETABLE_XEN_SLOTS(d) \ 260 (COMPAT_L2_PAGETABLE_LAST_XEN_SLOT - COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) + 1) 261 262 #define COMPAT_LEGACY_MAX_VCPUS XEN_LEGACY_MAX_VCPUS 263 #define COMPAT_HAVE_PV_GUEST_ENTRY XEN_HAVE_PV_GUEST_ENTRY 264 #define COMPAT_HAVE_PV_UPCALL_MASK XEN_HAVE_PV_UPCALL_MASK 265 266 #endif 267 268 #define __HYPERVISOR_CS64 0xe008 269 #define __HYPERVISOR_CS32 0xe038 270 #define __HYPERVISOR_CS __HYPERVISOR_CS64 271 #define __HYPERVISOR_DS64 0x0000 272 #define __HYPERVISOR_DS32 0xe010 273 #define __HYPERVISOR_DS __HYPERVISOR_DS64 274 275 #define SYMBOLS_ORIGIN XEN_VIRT_START 276 277 /* For generic assembly code: use macros to define operation/operand sizes. */ 278 #define __OS "q" /* Operation Suffix */ 279 #define __OP "r" /* Operand Prefix */ 280 281 #ifndef __ASSEMBLY__ 282 extern unsigned long xen_phys_start; 283 #endif 284 285 /* GDT/LDT shadow mapping area. The first per-domain-mapping sub-area. */ 286 #define GDT_LDT_VCPU_SHIFT 5 287 #define GDT_LDT_VCPU_VA_SHIFT (GDT_LDT_VCPU_SHIFT + PAGE_SHIFT) 288 #define GDT_LDT_MBYTES PERDOMAIN_SLOT_MBYTES 289 #define MAX_VIRT_CPUS (GDT_LDT_MBYTES << (20-GDT_LDT_VCPU_VA_SHIFT)) 290 #define GDT_LDT_VIRT_START PERDOMAIN_VIRT_SLOT(0) 291 #define GDT_LDT_VIRT_END (GDT_LDT_VIRT_START + (GDT_LDT_MBYTES << 20)) 292 293 /* The address of a particular VCPU's GDT or LDT. */ 294 #define GDT_VIRT_START(v) \ 295 (PERDOMAIN_VIRT_START + ((v)->vcpu_id << GDT_LDT_VCPU_VA_SHIFT)) 296 #define LDT_VIRT_START(v) \ 297 (GDT_VIRT_START(v) + (64*1024)) 298 299 /* map_domain_page() map cache. The second per-domain-mapping sub-area. */ 300 #define MAPCACHE_VCPU_ENTRIES (CONFIG_PAGING_LEVELS * CONFIG_PAGING_LEVELS) 301 #define MAPCACHE_ENTRIES (MAX_VIRT_CPUS * MAPCACHE_VCPU_ENTRIES) 302 #define MAPCACHE_VIRT_START PERDOMAIN_VIRT_SLOT(1) 303 #define MAPCACHE_VIRT_END (MAPCACHE_VIRT_START + \ 304 MAPCACHE_ENTRIES * PAGE_SIZE) 305 306 /* Argument translation area. The third per-domain-mapping sub-area. */ 307 #define ARG_XLAT_VIRT_START PERDOMAIN_VIRT_SLOT(2) 308 /* Allow for at least one guard page (COMPAT_ARG_XLAT_SIZE being 2 pages): */ 309 #define ARG_XLAT_VA_SHIFT (2 + PAGE_SHIFT) 310 #define ARG_XLAT_START(v) \ 311 (ARG_XLAT_VIRT_START + ((v)->vcpu_id << ARG_XLAT_VA_SHIFT)) 312 313 #define NATIVE_VM_ASSIST_VALID ((1UL << VMASST_TYPE_4gb_segments) | \ 314 (1UL << VMASST_TYPE_4gb_segments_notify) | \ 315 (1UL << VMASST_TYPE_writable_pagetables) | \ 316 (1UL << VMASST_TYPE_pae_extended_cr3) | \ 317 (1UL << VMASST_TYPE_architectural_iopl) | \ 318 (1UL << VMASST_TYPE_runstate_update_flag)| \ 319 (1UL << VMASST_TYPE_m2p_strict)) 320 #define VM_ASSIST_VALID NATIVE_VM_ASSIST_VALID 321 #define COMPAT_VM_ASSIST_VALID (NATIVE_VM_ASSIST_VALID & \ 322 ((1UL << COMPAT_BITS_PER_LONG) - 1)) 323 324 #define ELFSIZE 64 325 326 #define ARCH_CRASH_SAVE_VMCOREINFO 327 328 #endif /* __X86_CONFIG_H__ */ 329