1 /**
2 ******************************************************************************
3 * @file rtl8721d_tim.c
4 * @author
5 * @version V1.0.0
6 * @date 2016-05-17
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the Timer peripheral:
9 * - Initialization
10 * - TimeBase configuration and management
11 * - Intput Capture/Output Compare configuration and management
12 * - Interrupt and DMA management
13 ******************************************************************************
14 * @attention
15 *
16 * This module is a confidential and proprietary property of RealTek and
17 * possession or use of this module requires written permission of RealTek.
18 *
19 * Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
20 ******************************************************************************
21 */
22 #include "ameba_soc.h"
23
24 int TIMx_irq[6] = {
25 TIMER0_IRQ,
26 TIMER1_IRQ,
27 TIMER2_IRQ,
28 TIMER3_IRQ,
29 TIMER4_IRQ,
30 TIMER5_IRQ,
31 };
32
33 RTIM_TypeDef* TIMx[6] = {
34 TIM0,
35 TIM1,
36 TIM2,
37 TIM3,
38 TIM4,
39 TIM5
40 };
41
42 u32 TIM_IT_CCx[18] = {
43 TIM_IT_CC0,
44 TIM_IT_CC1,
45 TIM_IT_CC2,
46 TIM_IT_CC3,
47 TIM_IT_CC4,
48 TIM_IT_CC5,
49 TIM_IT_CC6,
50 TIM_IT_CC7,
51 TIM_IT_CC8,
52 TIM_IT_CC9,
53 TIM_IT_CC10,
54 TIM_IT_CC11,
55 TIM_IT_CC12,
56 TIM_IT_CC13,
57 TIM_IT_CC14,
58 TIM_IT_CC15,
59 TIM_IT_CC16,
60 TIM_IT_CC17
61 };
62
63 int TIMx_irq_LP[6] = {
64 TIMER0_IRQ_LP,
65 TIMER1_IRQ_LP,
66 TIMER2_IRQ_LP,
67 TIMER3_IRQ_LP,
68 TIMER4_IRQ_LP,
69 TIMER5_IRQ_LP,
70 };
71
72 RTIM_TypeDef* TIMx_LP[6] = {
73 TIMM00,
74 TIMM01,
75 TIMM02,
76 TIMM03,
77 TIMM04,
78 TIMM05
79 };
80
81 u32 TIM_IT_CCx_LP[6] = {
82 TIM_IT_CC0,
83 TIM_IT_CC1,
84 TIM_IT_CC2,
85 TIM_IT_CC3,
86 TIM_IT_CC4,
87 TIM_IT_CC5
88 };
89
90 /**
91 * @brief Enables or Disables the TIMx Update event(UEV).
92 * @param TIMx: where x can be 0-5 to select the TIM peripheral.
93 * @param NewState: new state of the TIMx UDIS bit
94 * This parameter can be:ENABLE or DISABLE
95 * @note
96 * - If NewState is ENABLE, Update Disable Bit is set, UEV disable and shadow registers keep their value.
97 * - If NewState is DISABLE, Update Disable Bit is clear, UEV enable and buffered registers are loaded with
98 * their preload values when UEV happen.
99 * @retval None
100 */
RTIM_UpdateDisableConfig(RTIM_TypeDef * TIMx,u32 NewState)101 void RTIM_UpdateDisableConfig(RTIM_TypeDef* TIMx, u32 NewState)
102 {
103 /* Check the parameters */
104 assert_param(IS_TIM_ALL_TIM(TIMx));
105
106 if (NewState != DISABLE) {
107 /* Set the Update Disable Bit */
108 TIMx->CR |= TIM_CR_UDIS;
109 } else {
110 /* Reset the Update Disable Bit */
111 TIMx->CR &= ~TIM_CR_UDIS;
112 }
113 }
114
115 /**
116 * @brief Enables or disables TIMx peripheral Preload register on ARR.
117 * @param TIMx: where x can be 0-5 to select the TIM peripheral.
118 * @param NewState: new state of the TIMx peripheral Preload register
119 * This parameter can be: ENABLE or DISABLE.
120 * @note
121 * - DISABLE: TIMx_ARR register is not buffered, and shadow register will update immediately
122 * - ENABLE: TIMx_ARR register is buffered, and shadow register will update after overflow
123 * @retval None
124 */
RTIM_ARRPreloadConfig(RTIM_TypeDef * TIMx,u32 NewState)125 void RTIM_ARRPreloadConfig(RTIM_TypeDef* TIMx, u32 NewState)
126 {
127 /* Check the parameters */
128 assert_param(IS_TIM_ALL_TIM(TIMx));
129
130 if (NewState != DISABLE) {
131 /* Set the ARR Preload Bit */
132 TIMx->CR |= TIM_CR_ARPE;
133 } else {
134 /* Reset the ARR Preload Bit */
135 TIMx->CR &= ~TIM_CR_ARPE;
136 }
137 }
138
139 /**
140 * @brief Configures the TIMx Update Request Interrupt source.
141 * @param TIMx: where x can be 0-5 to select the TIM peripheral.
142 * @param TIM_UpdateSource: specifies the Update source.
143 * This parameter can be one of the following values:
144 * @arg TIM_UpdateSource_Global: Source of update is the counter
145 * overflow or the setting of UG bit.
146 * @arg TIM_UpdateSource_Overflow: Source of update is counter overflow.
147 * @retval None
148 */
RTIM_UpdateRequestConfig(RTIM_TypeDef * TIMx,u32 TIM_UpdateSource)149 void RTIM_UpdateRequestConfig(RTIM_TypeDef* TIMx, u32 TIM_UpdateSource)
150 {
151 /* Check the parameters */
152 assert_param(IS_TIM_ALL_TIM(TIMx));
153 assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
154
155 if (TIM_UpdateSource != TIM_UpdateSource_Global) {
156 /* Set the URS Bit */
157 TIMx->CR |= TIM_CR_URS;
158 } else {
159 /* Reset the URS Bit */
160 TIMx->CR &= (u32)~TIM_CR_URS;
161 }
162 }
163
164 /**
165 * @brief Configures the TIMx Prescaler.
166 * @param TIMx: where x can be 4 or 5 to select the TIM peripheral.
167 * @param Prescaler: specifies the Prescaler Register value,which can be a number in 0~0xFF range.
168 * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
169 * This parameter can be one of the following values:
170 * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
171 * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
172 * @retval None
173 */
RTIM_PrescalerConfig(RTIM_TypeDef * TIMx,u32 Prescaler,u32 TIM_PSCReloadMode)174 void RTIM_PrescalerConfig(RTIM_TypeDef* TIMx, u32 Prescaler, u32 TIM_PSCReloadMode)
175 {
176 /* Check the parameters */
177 assert_param(IS_TIM_40M_TIM(TIMx));
178 assert_param(IS_TIM_PSC(Prescaler));
179 assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
180
181 /* Set the Prescaler value */
182 TIMx->PSC = Prescaler;
183 /* Set or reset the UG Bit */
184 TIMx->EGR = TIM_PSCReloadMode;
185 }
186
187 /**
188 * @brief Configures the TIMx event to be generate by software.
189 * @param TIMx: where x can be 0-5 to select the TIM peripheral.
190 * @param TIM_EventSource: specifies the event source.
191 * This parameter can be one or more of the following values @ref TIMx_Event_Generation_definitons
192 * @note
193 * - TIM0~5/TIMM00~05 have Timer update Event source TIM_EventSource_Update
194 * - TIM4/TIMM04 have Timer Capture Compare 1 Event source TIM_EventSource_CC0
195 * - TIMM05 has 6 Timer Capture Compare x Event source TIM_EventSource_CC0-5.
196 * - TIM5 has 18 Timer Capture Compare x Event source TIM_EventSource_CC0-17.
197 * @retval None
198 */
RTIM_GenerateEvent(RTIM_TypeDef * TIMx,u32 TIM_EventSource)199 void RTIM_GenerateEvent(RTIM_TypeDef* TIMx, u32 TIM_EventSource)
200 {
201 /* Check the parameters */
202 assert_param(IS_TIM_ALL_TIM(TIMx));
203 assert_param((IS_HP_TIM_EVENT_SOURCE(TIM_EventSource) || IS_LP_TIM_EVENT_SOURCE(TIM_EventSource)));
204
205 /* Set the event sources */
206 TIMx->EGR = TIM_EventSource;
207 }
208
209 /**
210 * @brief Sets the TIMx Autoreload Register(TIMx_ARR) value to change period
211 * @param TIMx: where x can be 0-5 to select the TIM peripheral.
212 * @param Autoreload: specifies the Autoreload register new value.
213 * To TIM0~3/TIMM00~TIMM03 this value can be a number in 0~0xFFFFFFFF range.
214 * To TIM4~5/TIMM04~TIMM05 this value can be a number in 0~0xFFFF range.
215 * @retval None
216 */
RTIM_ChangePeriodImmediate(RTIM_TypeDef * TIMx,u32 Autoreload)217 void RTIM_ChangePeriodImmediate(RTIM_TypeDef* TIMx, u32 Autoreload)
218 {
219 /* Check the parameters */
220 assert_param(IS_TIM_ALL_TIM(TIMx));
221
222 /* Reset the ARR Preload Bit */
223 /* period will update immediatly */
224 TIMx->CR &= ~TIM_CR_ARPE;
225
226 /* Set the Autoreload Register value */
227 TIMx->ARR = Autoreload;
228
229 /* Generate an update event */
230 /* 1) reload the Prescaler immediatly */
231 /* 2) reload the ARR immediatly */
232 /* 3) hadrware will clear this bit after reload */
233 /* 4) UEV will reset counter, and counter will start from 0 */
234 /* 5) gen a interrupt if use TIM_UpdateSource_Global */
235 TIMx->EGR = TIM_PSCReloadMode_Immediate;
236
237 /* poll EGR UG done */
238 while (1) {
239 if (TIMx->SR & TIM_SR_UG_DONE)
240 break;
241 }
242 }
243
244 /**
245 * @brief Sets the TIMx Autoreload Register(TIMx_ARR) value to change period with protection
246 * @param TIMx: where x can be 0-5 to select the TIM peripheral.
247 * @param Autoreload: specifies the Autoreload register new value.
248 * To TIM0~3/TIMM00~TIMM03 this value can be a number in 0~0xFFFFFFFF range.
249 * To TIM4~5/TIMM04~TIMM05 this value can be a number in 0~0xFFFF range.
250 * @retval None
251 */
RTIM_ChangePeriod(RTIM_TypeDef * TIMx,u32 Autoreload)252 void RTIM_ChangePeriod(RTIM_TypeDef* TIMx, u32 Autoreload)
253 {
254 /* Check the parameters */
255 assert_param(IS_TIM_ALL_TIM(TIMx));
256
257 /* Set the Autoreload Register value */
258 TIMx->ARR = Autoreload;
259 }
260
261 /**
262 * @brief Reset timer, counter will start from 0
263 * @param TIMx: where x can be 0-5 to select the TIM peripheral.
264 * @retval None
265 */
RTIM_Reset(RTIM_TypeDef * TIMx)266 void RTIM_Reset(RTIM_TypeDef* TIMx)
267 {
268 /* Check the parameters */
269 assert_param(IS_TIM_ALL_TIM(TIMx));
270
271 /* Generate an update event */
272 /* 1) reload the Prescaler immediatly */
273 /* 2) reload the ARR immediatly */
274 /* 3) hadrware will clear this bit after reload */
275 /* 4) UEV will reset counter, and counter will start from 0 */
276 /* 5) gen a interrupt if use TIM_UpdateSource_Global */
277 TIMx->EGR = TIM_PSCReloadMode_Immediate;
278 }
279
280 /**
281 * @brief Fills each TIM_CCInitStruct member with its default value.
282 * @param TIM_CCInitStruct: pointer to a TIM_CCInitTypeDef structure which will
283 * be initialized.
284 * @retval None
285 */
RTIM_CCStructInit(TIM_CCInitTypeDef * TIM_CCInitStruct)286 void RTIM_CCStructInit(TIM_CCInitTypeDef* TIM_CCInitStruct)
287 {
288 /* Set the default configuration */
289 TIM_CCInitStruct->TIM_CCMode = TIM_CCMode_PWM;
290 TIM_CCInitStruct->TIM_CCPolarity = TIM_CCPolarity_High;
291 TIM_CCInitStruct->TIM_OCProtection = TIM_OCPreload_Enable;
292 TIM_CCInitStruct->TIM_OCPulse = 0xFFF;
293 }
294
295 /**
296 * @brief Initializes the TIMx Channel 0-5 according to the specified parameters in
297 * the TIM_CCInitStruct.
298 * @param TIMx: where x can be 4/5, to select the TIM peripheral.
299 * @param TIM_CCInitStruct: pointer to a TIM_CCInitTypeDef structure that contains
300 * the configuration information for the specified TIM peripheral.
301 * @param TIM_Channel: the channel need to be initialized,
302 * which can be one of the following parameters @ref TIM_Channel_definitions
303 * @note
304 * - TIM4/TIMM04 only has 1 channel: TIM_Channel_0
305 * - TIMM05 has 6 channels: TIM_Channel_0-5.
306 * - TIM5 has 18 channels: TIM_Channel_0-17.
307 * @retval None
308 */
RTIM_CCxInit(RTIM_TypeDef * TIMx,TIM_CCInitTypeDef * TIM_CCInitStruct,u16 TIM_Channel)309 void RTIM_CCxInit(RTIM_TypeDef* TIMx, TIM_CCInitTypeDef* TIM_CCInitStruct, u16 TIM_Channel)
310 {
311 /* Check the parameters */
312 assert_param(IS_TIM_CCM_TIM(TIMx));
313 assert_param(IS_TIM_CC_MODE(TIM_CCInitStruct->TIM_CCMode));
314 assert_param(IS_TIM_CC_POLARITY(TIM_CCInitStruct->TIM_CCPolarity));
315 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_CCInitStruct->TIM_OCProtection));
316 assert_param(IS_TIM_CHANNEL(TIM_Channel));
317
318 /* Reset the CCMR Bit */
319 TIMx->CCMRx[TIM_Channel] = 0;
320
321 /* Write to TIMx CCMR */
322 if (IS_TIM_PWM_TIM(TIMx)) {
323 TIMx->CCMRx[TIM_Channel] = (TIM_CCInitStruct->TIM_CCPolarity |
324 TIM_CCInitStruct->TIM_OCProtection |
325 TIM_CCInitStruct->TIM_CCMode |
326 TIM_CCInitStruct->TIM_OCPulse);
327 } else if (IS_TIM_INPULSE_TIM(TIMx)) {
328 TIMx->CCMRx[TIM_Channel] = (TIM_CCInitStruct->TIM_CCPolarity |
329 TIM_CCInitStruct->TIM_ICPulseMode);
330 }
331 }
332
333 /**
334 * @brief Initializes the TIMx Channel 0-5 CCmode.
335 * @param TIMx: where x can be 5, to select the TIM peripheral.
336 * @param TIM_Channel: the channel need to be set mode,
337 * which can be one of the following parameters @ref TIM_Channel_definitions.
338 * @param TIM_CCMode: CCx working mode which can be one of the following parameters:
339 * @arg TIM_CCMode_PWM
340 * @arg TIM_CCMode_Inputcapture
341 * @note
342 * - TIM4/TIMM04 only has 1 channel: TIM_Channel_0
343 * - TIMM05 has 6 channels: TIM_Channel_0-5.
344 * - TIM5 has 18 channels: TIM_Channel_0-17.
345 * @retval None
346 */
RTIM_CCRxMode(RTIM_TypeDef * TIMx,u16 TIM_Channel,u32 TIM_CCMode)347 void RTIM_CCRxMode(RTIM_TypeDef* TIMx, u16 TIM_Channel, u32 TIM_CCMode)
348 {
349 u32 tmpccmr = TIMx->CCMRx[TIM_Channel];
350
351 /* Check the parameters */
352 assert_param(IS_TIM_PWM_TIM(TIMx));
353 assert_param(IS_TIM_CC_MODE(TIM_CCMode));
354
355 tmpccmr &= ~TIM_CCER_CCxM;
356 tmpccmr |= TIM_CCMode;
357
358 /* Write to TIMx CCMR */
359 TIMx->CCMRx[TIM_Channel] = tmpccmr;
360 }
361
362 /**
363 * @brief Sets the TIMx Capture Compare X register value
364 * @param TIMx: where x can be 5, to select the TIM peripheral.
365 * @param Compare: the value specifies pulsewidth, which is in the 0x00~0xFFFF range.
366 * Duty cycle = Compare / (ARR+1).
367 * @param TIM_Channel: the channel to be set,
368 * which can be one of the following parameters @ref TIM_Channel_definitions.
369 * @retval None
370 * @note
371 * - CCRx=0 will give 0% cycle pwm pulse.
372 * - CCRx>=TIM_Period there will be 100% pwm pulse.
373 * - TIMM05 has 6 channels: TIM_Channel_0-5.
374 * - TIM5 has 18 channels: TIM_Channel_0-17.
375 */
RTIM_CCRxSet(RTIM_TypeDef * TIMx,u32 Compare,u16 TIM_Channel)376 void RTIM_CCRxSet(RTIM_TypeDef* TIMx, u32 Compare, u16 TIM_Channel)
377 {
378 u32 PulseWidth = 0;
379 u32 tmpccmr = 0;
380
381 /* Check the parameters */
382 assert_param(IS_TIM_PWM_TIM(TIMx));
383 assert_param(IS_TIM_CHANNEL(TIM_Channel));
384 assert_param(IS_TIM_CC_PULSEWIDTH(Compare));
385
386 /* CCRx=0 will give 0% cycle pwm pulse */
387 PulseWidth = Compare;
388
389 tmpccmr = TIMx->CCMRx[TIM_Channel];
390
391 /* reset Compare val */
392 tmpccmr &= ~TIM_CCMode_CCR;
393
394 /* Set the Capture CompareX Register value */
395 tmpccmr |= (u32)PulseWidth;
396
397 /* set CCMR */
398 TIMx->CCMRx[TIM_Channel] = tmpccmr;
399 }
400
401 /**
402 * @brief Gets the TIMx Capture Compare X register value.
403 * @param TIMx: where x can be 4/5, to select the TIM peripheral.
404 * @param TIM_Channel: the channel to be read,
405 * which can be one of the following parameters @ref TIM_Channel_definitions.
406 * @retval Capture Compare x Register value.
407 * @note If you want to get pulse width of PWM, remember to plus 1 to
408 * the retval of this function.
409 * - TIMM05 has 6 channels: TIM_Channel_0-5.
410 * - TIM5 has 18 channels: TIM_Channel_0-17.
411 */
RTIM_CCRxGet(RTIM_TypeDef * TIMx,u16 TIM_Channel)412 u32 RTIM_CCRxGet(RTIM_TypeDef* TIMx, u16 TIM_Channel)
413 {
414 /* Check the parameters */
415 assert_param(IS_TIM_CCM_TIM(TIMx));
416 assert_param(IS_TIM_CHANNEL(TIM_Channel));
417
418 /* Get the Capture Compare x Register value */
419 return (TIMx->CCMRx[TIM_Channel] & TIM_CCMode_CCR);
420 }
421
422 /**
423 * @brief Enables or disables the TIMx peripheral Preload register on CCRx.
424 * @param TIMx: where x can be 5, to select the TIM peripheral.
425 * @param TIM_OCProtection: new state of the TIMx peripheral Preload register
426 * This parameter can be one of the following values:
427 * @arg TIM_OCPreload_Enable: value is loaded in the active register at each update event.
428 * @arg TIM_OCPreload_Disable: new value is taken in account immediately
429 * @param TIM_Channel: the channel need to be set,
430 * which can be one of the following parameters @ref TIM_Channel_definitions
431 * @note
432 * - TIMM05 has 6 channels: TIM_Channel_0-5.
433 * - TIM5 has 18 channels: TIM_Channel_0-17.
434 * @retval None
435 */
RTIM_OCxPreloadConfig(RTIM_TypeDef * TIMx,u32 TIM_OCProtection,u16 TIM_Channel)436 void RTIM_OCxPreloadConfig(RTIM_TypeDef* TIMx, u32 TIM_OCProtection, u16 TIM_Channel)
437 {
438 u32 tmpccmr = 0;
439
440 /* Check the parameters */
441 assert_param(IS_TIM_PWM_TIM(TIMx));
442 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCProtection));
443 assert_param(IS_TIM_CHANNEL(TIM_Channel));
444
445 tmpccmr = TIMx->CCMRx[TIM_Channel];
446
447 /* Reset the OC1PE Bit */
448 tmpccmr &= ~(TIM_OCER_CCxPE);
449
450 /* Enable or Disable the Output Compare Preload feature */
451 tmpccmr |= TIM_OCProtection;
452
453 /* Write to TIMx CCMR1 register */
454 TIMx->CCMRx[TIM_Channel] = tmpccmr;
455 }
456
457 /**
458 * @brief Configures the TIMx channel x polarity.
459 * @param TIMx: where x can be 5, to select the TIM peripheral.
460 * @param TIM_OCPolarity: specifies the OCx Polarity
461 * This parameter can be one of the following values:
462 * @arg TIM_CCPolarity_High: Output Compare active high
463 * @arg TIM_CCPolarity_Low: Output Compare active low
464 * @retval None
465 * @note
466 * -TIMM05 have CCR0-5
467 * -TIM5 have CCR0-17
468 * -TIM4/TIMM04 have CCR0
469 * -TIM0-3/TIMM00-3 dont have CCMR
470 */
RTIM_CCxPolarityConfig(RTIM_TypeDef * TIMx,u32 TIM_OCPolarity,u16 TIM_Channel)471 void RTIM_CCxPolarityConfig(RTIM_TypeDef* TIMx, u32 TIM_OCPolarity, u16 TIM_Channel)
472 {
473 u32 tmpccmr = 0;
474
475 /* Check the parameters */
476 assert_param(IS_TIM_PWM_TIM(TIMx));
477 assert_param(IS_TIM_CC_POLARITY(TIM_OCPolarity));
478 assert_param(IS_TIM_CHANNEL(TIM_Channel));
479
480 tmpccmr = TIMx->CCMRx[TIM_Channel];
481
482 /* Set or Reset the CCxP Bit */
483 tmpccmr &= ~(TIM_CCER_CCxP);
484 tmpccmr |= TIM_OCPolarity;
485
486 /* Write to TIMx CCER register */
487 TIMx->CCMRx[TIM_Channel] = tmpccmr;
488 }
489
490 /**
491 * @brief Enables or disables the TIM Capture Compare Channel x.
492 * @param TIMx: where x can be 4/5, to select the TIM peripheral.
493 * @param TIM_Channel: specifies the TIM Channel
494 * This parameter can be one of the following values @ref TIM_Channel_definitions
495 * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
496 * This parameter can be one of the following values:
497 * @arg TIM_CCx_Enable
498 * @arg TIM_CCx_Disable
499 * @note
500 * - TIMM05 has 6 channels: TIM_Channel_0-5.
501 * - TIM5 has 18 channels: TIM_Channel_0-17.
502 * @retval None
503 */
RTIM_CCxCmd(RTIM_TypeDef * TIMx,u16 TIM_Channel,u32 TIM_CCx)504 void RTIM_CCxCmd(RTIM_TypeDef* TIMx, u16 TIM_Channel, u32 TIM_CCx)
505 {
506 u32 tmpccmr = TIMx->CCMRx[TIM_Channel];
507
508 /* Check the parameters */
509 assert_param(IS_TIM_CCM_TIM(TIMx));
510 assert_param(IS_TIM_CHANNEL(TIM_Channel));
511 assert_param(IS_TIM_CCX(TIM_CCx));
512
513 tmpccmr &= ~TIM_CCER_CCxE;
514 tmpccmr |= TIM_CCx;
515
516 /* Set or reset the CCxE Bit */
517 TIMx->CCMRx[TIM_Channel] = tmpccmr;
518 }
519
520 /**
521 * @brief Set the TIMx's One Pulse Mode (output one pulse PWM mode).
522 * @param TIMx: where x can be 5 to select the TIM peripheral.
523 * @param TIM_OPMode: specifies the OPM Mode to be used.
524 * This parameter can be one of the following values:
525 * @arg TIM_OPMode_Single
526 * @arg TIM_OPMode_Repetitive
527 * @param TrigerPolarity: specifies the OPM Mode Triger Polarity.
528 * This parameter can be one of the following values:
529 * @arg TIM_OPMode_ETP_positive
530 * @arg TIM_OPMode_ETP_negative
531 * @note You must select TIM_OPMode_Single if you want to set One Pluse Mode,
532 * which makes the counter stop automatically at the next UEV.
533 * @retval None
534 */
RTIM_SetOnePulseOutputMode(RTIM_TypeDef * TIMx,u32 TIM_OPMode,u32 TrigerPolarity)535 void RTIM_SetOnePulseOutputMode(RTIM_TypeDef* TIMx, u32 TIM_OPMode, u32 TrigerPolarity)
536 {
537 /* Check the parameters */
538 assert_param(IS_TIM_ONE_PULSE_TIM(TIMx));
539 assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
540 assert_param(IS_TIM_OPM_ETP_MODE(TrigerPolarity));
541
542 /* Reset the OPM & ETP Bit */
543 TIMx->CR &= (u32)~(TIM_CR_OPM | TIM_CR_ETP);
544
545 /* Configure the OPM Mode */
546 TIMx->CR |= TIM_OPMode | TrigerPolarity;
547 }
548
549 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
550