1 /**
2 ******************************************************************************
3 * @file rtl8721d_uart.h
4 * @author
5 * @version V1.0.0
6 * @date 2016-05-17
7 * @brief This file contains all the functions prototypes for the UART firmware
8 * library.
9 ******************************************************************************
10 * @attention
11 *
12 * This module is a confidential and proprietary property of RealTek and
13 * possession or use of this module requires written permission of RealTek.
14 *
15 * Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
16 ******************************************************************************
17 */
18
19 #ifndef _RTL8710B_UART_H_
20 #define _RTL8710B_UART_H_
21
22 /** @addtogroup AmebaD_Periph_Driver
23 * @{
24 */
25
26 /** @defgroup UART
27 * @{
28 */
29
30 /** @addtogroup UART
31 * @verbatim
32 *****************************************************************************************
33 * Introduction
34 *****************************************************************************************
35 * KM4 UART0:
36 * - Base Address: UART0_DEV
37 * - IPclk: XTAL, normally is 40MHz
38 * - BaudRate: 110~6000000
39 * - Low Power Rx: Support
40 * - SocPs: SleepMode (clock gating & power gating)
41 * - Boot From UART without Flash
42 * - IRQ: UART0_IRQ
43 * - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_UART0_TX
44 * - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_UART0_RX
45 *
46 * KM4 UART1_BT: The same as KM4 UART0 except following
47 * - Base Address: UART1_DEV
48 * - IRQ: UART1_IRQ
49 * - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_UART1_TX
50 * - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_UART1_RX
51 *
52 * KM0 LUART: The same as KM4 UART0 except following
53 * - Base Address: UART3_DEV
54 * - IRQ: UARTLP_IRQ
55 * - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_UART3_TX
56 * - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_UART3_RX
57 *
58 * KM0 LOG UART: Used as loguart
59 * - Base Address: UART2_DEV
60 * - IPclk: XTAL, normally is 40MHz
61 * - BaudRate: 110~6000000, default set 115200 for log
62 * - Low Power Rx: Support
63 * - Flash Program use LOGUART
64 * - IRQ: UART_LOG_IRQ
65 *
66 *****************************************************************************************
67 * Low Power Rx
68 *****************************************************************************************
69 * All UART support
70 * UART can receive data when soc enter power save mode
71 * baudrate: 110~115200
72 *
73 *****************************************************************************************
74 * How to use Normal Uart
75 *****************************************************************************************
76 * To use the normal uart mode, the following steps are mandatory:
77 *
78 * 1. Enable peripheral clock and power(it is enable default):
79 * RCC_PeriphClockCmd(APBPeriph_UARTx, APBPeriph_UARTx_CLOCK, ENABLE);
80 *
81 * 2. configure the UART pinmux
82 * Pinmux_Config(Pin_Num, PINMUX_FUNCTION_UART)
83 *
84 * 3. Set default parameters, change some parameter if needed
85 * UART_StructInit(UART_InitTypeDef* UART_InitStruct)
86 *
87 * 4. init hardware use step3 parameters.
88 * UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef *UART_InitStruct)
89 *
90 * 5. Set Baud Rate.
91 * UART_SetBaud(UART_TypeDef* UARTx, u32 BaudRate)
92 *
93 * 6. Enable IRQ using following function if needed
94 * UART_INTConfig(): UART IRQ Mask set
95 * InterruptRegister(): register the uart irq handler
96 * InterruptEn(): Enable the NVIC interrupt
97 *
98 * 7. Enable uart rx path:
99 * UART_RxCmd().
100 *
101 * @note in UART_Normal_functions group, these functions below are about Interrupts
102 * and flags management.
103 * UART_INTConfig()
104 * UART_IntStatus()
105 * UART_LineStatusGet()
106 *
107 *****************************************************************************************
108 * How to use uart in DMA mode
109 *****************************************************************************************
110 * To use the uart in DMA mode, the following steps are mandatory:
111 *
112 * 1. Enable peripheral clock and power(it is enable default):
113 * RCC_PeriphClockCmd(APBPeriph_UARTx, APBPeriph_UARTx_CLOCK, ENABLE);
114 *
115 * 2. configure the UART pinmux
116 * Pinmux_Config(Pin_Num, PINMUX_FUNCTION_UART)
117 *
118 * 3. Set default parameters, and change DMA mode open UART_InitStruct
119 * UART_StructInit(UART_InitTypeDef* UART_InitStruct)
120 *
121 * 4. init hardware use step3 parameters.
122 * UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef *UART_InitStruct)
123 *
124 * 5. Set Baud Rate.
125 * UART_SetBaud(UART_TypeDef* UARTx, u32 BaudRate)
126 *
127 * 6. Enable uart rx path:
128 * UART_RxCmd().
129 *
130 * 7. Configure the uart DMA burst size:
131 * UART_TXDMAConfig()
132 * UART_RXDMAConfig().
133 *
134 * 8. Active the UART TX/RX DMA Request:
135 * UART_TXDMACmd()
136 * UART_RXDMACmd().
137 *
138 * 9. GDMA related configurations(source address/destination address/block size etc.).
139 * UART_TXGDMA_Init()
140 * UART_RXGDMA_Init()
141 *
142 *****************************************************************************************
143 * How to use uart in Low Power mode
144 *****************************************************************************************
145 * To use the uart in Low Power mode, the following steps are mandatory:
146 *
147 * 1. Enable peripheral clock and power(it is enable default):
148 * RCC_PeriphClockCmd(APBPeriph_UARTx, APBPeriph_UARTx_CLOCK, ENABLE);
149 *
150 * 2. configure the UART pinmux
151 * Pinmux_Config(Pin_Num, PINMUX_FUNCTION_UART)
152 *
153 * 3. Set default parameters, change some parameter if needed
154 * UART_StructInit(UART_InitTypeDef* UART_InitStruct)
155 *
156 * 4. init hardware use step3 parameters.
157 * UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef *UART_InitStruct)
158 *
159 * 5. Set Baud Rate.
160 * UART_SetBaud(UART_TypeDef* UARTx, u32 BaudRate)
161 *
162 * 6. Enable IRQ using following function if needed
163 * UART_INTConfig(): UART IRQ Mask set
164 * InterruptRegister(): register the uart irq handler
165 * InterruptEn(): Enable the NVIC interrupt
166 *
167 * 7. Configure monitor parameters:
168 * UART_MonitorParaConfig();
169 *
170 * 8. Enable monitor function if needed.
171 * UART_RxMonitorCmd()
172 *
173 * 9. Set lower power clock source
174 * RCC_PeriphClockSource_UART (UART_TypeDef* UARTx, u32 Source)
175 *
176 * 10. Set the low power RX Baud Rate
177 * UART_LPRxBaudSet(UART_TypeDef* UARTx, u32 BaudRate, u32 RxIPClockHz)
178 *
179 * 11. Enable uart rx path:
180 * UART_RxCmd().
181 *
182 * @note when uart work in low power rx mode, clock source can switch between
183 * XTAL and OSC. As for how and when to excute switching action,
184 * refer to related uart specifications for more details.
185 *
186 * @note Besides, if more details about the uart low power rx path contens is needed,
187 * please refer to uart specifications.
188 *
189 *****************************************************************************************
190 * How to use uart in IrDA mode
191 *****************************************************************************************
192 * To use the uart in IrDA mode, the following steps are mandatory:
193 *
194 * 1. Enable peripheral clock and power(it is enable default):
195 * RCC_PeriphClockCmd(APBPeriph_UARTx, APBPeriph_UARTx_CLOCK, ENABLE);
196 *
197 * 2. configure the pinmux:
198 * Pinmux_Config(Pin_Num, PINMUX_FUNCTION_UART)
199 *
200 * 3. Disable rx path:
201 * UART_RxCmd().
202 *
203 * 4. Program the IrDA tx pulse width and location and IrDA rx pulse filter:
204 * UART_IrDAStructInit(IrDA_InitTypeDef * IrDA_InitStruct)
205 *
206 * 5. Init Hardware:
207 * UART_IrDAInit(UART_TypeDef* UARTx, IrDA_InitTypeDef * IrDA_InitStruct).
208 *
209 * 6. Enable the IrDA function:
210 * UART_IrDACmd().
211 *
212 * 7. According to the IrDA SIR protocol data format requrement, program Word Length,
213 * Stop Bit, Parity and DMA Mode(ENABLE/DISABLE):
214 * UART_StructInit(UART_InitTypeDef* UART_InitStruct)
215 * UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef *UART_InitStruct)
216 *
217 * 8. Program the Baud Rate:
218 * UART_SetBaud().
219 *
220 * 9. Enable IRQ if needed:
221 * UART_INTConfig(): UART IRQ Mask set
222 * InterruptRegister(): register the uart irq handler
223 * InterruptEn(): Enable the NVIC interrupt
224 *
225 * 10. Enable uart rx path:
226 * UART_RxCmd().
227 *
228 * @note AmebaD IrDA just support IrDA SIR protocol, setting baud rate is no more than
229 * 115200 bps.
230 *
231 * @note because IrDA transfers data using infrared carrier and for the property of the
232 * IrDA transceiver, IrDA just work in half duplex mode. For details, refer to the IrDA
233 * protocol specification.
234 *****************************************************************************************
235 * @endverbatim
236 */
237
238 /* Exported Types --------------------------------------------------------*/
239
240 /** @defgroup UART_Exported_Types UART Exported Types
241 * @{
242 */
243
244 /**
245 * @brief UART Init structure definition
246 */
247 typedef struct
248 {
249 u32 DmaModeCtrl; /*!< Specifies the uart DMA mode state.
250 This parameter can be ENABLE or DISABLE. */
251
252 u32 WordLen; /*!< Specifies the UART word length.
253 This parameter can be a value of @ref UART_Word_length_define. */
254
255 u32 StopBit; /*!< Specifies the UART stop bit number.
256 This parameter can be a value of @ref UART_Stop_Bit_define. */
257
258 u32 Parity; /*!< Specifies the UART parity.
259 This parameter can be a value of @ref UART_Parity_Enable_define. */
260
261 u32 ParityType; /*!< Specifies the UART parity type.
262 This parameter can be a value of @ref UART_Parity_Type_define. */
263
264 u32 StickParity; /*!< Specifies the UART stick parity.
265 This parameter can be a value of @ref UART_Stick_Parity_Type_define. */
266
267 u32 FlowControl; /*!< Specifies the UART auto flow control.
268 This parameter can be ENABLE or DISABLE. */
269
270 u32 RxFifoTrigLevel; /*!< Specifies the UART rx fifo trigger level.
271 This parameter can be a value of @ref UART_RX_FIFO_TRIGGER_LEVEL_define. */
272
273 u32 RxErReportCtrl; /*!< Specifies the UART rx error report control.
274 This parameter can be a value of @ref UART_Rx_Err_Report_define. */
275
276 u32 RxTimeOutCnt; /*!< Specifies the UART rx time out counter.
277 This parameter can be a number between 0x00 and 0xffff.. */
278 } UART_InitTypeDef;
279
280 /**
281 * @brief UART IRDA Init structure definition
282 *
283 */
284 typedef struct
285 {
286 u32 UART_IrDARxInv; /*!< Specifies the uart irda rx invert control.
287 This parameter can be ENABLE or DISABLE.
288 ENABLE: invert the irda input signal.
289 DISABLE: does't invert the irda input signal.
290 @note This parameter is only used in IrDA mode. */
291
292 u32 UART_IrDATxInv; /*!< Specifies the uart irda tx invert control.
293 This parameter can be ENABLE or DISABLE.
294 ENABLE: invert the irda output signal.
295 DISABLE: does't invert the irda output signal.
296 @note This parameter is only used in IrDA mode. */
297
298 u32 UART_UpperShift; /*!< Specifies the uart irda tx pulse right edge shift direction.
299 This parameter can be a value of @ref UART_IRDA_PULSE_SHIFT_define. */
300
301 u32 UART_UpperShiftVal; /*!< Specifies the uart irda tx pulse right edge shift value in the given direction.
302 This parameter can be a number between 0x0000 and 0x7fff. */
303
304 u32 UART_LowShift; /*!< Specifies the uart irda tx pulse left edge shift direction.
305 This parameter can be a value of @ref UART_IRDA_PULSE_SHIFT_define. */
306
307 u32 UART_LowShiftVal; /*!< Specifies the uart irda tx pulse left edge shift value in the given direction.
308 This parameter can be a number between 0x0000 and 0x7fff. */
309
310 u32 UART_RxFilterThres; /*!< Specifies the uart irda rx filter threshold.
311 This parameter can be a number between 0x0000 and 0x7fff
312 @note This parameter is only used in IrDA mode. */
313
314 u32 UART_RxFilterCmd; /*!< Specifies the uart irda rx filter control.
315 This parameter can be ENABLE or DISABLE.
316 ENABLE: uart IrDA rx filter is used.
317 DISABLE: uart IrDA rx filter is not used.
318 @note This parameter is only used in IrDA mode. */
319 }IrDA_InitTypeDef;
320 /**
321 * @}
322 */
323
324 /* Exported constants --------------------------------------------------------*/
325 /** @defgroup UART_Exported_Constants UART Exported Constants
326 * @{
327 */
328
329 /** @defgroup UART_IRDA_PULSE_SHIFT_define
330 * @{
331 */
332 #define UART_IRDA_PULSE_LEFT_SHIFT ((u32)0x00000000)
333 #define UART_IRDA_PULSE_RIGHT_SHIFT ((u32)0x00000001)
334 #define IS_IRDA_PUL_SHIFT(SHIFT) (((SHIFT) == UART_IRDA_PULSE_LEFT_SHIFT) || \
335 ((SHIFT) == UART_IRDA_PULSE_RIGHT_SHIFT))
336
337 /**
338 * @}
339 */
340
341 /** @defgroup UART_RX_FIFO_TRIGGER_LEVEL_define
342 * @{
343 */
344
345 #define UART_RX_FIFOTRIG_LEVEL_1BYTES ((u32)0x00000000)
346 #define UART_RX_FIFOTRIG_LEVEL_4BYTES ((u32)0x00000040)
347 #define UART_RX_FIFOTRIG_LEVEL_8BYTES ((u32)0x00000080)
348 #define UART_RX_FIFOTRIG_LEVEL_14BYTES ((u32)0x000000c0)
349
350 #define IS_UART_RXFIFO_LEVEL(LEVEL) (((LEVEL) == UART_RX_FIFOTRIG_LEVEL_1BYTES) || \
351 ((LEVEL) == UART_RX_FIFOTRIG_LEVEL_4BYTES) || \
352 ((LEVEL) == UART_RX_FIFOTRIG_LEVEL_8BYTES) || \
353 ((LEVEL) == UART_RX_FIFOTRIG_LEVEL_14BYTES))
354
355 /**
356 * @}
357 */
358
359 /** @defgroup UART_Word_length_define
360 * @{
361 */
362
363 #define RUART_WLS_7BITS ((u32)0x00000000)
364 #define RUART_WLS_8BITS ((u32)0x00000001)
365
366 #define IS_UART_WLS(VAL) (((VAL) == RUART_WLS_7BITS) || \
367 ((VAL) == RUART_WLS_8BITS))
368
369 /**
370 * @}
371 */
372
373 /** @defgroup UART_Stop_Bit_define
374 * @{
375 */
376
377 #define RUART_STOP_BIT_1 ((u32)0x00000000)
378 #define RUART_STOP_BIT_2 ((u32)0x00000001)
379
380 #define IS_UART_STOP_BIT(VAL) (((VAL) == RUART_STOP_BIT_1) || \
381 ((VAL) == RUART_STOP_BIT_2))
382
383 /**
384 * @}
385 */
386
387 /** @defgroup UART_Parity_Enable_define
388 * @{
389 */
390
391 #define RUART_PARITY_DISABLE ((u32)0x00000000)
392 #define RUART_PARITY_ENABLE ((u32)0x00000001)
393
394 #define IS_UART_PARITY_ENABLE(VAL) (((VAL) == RUART_PARITY_DISABLE) || \
395 ((VAL) == RUART_PARITY_ENABLE))
396
397 /**
398 * @}
399 */
400
401 /** @defgroup UART_Parity_Type_define
402 * @{
403 */
404
405 #define RUART_ODD_PARITY ((u32)0x00000000)
406 #define RUART_EVEN_PARITY ((u32)0x00000001)
407
408 #define IS_UART_PARITY_TYPE(VAL) (((VAL) == RUART_ODD_PARITY) || \
409 ((VAL) == RUART_EVEN_PARITY))
410
411 /**
412 * @}
413 */
414
415 /** @defgroup UART_Stick_Parity_Type_define
416 * @{
417 */
418
419 #define RUART_STICK_PARITY_DISABLE ((u32)0x00000000)
420 #define RUART_STICK_PARITY_ENABLE ((u32)0x00000001)
421
422 #define IS_UART_STICK_PARITY_ENABLE(VAL) (((VAL) == RUART_STICK_PARITY_DISABLE) || \
423 ((VAL) == RUART_STICK_PARITY_ENABLE))
424
425 /**
426 * @}
427 */
428
429 /** @defgroup UART_Interrupt_ID_define
430 * @{
431 */
432
433 #define RUART_MODEM_STATUS ((u32)0x00000000)
434 #define RUART_TX_FIFO_EMPTY ((u32)0x00000001)
435 #define RUART_RECEIVER_DATA_AVAILABLE ((u32)0x00000002)
436 #define RUART_RECEIVE_LINE_STATUS ((u32)0x00000003)
437 #define RUART_LP_RX_MONITOR_DONE ((u32)0x00000004)
438 #define RUART_TIME_OUT_INDICATION ((u32)0x00000006)
439
440 /**
441 * @}
442 */
443
444 /** @defgroup UART_RX_Clock_Source_define
445 * @{
446 */
447
448 #define UART_RX_CLK_XTAL_40M ((u32)0x00000000)
449 #define UART_RX_CLK_OSC_LP ((u32)0x00000001)
450 #define UART_RX_CLK_XTAL_LP ((u32)0x00000002)
451 #define IS_UART_RX_CLK(CLK) (((CLK) == UART_RX_CLK_XTAL_40M) || \
452 ((CLK) == UART_RX_CLK_XTAL_LP) || \
453 ((CLK) == UART_RX_CLK_OSC_LP))
454 /**
455 * @}
456 */
457
458 /** @defgroup UART_Rx_Err_Report_define
459 * @{
460 */
461
462 #define UART_RX_EEROR_REPORT_DISABLE ((u32)0x00000000)
463 #define UART_RX_EEROR_REPORT_ENABLE ((u32)0x00000001)
464
465 #define IS_UART_RX_ERROR_REPORT(REPORT) (((REPORT) == UART_RX_EEROR_REPORT_DISABLE) || \
466 ((REPORT) == UART_RX_EEROR_REPORT_ENABLE) )
467
468 /**
469 * @}
470 */
471
472 /** @defgroup UART_Low_Power_Peripheral_define
473 * @{
474 */
475 #define IS_LPUART_PERIPH(PERIPH) (((PERIPH) == UART0_DEV) || ((PERIPH) == UART2_DEV) || ((PERIPH) == UART3_DEV))
476 /**
477 * @}
478 */
479
480 /** @defgroup UART_SoftWare_Status_define
481 * @{
482 */
483 #define STATETX_DMA 1
484 #define STATETX_INT 2
485 #define STATETX_POLL 3
486 #define STATERX_DMA 1
487 #define STATERX_INT 2
488 #define STATERX_POLL 3
489 /**
490 * @}
491 */
492
493
494 /**
495 * @}
496 */
497
498 /* Exported functions --------------------------------------------------------*/
499 /** @defgroup UART_Exported_Functions UART Exported Functions
500 * @{
501 */
502 /** @defgroup UART_Normal_functions
503 * @{
504 */
505 _LONG_CALL_ void UART_DeInit(UART_TypeDef* UARTx);
506 _LONG_CALL_ void UART_StructInit(UART_InitTypeDef* UART_InitStruct);
507 _LONG_CALL_ void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef *UART_InitStruct);
508 _LONG_CALL_ u32 UART_BaudParaGet(u32 baudrate, u32 *ovsr, u32 *ovsr_adj);
509 _LONG_CALL_ void UART_BaudParaGetFull(u32 IPclk, u32 baudrate, u32 *ovsr, u32 *ovsr_adj);
510 _LONG_CALL_ void UART_SetBaudExt(UART_TypeDef* UARTx, u32 Ovsr, u32 Ovsr_adj);
511 _LONG_CALL_ void UART_SetBaud(UART_TypeDef* UARTx, u32 BaudRate);
512 _LONG_CALL_ void UART_SetRxLevel(UART_TypeDef* UARTx, u32 FifoLv);
513 _LONG_CALL_ void UART_RxCmd(UART_TypeDef* UARTx, u32 NewState);
514 _LONG_CALL_ u32 UART_Writable(UART_TypeDef* UARTx);
515 _LONG_CALL_ u32 UART_Readable(UART_TypeDef* UARTx);
516 _LONG_CALL_ void UART_CharPut(UART_TypeDef* UARTx, u8 TxData);
517 _LONG_CALL_ void UART_CharGet(UART_TypeDef* UARTx, u8 *pRxByte);
518 _LONG_CALL_ void UART_ReceiveData(UART_TypeDef* UARTx, u8* OutBuf, u32 Count);
519 _LONG_CALL_ void UART_SendData(UART_TypeDef* UARTx, u8* InBuf, u32 Count);
520 _LONG_CALL_ u32 UART_ReceiveDataTO(UART_TypeDef* UARTx, u8* OutBuf, u32 Count, u32 Times);
521 _LONG_CALL_ u32 UART_SendDataTO(UART_TypeDef* UARTx,u8* InBuf,u32 Count, u32 Times);
522 _LONG_CALL_ void UART_RxByteCntClear(UART_TypeDef* UARTx);
523 _LONG_CALL_ u32 UART_RxByteCntGet(UART_TypeDef* UARTx);
524 _LONG_CALL_ void UART_BreakCtl(UART_TypeDef* UARTx, u32 NewState);
525 _LONG_CALL_ u32 UART_ClearRxFifo(UART_TypeDef* UARTx);
526 _LONG_CALL_ void UART_ClearTxFifo(UART_TypeDef* UARTx);
527 _LONG_CALL_ void UART_INTConfig(UART_TypeDef* UARTx, u32 UART_IT, u32 newState);
528 _LONG_CALL_ u32 UART_IntStatus(UART_TypeDef* UARTx);
529 _LONG_CALL_ u32 UART_ModemStatusGet(UART_TypeDef* UARTx);
530 _LONG_CALL_ u32 UART_LineStatusGet(UART_TypeDef* UARTx);
531 _LONG_CALL_ void UART_WaitBusy(UART_TypeDef* UARTx, u32 PollTimes);
532 /**
533 * @}
534 */
535
536 /** @defgroup UART_DMA_functions
537 * @{
538 */
539 _LONG_CALL_ void UART_TXDMAConfig(UART_TypeDef* UARTx, u32 TxDmaBurstSize);
540 _LONG_CALL_ void UART_RXDMAConfig(UART_TypeDef* UARTx, u32 RxDmaBurstSize);
541 _LONG_CALL_ void UART_TXDMACmd(UART_TypeDef* UARTx, u32 NewState);
542 _LONG_CALL_ void UART_RXDMACmd(UART_TypeDef* UARTx, u32 NewState);
543 _LONG_CALL_ BOOL UART_TXGDMA_Init(u8 UartIndex, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pTxBuf, int TxCount);
544 _LONG_CALL_ BOOL UART_RXGDMA_Init(u8 UartIndex, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pRxBuf, int RxCount);
545 /**
546 * @}
547 */
548
549 /** @defgroup UART_Low_Power_functions
550 * @{
551 */
552 _LONG_CALL_ void UART_MonitorParaConfig(UART_TypeDef* UARTx, u32 BitNumThres, u32 OscPerbitUpdCtrl);
553 _LONG_CALL_ void UART_LPRxBaudSet(UART_TypeDef* UARTx, u32 BaudRate, u32 RxIPClockHz);
554 _LONG_CALL_ void UART_RxMonitorCmd(UART_TypeDef* UARTx, u32 NewState);
555 _LONG_CALL_ u32 UART_RxMonBaudCtrlRegGet(UART_TypeDef* UARTx);
556 _LONG_CALL_ u32 UART_RxMonitorSatusGet(UART_TypeDef* UARTx);
557 /**
558 * @}
559 */
560
561 /** @defgroup UART_IRDA_functions
562 * @{
563 */
564 _LONG_CALL_ void UART_IrDAStructInit(IrDA_InitTypeDef * IrDA_InitStruct);
565 _LONG_CALL_ void UART_IrDAInit(UART_TypeDef* UARTx, IrDA_InitTypeDef * IrDA_InitStruct);
566 _LONG_CALL_ void UART_IrDACmd(UART_TypeDef* UARTx, u32 NewState);
567 /**
568 * @}
569
570 */
571 /**
572 * @}
573 */
574
575
576
577
578 /* Registers Definitions --------------------------------------------------------*/
579 /**************************************************************************//**
580 * @defgroup UART_Register_Definitions UART Register Definitions
581 * @{
582 *****************************************************************************/
583
584 /**************************************************************************//**
585 * @defgroup UART_DLH_INTCR
586 * @{
587 *****************************************************************************/
588 #define RUART_IER_ERBI ((u32)0x00000001) /*BIT[0], Enable received data available interrupt (rx trigger)*/
589 #define RUART_IER_ETBEI ((u32)0x00000001<<1) /*BIT[1], Enable transmitter FIFO empty interrupt (tx fifo empty)*/
590 #define RUART_IER_ELSI ((u32)0x00000001<<2) /*BIT[2], Enable receiver line status interrupt (receiver line status)*/
591 #define RUART_IER_EDSSI ((u32)0x00000001<<3) /*BIT[3], Enable modem status interrupt (modem status transition)*/
592 #define RUART_IER_EDMI ((u32)0x00000001<<4) /*BIT[4], Enable low power rx monitor done interrupt (monitor done)*/
593 #define RUART_IER_ETOI ((u32)0x00000001<<5) /*BIT[5], Enable rx time out interrupt*/
594 /** @} */
595
596 /**************************************************************************//**
597 * @defgroup UART_INTID
598 * @{
599 *****************************************************************************/
600 #define RUART_IIR_INT_PEND ((u32)0x00000001) /*uart interrupt global status*/
601 #define RUART_IIR_INT_ID ((u32)0x00000007<<1) /*Uart Interrupt ID mask, register INTID[3:1]*/
602 /** @} */
603
604 /**************************************************************************//**
605 * @defgroup UART_FCR
606 * @{
607 *****************************************************************************/
608 #define RUART_FIFO_CTL_RX_ERR_RPT ((u32)0x00000001) /*BIT[0], 0x01, RX error report control bit*/
609 #define RUART_FIFO_CTL_REG_CLEAR_RXFIFO ((u32)0x00000001<<1) /*BIT[1], 0x02, Write 1 clear*/
610 #define RUART_FIFO_CTL_REG_CLEAR_TXFIFO ((u32)0x00000001<<2) /*BIT[2], 0x04, Write 1 clear*/
611 #define RUART_FIFO_CTL_REG_DMA_ENABLE ((u32)0x00000001<<3) /*BIT[3], 0x08, Uart DMA control bit*/
612 #define RUART_FIFO_CTL_REG_RX_TRG_LEV ((u32)0x00000003<<6) /*BIT[7:6], 0xc0, Uart rx trigger level field*/
613 /** @} */
614
615 /**************************************************************************//**
616 * @defgroup UART_MCR
617 * @{
618 *****************************************************************************/
619 #define RUART_MCL_FLOW_ENABLE ((u32)((0x00000001 << 5) | (0x00000001 << 1))) /*BIT[1],BIT[5],Uart auto flow control enable bit*/
620 /** @} */
621
622 /**************************************************************************//**
623 * @defgroup UART_LCR
624 * @{
625 *****************************************************************************/
626 #define BIT_UART_LCR_BREAK_CTRL ((u32)0x00000001<<6) /*BIT[6], Uart break control function enable bit*/
627 #define RUART_LINE_CTL_REG_DLAB_ENABLE ((u32)0x00000001<<7) /*BIT[7], 0x80*/
628 /** @} */
629
630 /**************************************************************************//**
631 * @defgroup UART_LSR
632 * @{
633 *****************************************************************************/
634 #define RUART_LINE_STATUS_REG_DR ((u32)0x00000001) /*BIT[0], Data ready indicator*/
635 #define RUART_LINE_STATUS_ERR_OVERRUN ((u32)0x00000001<<1) /*BIT[1], Over run*/
636 #define RUART_LINE_STATUS_ERR_PARITY ((u32)0x00000001<<2) /*BIT[2], Parity error*/
637 #define RUART_LINE_STATUS_ERR_FRAMING ((u32)0x00000001<<3) /*BIT[3], Framing error*/
638 #define RUART_LINE_STATUS_ERR_BREAK ((u32)0x00000001<<4) /*BIT[4], Break interrupt error*/
639 #define RUART_LINE_STATUS_REG_THRE ((u32)0x00000001<<5) /*BIT[5], 0x20, Transmit holding register empty interrupt enable*/
640 #define RUART_LINE_STATUS_REG_TEMT ((u32)0x00000001<<6) /*BIT[6], 0x40, Transmitter empty indicator(bit)*/
641 #define RUART_LINE_STATUS_ERR_RXFIFO ((u32)0x00000001<<7) /*BIT[7], RX FIFO error*/
642 #define RUART_LINE_STATUS_ERR (RUART_LINE_STATUS_ERR_OVERRUN |RUART_LINE_STATUS_ERR_PARITY| \
643 RUART_LINE_STATUS_ERR_FRAMING|RUART_LINE_STATUS_ERR_BREAK| \
644 RUART_LINE_STATUS_ERR_RXFIFO) /*Line status error*/
645 /** @} */
646
647 /**************************************************************************//**
648 * @defgroup UART_SPR
649 * @{
650 *****************************************************************************/
651 #define RUART_SP_REG_RXBREAK_INT_STATUS ((u32)0x00000001<<7) /*BIT[7], 0x80, Write 1 clear*/
652 #define RUART_SP_REG_DBG_SEL ((u32)0x0000000F<<8) /*BIT[11:8], Debug port selection*/
653 #define RUART_SP_REG_XFACTOR_ADJ ((u32)0x000007FF<<16) /*BIT[26:16], ovsr_adj parameter field*/
654 /** @} */
655
656 /**************************************************************************//**
657 * @defgroup UART_STSR
658 * @{
659 *****************************************************************************/
660 //#define RUART_STS_REG_RESET_RCV ((u32)0x00000001<<3) /*BIT[3], 0x08, Reset uart receiver*/
661 #define RUART_STS_REG_XFACTOR ((u32)0x000FFFFF<<4) /*BIT[23:4]ovsr parameter field*/
662 /** @} */
663
664 /**************************************************************************//**
665 * @defgroup UART_MISCR
666 * @{
667 *****************************************************************************/
668 #define RUART_IRDA_ENABLE ((u32)0x00000001) /*BIT[0], Enable IrDA*/
669
670 #define RUART_IRDA_TX_INVERT ((u32)0x00000001 << 13) /*BIT[13], Enable IrDA tx invert*/
671
672 #define RUART_IRDA_RX_INVERT ((u32)0x00000001 << 14) /*BIT[14], Enable IrDA rx invert*/
673
674 #define RUART_TXDMA_BURSTSIZE_MASK ((u32)0x0000001F << 3) /*BIT[7:3], Uart tx DMA burst size mask.
675 This field value must be no more than 16.
676 Because tx fifo depth is 16 in UART IP hardware*/
677
678 #define RUART_RXDMA_BURSTSIZE_MASK ((u32)0x0000001F << 8) /*BIT[12:8], Uart rx DMA burst size mask.
679 This field value must be no more than 16.
680 Because rx fifo depth is 16 in uart IP hardware*/
681
682 #define RUART_TXDMA_ENABLE ((u32)0x00000001 << 1) /*BIT[1], Uart tx DMA enable bit*/
683 #define RUART_RXDMA_ENABLE ((u32)0x00000001 << 2) /*BIT[2], Uart rx DMA enable bit*/
684
685 #define RUART_RXDMA_OWNER ((u32)0x00000001 << 15) /*BIT[15], the DMA flow controller selection(UART or DMA)*/
686 #define RUART_RXDMA_DUMMY_DATA ((u32)0x000000FF << 16) /*BIT[23:16], dummy data when uart is the flow controller*/
687 #define RUART_RXDMA_DUMMY_FLAG ((u32)0x00000001 << 24) /*BIT[24], this bit is set when master read dummy data from UART RX FIFO, it can be cleared by software
688 by writing 1 to this bit*/
689
690 /** @} */
691
692 /**************************************************************************//**
693 * @defgroup UART_TXPLSR
694 * @{
695 *****************************************************************************/
696 #define RUART_IRDA_TX_PUL_LOW_BUND_VAL ((u32)0x00007FFF) /*BIT[14:0], IrDA tx pulse low bound edge shift value*/
697
698 #define RUART_IRDA_TX_PUL_LOW_BUND_SHIFT ((u32)0x00000001 << 15) /*BIT[15], IrDA tx pulse low bound edge shift direction*/
699
700 #define RUART_IRDA_TX_PUL_UP_BUND_VAL ((u32)0x00007FFF << 16) /*BIT[30:16], IrDA tx pulse upper bound edge shift value*/
701
702 #define RUART_IRDA_TX_PUL_UP_BUND_SHIFT ((u32)0x00000001 << 31) /*BIT[31], IrDA tx pulse upper bound edge shift direction*/
703 /** @} */
704
705 /**************************************************************************//**
706 * @defgroup UART_RXPLSR
707 * @{
708 *****************************************************************************/
709 #define RUART_IRDA_RX_FILTER_ENABLE ((u32)0x00000001) /*BIT[0], IrDA rx filter enable*/
710
711 #define RUART_IRDA_RX_FILTER_THRES ((u32)0x00007FFF << 1) /*BIT[15:1], IrDA rx filter threshold field*/
712 /** @} */
713
714 /**************************************************************************//**
715 * @defgroup UART_REG_RX_PATH_CTRL
716 * @{
717 *****************************************************************************/
718 #define RUART_REG_LP_RX_PATH_SELECT ((u32)0x00000001) /*BIT[0], 0x01, Select uart low power rx path*/
719 #define RUART_REG_LP_RX_PATH_RESET ((u32)0x00000001 << 2) /*BIT[2], 0x40, Reset uart low power rx path receiver*/
720 #define RUART_REG_RX_XFACTOR_ADJ ((u32)0x000007FF << 3) /*BIT[13:3], One factor of Baud rate calculation for rx path, similar with xfactor_adj */
721 #define RUART_REG_RX_TO_THRES ((u32)0x0000FFFF<<16) /*BIT[31:16], rx timeout threshold, unit is one bit period*/
722 /** @} */
723
724 /**************************************************************************//**
725 * @defgroup UART_REG_MON_BAUD_CTRL
726 * @{
727 *****************************************************************************/
728 #define RUART_LP_RX_MON_ENABLE ((u32)0x00000001) /*BIT[0], 0x01, Enable low power rx monitor function*/
729 #define RUART_LP_RX_BIT_NUM_THRES ((u32)0x000000FF << 1) /*BIT[8:1], Bit Number threshold of one monitor period*/
730 #define RUART_LP_RX_OSC_CYCNUM_PERBIT ((u32)0x000FFFFF << 9) /*BIT[28:9], Cycle number perbit for osc clock */
731 #define RUART_LP_RX_OSC_UPD_IN_XTAL ((u32)0x00000001 << 29) /*BIT[29], Control bit for osc monitor parameter update */
732 /** @} */
733
734 /**************************************************************************//**
735 * @defgroup UART_REG_MON_BAUD_STS
736 * @{
737 *****************************************************************************/
738 #define RUART_LP_RX_XTAL_CYCNUM_PERBIT ((u32)0x000FFFFF) /*BIT[19:0], Cycle number perbit for xtal clock */
739 #define RUART_LP_RX_MON_RDY ((u32)0x00000001 << 20) /*BIT[20], Monitor ready status*/
740 #define RUART_LP_RX_MON_TOTAL_BITS ((u32)0x0000000F << 21) /*BIT[28:21], Actualy monitor bit number */
741 /** @} */
742
743 /**************************************************************************//**
744 * @defgroup UART_REG_RX_BYTE_CNT
745 * @{
746 *****************************************************************************/
747 /******************** Bits definition for register *******************/
748 #define RUART_RX_READ_BYTE_CNTER ((u32)0x0000FFFF) /*BIT[15:0], Byte number of data read from rx fifo */
749 #define RUART_RX_BYTE_CNTER_CLEAR ((u32)0x00000001 << 16) /*BIT[16], Write 1 clear rx byte counter*/
750 /** @} */
751 /** @} */
752
753 /**
754 * @}
755 */
756
757 /**
758 * @}
759 */
760
761 /* Other Definitions --------------------------------------------------------*/
762 typedef struct
763 {
764 u32 LOW_POWER_RX_ENABLE; /*Enable low power RX*/
765 } UARTCFG_TypeDef;
766
767 typedef struct
768 {
769 UART_TypeDef* UARTx;
770 u32 Tx_HandshakeInterface;
771 u32 Rx_HandshakeInterface;
772 IRQn_Type IrqNum;
773 } UART_DevTable;
774
775 extern UARTCFG_TypeDef uart_config[];
776 extern const UART_DevTable UART_DEV_TABLE[4];
777 extern u32 UART_StateTx[4];
778 extern u32 UART_StateRx[4];
779
780 #define MAX_UART_INDEX (4)
781
782 static inline void
UART_SetTxFlag(u32 UartIdx,u32 Flag)783 UART_SetTxFlag(u32 UartIdx, u32 Flag)
784 {
785 UART_StateTx[UartIdx] = Flag;
786 }
787
788 static inline void
UART_SetRxFlag(u32 UartIdx,u32 Flag)789 UART_SetRxFlag(u32 UartIdx, u32 Flag)
790 {
791 UART_StateRx[UartIdx] = Flag;
792 }
793
794 static inline u32
UART_GetTxFlag(u32 UartIdx)795 UART_GetTxFlag(u32 UartIdx)
796 {
797 return (UART_StateTx[UartIdx]);
798 }
799
800 static inline u32
UART_GetRxFlag(u32 UartIdx)801 UART_GetRxFlag(u32 UartIdx)
802 {
803 return (UART_StateRx[UartIdx]);
804 }
805 #endif
806 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
807