1 /**
2 ******************************************************************************
3 * @file rtl8721dhp_sdio.c
4 * @author
5 * @version V1.0.0
6 * @date 2016-05-17
7 * @brief This file provides firmware functions to manage the
8 * functionalities of the SDIO device peripheral:
9 ******************************************************************************
10 * @attention
11 *
12 * This module is a confidential and proprietary property of RealTek and
13 * possession or use of this module requires written permission of RealTek.
14 *
15 * Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
16 ******************************************************************************
17 */
18
19 #include "ameba_soc.h"
20
21 /**
22 * @brief Fills each SDIO_InitStruct member with its default value.
23 * @param SDIO_InitStruct: pointer to a SDIO_InitTypeDef structure which will be
24 * initialized.
25 * @retval None
26 */
27
SDIO_StructInit(SDIO_InitTypeDef * SDIO_InitStruct)28 void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
29 {
30 /* TXBD */
31 SDIO_InitStruct->TXBD_BAR = (u32)NULL; /* init txbd_bar */
32 SDIO_InitStruct->TXBD_RING_SIZE = 20; /* init TXBD ring size */
33 SDIO_InitStruct->TX_BUFFER_SIZE = 0xFF; /* init txbuf_size */
34
35 /* RXBD */
36 SDIO_InitStruct->RXBD_BAR = (u32)NULL; /* init rxbd_bar reg */
37 SDIO_InitStruct->RXBD_RING_SIZE = 32; /* init rxbd ring size */
38 SDIO_InitStruct->RXBD_FREE_TH = 5; /* init AHB rx_blk_size */
39 }
40
41 /**
42 * @brief Initializes the SDIO registers according to the specified parameters
43 * in SDIO_InitStruct.
44 * @param SDIO_InitStruct: pointer to a SDIO_InitTypeDef structure that contains
45 * the configuration information for the SDIO peripheral.
46 * @retval none
47 */
48
SDIO_Init(SDIO_InitTypeDef * SDIOInit_Struct)49 void SDIO_Init(SDIO_InitTypeDef* SDIOInit_Struct)
50 {
51 u16 Temp = 0;
52
53 /* Reset SDIO DMA */
54 HAL_SDIO_WRITE8(REG_SPDIO_CPU_RST_DMA, BIT_CPU_RST_SDIO_DMA);
55
56 /* initial TX BD */
57 HAL_SDIO_WRITE32(REG_SPDIO_TXBD_ADDR, SDIOInit_Struct->TXBD_BAR);
58 HAL_SDIO_WRITE16(REG_SPDIO_TXBD_SIZE, SDIOInit_Struct->TXBD_RING_SIZE);
59
60 /* Set TX_BUFF_UNIT_SIZE */
61 HAL_SDIO_WRITE8(REG_SPDIO_TX_BUF_UNIT_SZ, SDIOInit_Struct->TX_BUFFER_SIZE);
62
63 /* Set DISPATCH_TXAGG_PKT */
64 HAL_SDIO_WRITE32(REG_SPDIO_AHB_DMA_CTRL, HAL_SDIO_READ32(REG_SPDIO_AHB_DMA_CTRL)|BIT31);
65
66 /* Reset HW TX BD pointer */
67 HAL_SDIO_WRITE32(REG_SPDIO_TXBD_RPTR, HAL_SDIO_READ32(REG_SPDIO_TXBD_WPTR));
68
69 /* Init RX BD and RX Buffer */
70 HAL_SDIO_WRITE32(REG_SPDIO_RXBD_ADDR, SDIOInit_Struct->RXBD_BAR);
71 HAL_SDIO_WRITE16(REG_SPDIO_RXBD_SIZE, SDIOInit_Struct->RXBD_RING_SIZE);
72
73 /* Reset HW RX BD pointer */
74 HAL_SDIO_WRITE16(REG_SPDIO_RXBD_C2H_WPTR, HAL_SDIO_READ16(REG_SPDIO_RXBD_C2H_RPTR));
75
76 /* Set the threshold of free RX BD count to trigger interrupt */
77 HAL_SDIO_WRITE16(REG_SPDIO_RX_BD_FREE_CNT, SDIOInit_Struct->RXBD_FREE_TH);
78
79 /* Indicate Host this is a iNIC FW */
80 Temp = HAL_SDIO_READ16(REG_SPDIO_CCPWM2);
81 Temp |= CPWM2_INIC_FW_RDY_BIT;
82 Temp ^= CPWM2_TOGGLE_BIT;
83 HAL_SDIO_WRITE16(REG_SPDIO_CCPWM2, Temp);
84 }
85
86 /**
87 * @brief SDIO interrupt clear
88 * @note clear all interrupt of SDIO
89 * @retval None
90 */
91
SDIO_INTClear(void)92 void SDIO_INTClear(void)
93 {
94 u16 IntStatus;
95
96 IntStatus = HAL_SDIO_READ16(REG_SPDIO_CPU_INT_STAS);
97 HAL_SDIO_WRITE16(REG_SPDIO_CPU_INT_STAS, IntStatus); // clean the ISR
98 }
99
100 /**
101 * @brief SDIO disable or enable interrupt by modify the interrupt mask
102 * @param IntMask: The bit map to enable the interrupt.
103 * This parameter can be one or combinations of the following values:
104 * @arg BIT_TXFIFO_H2C_OVF:
105 * @arg BIT_H2C_BUS_RES_FAIL:
106 * @arg BIT_H2C_DMA_OK:
107 * @arg BIT_C2H_DMA_OK:
108 * @arg BIT_H2C_MSG_INT:
109 * @arg BIT_RPWM1_INT:
110 * @arg BIT_RPWM2_INT:
111 * @arg BIT_SDIO_RST_CMD_INT:
112 * @arg BIT_RXBD_FLAG_ERR_INT:
113 * @arg BIT_RX_BD_AVAI_INT:
114 * @arg BIT_HOST_WAKE_CPU_INT:
115 * @param NewState: ENABLE or DISABLE.
116 * @retval None
117 */
118
SDIO_INTConfig(u16 IntMask,u32 NewState)119 VOID SDIO_INTConfig(u16 IntMask, u32 NewState)
120 {
121 u16 IntMaskTmp = HAL_SDIO_READ16(REG_SPDIO_CPU_INT_MASK);
122
123 if (NewState == ENABLE) {
124 IntMaskTmp |= IntMask;
125 } else {
126 IntMaskTmp &= ~IntMask;
127 }
128
129 HAL_SDIO_WRITE16(REG_SPDIO_CPU_INT_MASK, IntMaskTmp);
130 }
131
132 /**
133 * @brief Get RPWM1 from host.
134 * @param none.
135 * @retval RPWM1 val.
136 */
137
SDIO_RPWM1_Get(void)138 u8 SDIO_RPWM1_Get(void)
139 {
140 return HAL_SDIO_READ8(REG_SPDIO_CRPWM);
141 }
142
143 /**
144 * @brief Get RPWM2 from host.
145 * @param none.
146 * @retval RPWM2 val.
147 */
148
SDIO_RPWM2_Get(void)149 u16 SDIO_RPWM2_Get(void)
150 {
151 return HAL_SDIO_READ16(REG_SPDIO_CRPWM2);
152 }
153
154 /**
155 * @brief Set CPWM1 to host
156 * @param Val: CPWM msg to send.
157 * @retval None
158 */
159
SDIO_CPWM1_Set(u8 Val)160 void SDIO_CPWM1_Set(u8 Val)
161 {
162 u8 Temp = HAL_SDIO_READ8(REG_SPDIO_CCPWM);
163
164 Temp ^= CPWM1_TOGGLE_BIT;
165 Temp |= Val;
166
167 HAL_SDIO_WRITE8(REG_SPDIO_CCPWM, Temp);
168 }
169
170 /**
171 * @brief Set CPWM2 to host
172 * @param Val: CPWM msg to send.
173 * @param Newstate: DISABLE/ENABLE.
174 * @retval None
175 */
176
SDIO_CPWM2_Set(u16 Val,u32 Newstate)177 void SDIO_CPWM2_Set(u16 Val, u32 Newstate)
178 {
179 u16 Temp = HAL_SDIO_READ16(REG_SPDIO_CCPWM2);
180
181 Temp ^= CPWM2_TOGGLE_BIT;
182
183 if (Newstate == ENABLE)
184 Temp |= Val;
185 else
186 Temp &= ~Val;
187
188 HAL_SDIO_WRITE16(REG_SPDIO_CCPWM2, Temp);
189 }
190
191 /**
192 * @brief Get RXBD read pointer, updated by SDIO IP.
193 * @param none
194 * @retval RXBD read pointer
195 */
196
SDIO_RXBD_RPTR_Get(void)197 u16 SDIO_RXBD_RPTR_Get(void)
198 {
199 return HAL_SDIO_READ16(REG_SPDIO_RXBD_C2H_RPTR);
200 }
201
202 /**
203 * @brief Set RXBD write pointer, updated by cpu CM4 driver.
204 * @param Val: RXBD write pointer
205 * @retval none
206 */
207
SDIO_RXBD_WPTR_Set(u16 Val)208 void SDIO_RXBD_WPTR_Set(u16 Val)
209 {
210 HAL_SDIO_WRITE16(REG_SPDIO_RXBD_C2H_WPTR, Val);
211 }
212
213 /**
214 * @brief Get TXBD write pointer, updated by SDIO IP.
215 * @param none
216 * @retval TXBD write pointer
217 */
218
SDIO_TXBD_WPTR_Get(void)219 u16 SDIO_TXBD_WPTR_Get(void)
220 {
221 return HAL_SDIO_READ16(REG_SPDIO_TXBD_WPTR);
222 }
223
224 /**
225 * @brief Set TXBD read pointer, updated by CM4 driver.
226 * @param none
227 * @retval TXBD read pointer
228 */
229
SDIO_TXBD_RPTR_Set(u16 Val)230 void SDIO_TXBD_RPTR_Set(u16 Val)
231 {
232 HAL_SDIO_WRITE16(REG_SPDIO_TXBD_RPTR, Val);
233 }
234
235 /**
236 * @brief Reset SDIO DMA.
237 * @param none
238 * @retval TXBD read pointer
239 */
240
SDIO_DMA_Reset(void)241 void SDIO_DMA_Reset(void)
242 {
243 HAL_SDIO_WRITE8(REG_SPDIO_CPU_RST_DMA, BIT_CPU_RST_SDIO_DMA);
244 }
245
246 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
247