1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2019 Broadcom. 4 */ 5 6 #ifndef PLATFORM_CONFIG_H 7 #define PLATFORM_CONFIG_H 8 9 #include <mm/generic_ram_layout.h> 10 11 #define STACK_ALIGNMENT 64 12 13 #define CONSOLE_UART_CLK_IN_HZ 25000000 14 #define CONSOLE_BAUDRATE 115200 15 16 #define CONSOLE_UART_BASE 0x68a10000 17 18 #define GICD_BASE 0x63c00000 19 20 #define SMBUS0_BASE 0x689b0000 21 #define SMBUS0_END (SMBUS0_BASE + 0xB0) 22 23 #define SECURE_GPIO_BASE0 0x68b00000 24 #define ASIU_GPIO_INTR 190 25 #define GPIO_NUM_START0 0 26 #define NUM_GPIOS0 151 27 28 #define CHIP_SECURE_GPIO_CONTROL0_BASE 0x68b60000 29 30 #define SPI_0_BASE 0x68a80000 31 #define SPI_0_END (SPI_0_BASE + 0x1000) 32 #define SPI_0_CLK_HZ 175000000 33 #define SPI_0_CS_MUX_PAD 0x68a40490 34 35 #define HWRNG_BASE 0x68b20000 36 #define HWRNG_END (HWRNG_BASE + 0x28) 37 38 #define SOTP_BASE 0x68b50000 39 40 /* NO ECC bits are present from ROW_0 to ROW_20, i.e Section 0 to Section 3 */ 41 #define SOTP_NO_ECC_ROWS 20 42 43 /* Secure Watch Dog */ 44 #define SEC_WDT_BASE 0x68B30000 45 #define SEC_WDT_END (SEC_WDT_BASE + 0x1000) 46 #define SEC_WDT_CLK_HZ 12500000 47 #define SEC_WDT_INTR 192 48 49 #define BNXT_BASE 0x60800000 50 51 #define QSPI_MEM_BASE 0x70000000 52 53 /* device memory ranges */ 54 #define BCM_DEVICE0_BASE GICD_BASE 55 #define BCM_DEVICE0_SIZE CORE_MMU_PGDIR_SIZE 56 #define BCM_DEVICE1_BASE SMBUS0_BASE 57 #define BCM_DEVICE1_SIZE CORE_MMU_PGDIR_SIZE 58 #define BCM_DEVICE4_BASE BNXT_BASE 59 #define BCM_DEVICE4_SIZE 0x800000 60 #define BCM_DEVICE5_BASE QSPI_MEM_BASE 61 #define BCM_DEVICE5_SIZE 0x800000 62 63 /* NS DDR ranges */ 64 #define BCM_DRAM0_NS_BASE 0x80000000 65 #define BCM_DRAM0_NS_SIZE 0xae00000 66 #define BCM_DRAM1_NS_BASE 0x90000000 67 #define BCM_DRAM1_NS_SIZE 0x70000000 68 #define BCM_DRAM2_NS_BASE 0x880100000 69 #define BCM_DRAM2_NS_SIZE 0x17ff00000 70 71 /* Secure DDR ranges */ 72 #define BCM_DRAM0_SEC_BASE 0x8ae00000 73 #define BCM_DRAM0_SEC_SIZE 0x2200000 74 75 #endif /*PLATFORM_CONFIG_H*/ 76