1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #ifndef __RTW_TX_H_
6 #define __RTW_TX_H_
7
8 #define RTK_TX_MAX_AGG_NUM_MASK 0x1f
9
10 #define RTW_TX_PROBE_TIMEOUT msecs_to_jiffies(500)
11
12 #define SET_TX_DESC_TXPKTSIZE(txdesc, value) \
13 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, GENMASK(15, 0))
14 #define SET_TX_DESC_OFFSET(txdesc, value) \
15 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, GENMASK(23, 16))
16 #define SET_TX_DESC_PKT_OFFSET(txdesc, value) \
17 le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(28, 24))
18 #define SET_TX_DESC_QSEL(txdesc, value) \
19 le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(12, 8))
20 #define SET_TX_DESC_BMC(txdesc, value) \
21 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, BIT(24))
22 #define SET_TX_DESC_RATE_ID(txdesc, value) \
23 le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(20, 16))
24 #define SET_TX_DESC_DATARATE(txdesc, value) \
25 le32p_replace_bits((__le32 *)(txdesc) + 0x04, value, GENMASK(6, 0))
26 #define SET_TX_DESC_DISDATAFB(txdesc, value) \
27 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(10))
28 #define SET_TX_DESC_USE_RATE(txdesc, value) \
29 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(8))
30 #define SET_TX_DESC_SEC_TYPE(txdesc, value) \
31 le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(23, 22))
32 #define SET_TX_DESC_DATA_BW(txdesc, value) \
33 le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, GENMASK(6, 5))
34 #define SET_TX_DESC_SW_SEQ(txdesc, value) \
35 le32p_replace_bits((__le32 *)(txdesc) + 0x09, value, GENMASK(23, 12))
36 #define SET_TX_DESC_TIM_EN(txdesc, value) \
37 le32p_replace_bits((__le32 *)(txdesc) + 0x09, value, BIT(7))
38 #define SET_TX_DESC_TIM_OFFSET(txdesc, value) \
39 le32p_replace_bits((__le32 *)(txdesc) + 0x09, value, GENMASK(6, 0))
40 #define SET_TX_DESC_MAX_AGG_NUM(txdesc, value) \
41 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, GENMASK(21, 17))
42 #define SET_TX_DESC_USE_RTS(tx_desc, value) \
43 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(12))
44 #define SET_TX_DESC_RTSRATE(txdesc, value) \
45 le32p_replace_bits((__le32 *)(txdesc) + 0x04, value, GENMASK(28, 24))
46 #define SET_TX_DESC_DATA_RTS_SHORT(txdesc, value) \
47 le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, BIT(12))
48 #define SET_TX_DESC_AMPDU_DENSITY(txdesc, value) \
49 le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, GENMASK(22, 20))
50 #define SET_TX_DESC_DATA_STBC(txdesc, value) \
51 le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, GENMASK(9, 8))
52 #define SET_TX_DESC_DATA_LDPC(txdesc, value) \
53 le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, BIT(7))
54 #define SET_TX_DESC_AGG_EN(txdesc, value) \
55 le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, BIT(12))
56 #define SET_TX_DESC_LS(txdesc, value) \
57 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, BIT(26))
58 #define SET_TX_DESC_DATA_SHORT(txdesc, value) \
59 le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, BIT(4))
60 #define SET_TX_DESC_SPE_RPT(tx_desc, value) \
61 le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, BIT(19))
62 #define SET_TX_DESC_SW_DEFINE(tx_desc, value) \
63 le32p_replace_bits((__le32 *)(txdesc) + 0x06, value, GENMASK(11, 0))
64 #define SET_TX_DESC_DISQSELSEQ(txdesc, value) \
65 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, BIT(31))
66 #define SET_TX_DESC_EN_HWSEQ(txdesc, value) \
67 le32p_replace_bits((__le32 *)(txdesc) + 0x08, value, BIT(15))
68 #define SET_TX_DESC_HW_SSN_SEL(txdesc, value) \
69 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, GENMASK(7, 6))
70 #define SET_TX_DESC_NAVUSEHDR(txdesc, value) \
71 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(15))
72 #define SET_TX_DESC_BT_NULL(txdesc, value) \
73 le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, BIT(23))
74 #define SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) \
75 le32p_replace_bits((__le32 *)(txdesc) + 0x07, value, GENMASK(15, 0))
76 #define SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) \
77 le32p_replace_bits((__le32 *)(txdesc) + 0x07, value, GENMASK(31, 24))
78 #define GET_TX_DESC_PKT_OFFSET(txdesc) \
79 le32_get_bits(*((__le32 *)(txdesc) + 0x01), GENMASK(28, 24))
80 #define GET_TX_DESC_QSEL(txdesc) \
81 le32_get_bits(*((__le32 *)(txdesc) + 0x01), GENMASK(12, 8))
82
83 enum rtw_tx_desc_queue_select {
84 TX_DESC_QSEL_TID0 = 0,
85 TX_DESC_QSEL_TID1 = 1,
86 TX_DESC_QSEL_TID2 = 2,
87 TX_DESC_QSEL_TID3 = 3,
88 TX_DESC_QSEL_TID4 = 4,
89 TX_DESC_QSEL_TID5 = 5,
90 TX_DESC_QSEL_TID6 = 6,
91 TX_DESC_QSEL_TID7 = 7,
92 TX_DESC_QSEL_TID8 = 8,
93 TX_DESC_QSEL_TID9 = 9,
94 TX_DESC_QSEL_TID10 = 10,
95 TX_DESC_QSEL_TID11 = 11,
96 TX_DESC_QSEL_TID12 = 12,
97 TX_DESC_QSEL_TID13 = 13,
98 TX_DESC_QSEL_TID14 = 14,
99 TX_DESC_QSEL_TID15 = 15,
100 TX_DESC_QSEL_BEACON = 16,
101 TX_DESC_QSEL_HIGH = 17,
102 TX_DESC_QSEL_MGMT = 18,
103 TX_DESC_QSEL_H2C = 19,
104 };
105
106 enum rtw_rsvd_packet_type;
107
108 void rtw_tx(struct rtw_dev *rtwdev,
109 struct ieee80211_tx_control *control,
110 struct sk_buff *skb);
111 void rtw_txq_init(struct rtw_dev *rtwdev, struct ieee80211_txq *txq);
112 void rtw_txq_cleanup(struct rtw_dev *rtwdev, struct ieee80211_txq *txq);
113 void rtw_tx_work(struct work_struct *w);
114 void rtw_tx_pkt_info_update(struct rtw_dev *rtwdev,
115 struct rtw_tx_pkt_info *pkt_info,
116 struct ieee80211_sta *sta,
117 struct sk_buff *skb);
118 void rtw_tx_fill_tx_desc(struct rtw_tx_pkt_info *pkt_info, struct sk_buff *skb);
119 void rtw_tx_report_enqueue(struct rtw_dev *rtwdev, struct sk_buff *skb, u8 sn);
120 void rtw_tx_report_handle(struct rtw_dev *rtwdev, struct sk_buff *skb, int src);
121 void rtw_tx_rsvd_page_pkt_info_update(struct rtw_dev *rtwdev,
122 struct rtw_tx_pkt_info *pkt_info,
123 struct sk_buff *skb,
124 enum rtw_rsvd_packet_type type);
125 struct sk_buff *
126 rtw_tx_write_data_rsvd_page_get(struct rtw_dev *rtwdev,
127 struct rtw_tx_pkt_info *pkt_info,
128 u8 *buf, u32 size);
129 struct sk_buff *
130 rtw_tx_write_data_h2c_get(struct rtw_dev *rtwdev,
131 struct rtw_tx_pkt_info *pkt_info,
132 u8 *buf, u32 size);
133
134 enum rtw_tx_queue_type rtw_tx_ac_to_hwq(enum ieee80211_ac_numbers ac);
135 enum rtw_tx_queue_type rtw_tx_queue_mapping(struct sk_buff *skb);
136
137 static inline
fill_txdesc_checksum_common(u8 * txdesc,size_t words)138 void fill_txdesc_checksum_common(u8 *txdesc, size_t words)
139 {
140 __le16 chksum = 0;
141 __le16 *data = (__le16 *)(txdesc);
142
143 SET_TX_DESC_TXDESC_CHECKSUM(txdesc, 0x0000);
144
145 while (words--)
146 chksum ^= *data++;
147
148 SET_TX_DESC_TXDESC_CHECKSUM(txdesc, __le16_to_cpu(chksum));
149 }
150
rtw_tx_fill_txdesc_checksum(struct rtw_dev * rtwdev,struct rtw_tx_pkt_info * pkt_info,u8 * txdesc)151 static inline void rtw_tx_fill_txdesc_checksum(struct rtw_dev *rtwdev,
152 struct rtw_tx_pkt_info *pkt_info,
153 u8 *txdesc)
154 {
155 const struct rtw_chip_info *chip = rtwdev->chip;
156
157 chip->ops->fill_txdesc_checksum(rtwdev, pkt_info, txdesc);
158 }
159
160 #endif
161