1 /* 2 * Copyright (c) 2015 Brian Swetland 3 * 4 * Use of this source code is governed by a MIT-style 5 * license that can be found in the LICENSE file or at 6 * https://opensource.org/licenses/MIT 7 */ 8 9 #pragma once 10 11 #define SGPIO_OUT_CFG(n) (0x40101000 + ((n) * 4)) 12 #define CFG_OUT_M1 0x00 13 #define CFG_OUT_M2A 0x01 14 #define CFG_OUT_M2B 0x02 15 #define CFG_OUT_M2C 0x03 16 #define CFG_OUT_GPIO 0x04 17 #define CFG_OUT_M4A 0x05 18 #define CFG_OUT_M4B 0x06 19 #define CFG_OUT_M4C 0x07 20 #define CFG_OUT_CLK 0x08 21 #define CFG_OUT_M8A 0x09 22 #define CFG_OUT_M8B 0x0A 23 #define CFG_OUT_M8C 0x0B 24 #define CFG_OE_GPIO 0x00 25 #define CFG_OE_M1 0x40 26 #define CFG_OE_M2 0x50 27 #define CFG_OE_M4 0x60 28 #define CFG_OE_M8 0x70 29 30 #define SLICE_CFG1(n) (0x40101040 + ((n) * 4)) 31 #define CLK_USE_SLICE (0 << 0) 32 #define CLK_USE_PIN (1 << 0) 33 #define CLK_PIN_SGPIO8 (0 << 1) 34 #define CLK_PIN_SGPIO9 (1 << 1) 35 #define CLK_PIN_SGPIO10 (2 << 1) 36 #define CLK_PIN_SGPIO11 (3 << 1) 37 #define CLK_SLICE_D (0 << 3) 38 #define CLK_SLICE_H (1 << 3) 39 #define CLK_SLICE_O (2 << 3) 40 #define CLK_SLICE_P (3 << 3) 41 #define QUAL_ENABLE (0 << 5) 42 #define QUAL_DISABLE (1 << 5) 43 #define QUAL_USE_SLICE (2 << 5) 44 #define QUAL_USE_PIN (3 << 5) 45 #define QUAL_PIN_SGPIO8 (0 << 7) 46 #define QUAL_PIN_SGPIO9 (1 << 7) 47 #define QUAL_PIN_SGPIO10 (2 << 7) 48 #define QUAL_PIN_SGPIO11 (3 << 7) 49 #define QUAL_SLICE_A (0 << 9) // D for SLICE A 50 #define QUAL_SLICE_H (1 << 9) // O for SLICE H 51 #define QUAL_SLICE_I (2 << 9) // D for SLICE I 52 #define QUAL_SLICE_P (3 << 9) // O for SLICE P 53 #define CONCAT_PIN (0 << 11) 54 #define CONCAT_SLICE (1 << 11) 55 #define CONCAT_LOOP (0 << 12) 56 #define CONCAT_2_SLICE (1 << 12) 57 #define CONCAT_4_SLICE (2 << 12) 58 #define CONCAT_8_SLICE (3 << 12) 59 60 #define SLICE_CFG2(n) (0x40101080 + ((n) * 4)) 61 #define MATCH_MODE (1 << 0) 62 #define CLK_GEN_INTERNAL (0 << 2) // from COUNTER 63 #define CLK_GEN_EXTERNAL (1 << 2) // from PIN or SLICE 64 #define INV_CLK_OUT (1 << 3) 65 #define SHIFT_1BPC (0 << 6) 66 #define SHIFT_2BPC (1 << 6) 67 #define SHIFT_4BPC (2 << 6) 68 #define SHIFT_8BPC (3 << 6) 69 #define INVERT_QUALIFIER (1 << 8) 70 71 #define SLICE_REG(n) (0x401010C0 + ((n) * 4)) // main shift reg 72 #define SLICE_SHADOW(n) (0x40101100 + ((n) * 4)) // swapped @ POS underflow 73 #define SLICE_PRESET(n) (0x40101140 + ((n) * 4)) // 12bit -> COUNT @ 0 74 #define SLICE_COUNT(n) (0x40101180 + ((n) * 4)) // 12 bit downcount 75 #define SLICE_POS(n) (0x401011C0 + ((n) * 4)) 76 #define POS_POS(n) ((n) << 0) // value at start 77 #define POS_RESET(n) ((n) << 8) // load at underflow 78 79 #define SGPIO_IN (0x40101210) 80 #define SGPIO_OUT (0x40101214) 81 #define SGPIO_OEN (0x40101218) 82 #define SLICE_CTRL_ENABLE (0x4010121C) 83 #define SLICE_CTRL_DISABLE (0x40101220) 84 #define SLICE_XHG_STS (0x40101F2C) 85 #define SLICE_XHG_STS_CLR (0x40101F30) 86 #define SLICE_XHG_STS_SET (0x40101F34) 87 88 #define SLC_A 0 89 #define SLC_B 1 90 #define SLC_C 2 91 #define SLC_D 3 92 #define SLC_E 4 93 #define SLC_F 5 94 #define SLC_G 6 95 #define SLC_H 7 96 #define SLC_I 8 97 #define SLC_J 9 98 #define SLC_K 10 99 #define SLC_L 11 100 #define SLC_M 12 101 #define SLC_N 13 102 #define SLC_O 14 103 #define SLC_P 15 104 105